diff options
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/Makefile | 8 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/linux/vgpu/vgpu_ivm.c | 15 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/css_gr_gk20a.c | 27 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/vgpu/vgpu_ivm.h | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/css_vgpu.c (renamed from drivers/gpu/nvgpu/common/linux/vgpu/css_vgpu.c) | 53 |
6 files changed, 73 insertions, 40 deletions
diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index 9f58d6ef..e219df98 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile | |||
@@ -95,6 +95,8 @@ nvgpu-y += \ | |||
95 | common/clock_gating/gp10b_gating_reglist.o \ | 95 | common/clock_gating/gp10b_gating_reglist.o \ |
96 | common/clock_gating/gv100_gating_reglist.o \ | 96 | common/clock_gating/gv100_gating_reglist.o \ |
97 | common/clock_gating/gv11b_gating_reglist.o \ | 97 | common/clock_gating/gv11b_gating_reglist.o \ |
98 | common/sim.o \ | ||
99 | common/sim_pci.o \ | ||
98 | gk20a/gk20a.o \ | 100 | gk20a/gk20a.o \ |
99 | gk20a/ce2_gk20a.o \ | 101 | gk20a/ce2_gk20a.o \ |
100 | gk20a/fifo_gk20a.o \ | 102 | gk20a/fifo_gk20a.o \ |
@@ -133,9 +135,7 @@ nvgpu-y += \ | |||
133 | boardobj/boardobjgrp.o \ | 135 | boardobj/boardobjgrp.o \ |
134 | boardobj/boardobjgrpmask.o \ | 136 | boardobj/boardobjgrpmask.o \ |
135 | boardobj/boardobjgrp_e255.o \ | 137 | boardobj/boardobjgrp_e255.o \ |
136 | boardobj/boardobjgrp_e32.o \ | 138 | boardobj/boardobjgrp_e32.o |
137 | common/sim.o \ | ||
138 | common/sim_pci.o | ||
139 | 139 | ||
140 | nvgpu-$(CONFIG_GK20A_VIDMEM) += \ | 140 | nvgpu-$(CONFIG_GK20A_VIDMEM) += \ |
141 | common/mm/vidmem.o \ | 141 | common/mm/vidmem.o \ |
@@ -192,6 +192,7 @@ nvgpu-$(CONFIG_TEGRA_GR_VIRTUALIZATION) += \ | |||
192 | vgpu/vgpu.o \ | 192 | vgpu/vgpu.o \ |
193 | vgpu/dbg_vgpu.o \ | 193 | vgpu/dbg_vgpu.o \ |
194 | vgpu/tsg_vgpu.o \ | 194 | vgpu/tsg_vgpu.o \ |
195 | vgpu/css_vgpu.o \ | ||
195 | vgpu/gm20b/vgpu_gr_gm20b.o \ | 196 | vgpu/gm20b/vgpu_gr_gm20b.o \ |
196 | vgpu/gp10b/vgpu_hal_gp10b.o \ | 197 | vgpu/gp10b/vgpu_hal_gp10b.o \ |
197 | vgpu/gp10b/vgpu_gr_gp10b.o \ | 198 | vgpu/gp10b/vgpu_gr_gp10b.o \ |
@@ -206,7 +207,6 @@ nvgpu-$(CONFIG_TEGRA_GR_VIRTUALIZATION) += \ | |||
206 | common/linux/vgpu/platform_vgpu_tegra.o \ | 207 | common/linux/vgpu/platform_vgpu_tegra.o \ |
207 | common/linux/vgpu/fecs_trace_vgpu.o \ | 208 | common/linux/vgpu/fecs_trace_vgpu.o \ |
208 | common/linux/vgpu/clk_vgpu.o \ | 209 | common/linux/vgpu/clk_vgpu.o \ |
209 | common/linux/vgpu/css_vgpu.o \ | ||
210 | common/linux/vgpu/sysfs_vgpu.o \ | 210 | common/linux/vgpu/sysfs_vgpu.o \ |
211 | common/linux/vgpu/vgpu_ivc.o \ | 211 | common/linux/vgpu/vgpu_ivc.o \ |
212 | common/linux/vgpu/vgpu_ivm.o \ | 212 | common/linux/vgpu/vgpu_ivm.o \ |
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/vgpu_ivm.c b/drivers/gpu/nvgpu/common/linux/vgpu/vgpu_ivm.c index 82475cac..90089de8 100644 --- a/drivers/gpu/nvgpu/common/linux/vgpu/vgpu_ivm.c +++ b/drivers/gpu/nvgpu/common/linux/vgpu/vgpu_ivm.c | |||
@@ -15,8 +15,11 @@ | |||
15 | */ | 15 | */ |
16 | 16 | ||
17 | #include <nvgpu/vgpu/vgpu_ivm.h> | 17 | #include <nvgpu/vgpu/vgpu_ivm.h> |
18 | |||
18 | #include <linux/tegra-ivc.h> | 19 | #include <linux/tegra-ivc.h> |
19 | 20 | ||
21 | #include "common/linux/os_linux.h" | ||
22 | |||
20 | struct tegra_hv_ivm_cookie *vgpu_ivm_mempool_reserve(unsigned int id) | 23 | struct tegra_hv_ivm_cookie *vgpu_ivm_mempool_reserve(unsigned int id) |
21 | { | 24 | { |
22 | return tegra_hv_mempool_reserve(id); | 25 | return tegra_hv_mempool_reserve(id); |
@@ -36,3 +39,15 @@ u64 vgpu_ivm_get_size(struct tegra_hv_ivm_cookie *cookie) | |||
36 | { | 39 | { |
37 | return cookie->size; | 40 | return cookie->size; |
38 | } | 41 | } |
42 | |||
43 | void *vgpu_ivm_mempool_map(struct tegra_hv_ivm_cookie *cookie) | ||
44 | { | ||
45 | return ioremap_cache(vgpu_ivm_get_ipa(cookie), | ||
46 | vgpu_ivm_get_size(cookie)); | ||
47 | } | ||
48 | |||
49 | void vgpu_ivm_mempool_unmap(struct tegra_hv_ivm_cookie *cookie, | ||
50 | void *addr) | ||
51 | { | ||
52 | iounmap(addr); | ||
53 | } | ||
diff --git a/drivers/gpu/nvgpu/gk20a/css_gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/css_gr_gk20a.c index 764ffe1a..6fd0d330 100644 --- a/drivers/gpu/nvgpu/gk20a/css_gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/css_gr_gk20a.c | |||
@@ -453,15 +453,24 @@ static int css_gr_create_client_data(struct gk20a *g, | |||
453 | u32 perfmon_count, | 453 | u32 perfmon_count, |
454 | struct gk20a_cs_snapshot_client *cur) | 454 | struct gk20a_cs_snapshot_client *cur) |
455 | { | 455 | { |
456 | memset(cur->snapshot, 0, sizeof(*cur->snapshot)); | 456 | /* |
457 | cur->snapshot->start = sizeof(*cur->snapshot); | 457 | * Special handling in-case of rm-server |
458 | /* we should be ensure that can fit all fifo entries here */ | 458 | * |
459 | cur->snapshot->end = | 459 | * client snapshot buffer will not be mapped |
460 | CSS_FIFO_ENTRY_CAPACITY(cur->snapshot_size) | 460 | * in-case of rm-server its only mapped in |
461 | * sizeof(struct gk20a_cs_snapshot_fifo_entry) | 461 | * guest side |
462 | + sizeof(struct gk20a_cs_snapshot_fifo); | 462 | */ |
463 | cur->snapshot->get = cur->snapshot->start; | 463 | if (cur->snapshot) { |
464 | cur->snapshot->put = cur->snapshot->start; | 464 | memset(cur->snapshot, 0, sizeof(*cur->snapshot)); |
465 | cur->snapshot->start = sizeof(*cur->snapshot); | ||
466 | /* we should be ensure that can fit all fifo entries here */ | ||
467 | cur->snapshot->end = | ||
468 | CSS_FIFO_ENTRY_CAPACITY(cur->snapshot_size) | ||
469 | * sizeof(struct gk20a_cs_snapshot_fifo_entry) | ||
470 | + sizeof(struct gk20a_cs_snapshot_fifo); | ||
471 | cur->snapshot->get = cur->snapshot->start; | ||
472 | cur->snapshot->put = cur->snapshot->start; | ||
473 | } | ||
465 | 474 | ||
466 | cur->perfmon_count = perfmon_count; | 475 | cur->perfmon_count = perfmon_count; |
467 | 476 | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h b/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h index 3890249d..3e4372eb 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h +++ b/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h | |||
@@ -509,6 +509,12 @@ struct tegra_vgpu_constants_params { | |||
509 | u32 l2_en_mask[TEGRA_VGPU_L2_EN_MASK]; | 509 | u32 l2_en_mask[TEGRA_VGPU_L2_EN_MASK]; |
510 | }; | 510 | }; |
511 | 511 | ||
512 | enum { | ||
513 | TEGRA_VGPU_CYCLE_STATS_SNAPSHOT_CMD_FLUSH = 0, | ||
514 | TEGRA_VGPU_CYCLE_STATS_SNAPSHOT_CMD_ATTACH = 1, | ||
515 | TEGRA_VGPU_CYCLE_STATS_SNAPSHOT_CMD_DETACH = 2, | ||
516 | }; | ||
517 | |||
512 | struct tegra_vgpu_channel_cyclestats_snapshot_params { | 518 | struct tegra_vgpu_channel_cyclestats_snapshot_params { |
513 | u64 handle; | 519 | u64 handle; |
514 | u32 perfmon_start; | 520 | u32 perfmon_start; |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/vgpu/vgpu_ivm.h b/drivers/gpu/nvgpu/include/nvgpu/vgpu/vgpu_ivm.h index ba2cfc56..cecdd516 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/vgpu/vgpu_ivm.h +++ b/drivers/gpu/nvgpu/include/nvgpu/vgpu/vgpu_ivm.h | |||
@@ -31,5 +31,7 @@ struct tegra_hv_ivm_cookie *vgpu_ivm_mempool_reserve(unsigned int id); | |||
31 | int vgpu_ivm_mempool_unreserve(struct tegra_hv_ivm_cookie *cookie); | 31 | int vgpu_ivm_mempool_unreserve(struct tegra_hv_ivm_cookie *cookie); |
32 | u64 vgpu_ivm_get_ipa(struct tegra_hv_ivm_cookie *cookie); | 32 | u64 vgpu_ivm_get_ipa(struct tegra_hv_ivm_cookie *cookie); |
33 | u64 vgpu_ivm_get_size(struct tegra_hv_ivm_cookie *cookie); | 33 | u64 vgpu_ivm_get_size(struct tegra_hv_ivm_cookie *cookie); |
34 | 34 | void *vgpu_ivm_mempool_map(struct tegra_hv_ivm_cookie *cookie); | |
35 | void vgpu_ivm_mempool_unmap(struct tegra_hv_ivm_cookie *cookie, | ||
36 | void *addr); | ||
35 | #endif | 37 | #endif |
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/css_vgpu.c b/drivers/gpu/nvgpu/vgpu/css_vgpu.c index ba2bf58b..0e44b81a 100644 --- a/drivers/gpu/nvgpu/common/linux/vgpu/css_vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/css_vgpu.c | |||
@@ -1,51 +1,51 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * copy of this software and associated documentation files (the "Software"), |
6 | * version 2, as published by the Free Software Foundation. | 6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
7 | * | 10 | * |
8 | * This program is distributed in the hope it will be useful, but WITHOUT | 11 | * The above copyright notice and this permission notice shall be included in |
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | 12 | * all copies or substantial portions of the Software. |
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | 13 | * |
13 | * You should have received a copy of the GNU General Public License | 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
15 | */ | 21 | */ |
16 | #if defined(CONFIG_GK20A_CYCLE_STATS) | 22 | #if defined(CONFIG_GK20A_CYCLE_STATS) |
17 | 23 | ||
18 | #include <nvgpu/vgpu/vgpu_ivm.h> | 24 | #include <nvgpu/vgpu/vgpu_ivm.h> |
19 | #include <nvgpu/vgpu/tegra_vgpu.h> | ||
20 | #include <uapi/linux/nvgpu.h> | ||
21 | #include <nvgpu/vgpu/vgpu.h> | 25 | #include <nvgpu/vgpu/vgpu.h> |
26 | #include <nvgpu/vgpu/tegra_vgpu.h> | ||
27 | #include <nvgpu/dt.h> | ||
22 | 28 | ||
23 | #include "gk20a/gk20a.h" | 29 | #include "gk20a/gk20a.h" |
24 | #include "gk20a/channel_gk20a.h" | 30 | #include "gk20a/channel_gk20a.h" |
25 | #include "gk20a/css_gr_gk20a.h" | 31 | #include "gk20a/css_gr_gk20a.h" |
26 | #include "common/linux/platform_gk20a.h" | 32 | |
27 | #include "common/linux/os_linux.h" | ||
28 | #include "vgpu/css_vgpu.h" | 33 | #include "vgpu/css_vgpu.h" |
29 | 34 | ||
30 | static struct tegra_hv_ivm_cookie *css_cookie; | 35 | static struct tegra_hv_ivm_cookie *css_cookie; |
31 | 36 | ||
32 | static struct tegra_hv_ivm_cookie *vgpu_css_reserve_mempool(struct gk20a *g) | 37 | static struct tegra_hv_ivm_cookie *vgpu_css_reserve_mempool(struct gk20a *g) |
33 | { | 38 | { |
34 | struct device *dev = dev_from_gk20a(g); | ||
35 | struct device_node *np = dev->of_node; | ||
36 | struct of_phandle_args args; | ||
37 | struct tegra_hv_ivm_cookie *cookie; | 39 | struct tegra_hv_ivm_cookie *cookie; |
38 | u32 mempool; | 40 | u32 mempool; |
39 | int err; | 41 | int err; |
40 | 42 | ||
41 | err = of_parse_phandle_with_fixed_args(np, | 43 | err = nvgpu_dt_read_u32_index(g, "mempool-css", 1, &mempool); |
42 | "mempool-css", 1, 0, &args); | ||
43 | if (err) { | 44 | if (err) { |
44 | nvgpu_err(g, "dt missing mempool-css"); | 45 | nvgpu_err(g, "dt missing mempool-css"); |
45 | return ERR_PTR(err); | 46 | return ERR_PTR(err); |
46 | } | 47 | } |
47 | 48 | ||
48 | mempool = args.args[0]; | ||
49 | cookie = vgpu_ivm_mempool_reserve(mempool); | 49 | cookie = vgpu_ivm_mempool_reserve(mempool); |
50 | if (IS_ERR_OR_NULL(cookie)) { | 50 | if (IS_ERR_OR_NULL(cookie)) { |
51 | nvgpu_err(g, "mempool %u reserve failed", mempool); | 51 | nvgpu_err(g, "mempool %u reserve failed", mempool); |
@@ -103,9 +103,9 @@ static int vgpu_css_init_snapshot_buffer(struct gr_gk20a *gr) | |||
103 | goto fail; | 103 | goto fail; |
104 | } | 104 | } |
105 | 105 | ||
106 | buf = ioremap_cache(vgpu_ivm_get_ipa(css_cookie), size); | 106 | buf = vgpu_ivm_mempool_map(css_cookie); |
107 | if (!buf) { | 107 | if (!buf) { |
108 | nvgpu_info(g, "ioremap_cache failed"); | 108 | nvgpu_info(g, "vgpu_ivm_mempool_map failed"); |
109 | err = -EINVAL; | 109 | err = -EINVAL; |
110 | goto fail; | 110 | goto fail; |
111 | } | 111 | } |
@@ -130,7 +130,7 @@ void vgpu_css_release_snapshot_buffer(struct gr_gk20a *gr) | |||
130 | if (!data->hw_snapshot) | 130 | if (!data->hw_snapshot) |
131 | return; | 131 | return; |
132 | 132 | ||
133 | iounmap(data->hw_snapshot); | 133 | vgpu_ivm_mempool_unmap(css_cookie, data->hw_snapshot); |
134 | data->hw_snapshot = NULL; | 134 | data->hw_snapshot = NULL; |
135 | 135 | ||
136 | vgpu_ivm_mempool_unreserve(css_cookie); | 136 | vgpu_ivm_mempool_unreserve(css_cookie); |
@@ -155,7 +155,7 @@ int vgpu_css_flush_snapshots(struct channel_gk20a *ch, | |||
155 | msg.handle = vgpu_get_handle(g); | 155 | msg.handle = vgpu_get_handle(g); |
156 | p = &msg.params.cyclestats_snapshot; | 156 | p = &msg.params.cyclestats_snapshot; |
157 | p->handle = ch->virt_ctx; | 157 | p->handle = ch->virt_ctx; |
158 | p->subcmd = NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT_CMD_FLUSH; | 158 | p->subcmd = TEGRA_VGPU_CYCLE_STATS_SNAPSHOT_CMD_FLUSH; |
159 | p->buf_info = (uintptr_t)data->hw_get - (uintptr_t)data->hw_snapshot; | 159 | p->buf_info = (uintptr_t)data->hw_get - (uintptr_t)data->hw_snapshot; |
160 | 160 | ||
161 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | 161 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); |
@@ -182,7 +182,7 @@ static int vgpu_css_attach(struct channel_gk20a *ch, | |||
182 | msg.cmd = TEGRA_VGPU_CMD_CHANNEL_CYCLESTATS_SNAPSHOT; | 182 | msg.cmd = TEGRA_VGPU_CMD_CHANNEL_CYCLESTATS_SNAPSHOT; |
183 | msg.handle = vgpu_get_handle(g); | 183 | msg.handle = vgpu_get_handle(g); |
184 | p->handle = ch->virt_ctx; | 184 | p->handle = ch->virt_ctx; |
185 | p->subcmd = NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT_CMD_ATTACH; | 185 | p->subcmd = TEGRA_VGPU_CYCLE_STATS_SNAPSHOT_CMD_ATTACH; |
186 | p->perfmon_count = cs_client->perfmon_count; | 186 | p->perfmon_count = cs_client->perfmon_count; |
187 | 187 | ||
188 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | 188 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); |
@@ -209,7 +209,7 @@ int vgpu_css_detach(struct channel_gk20a *ch, | |||
209 | msg.cmd = TEGRA_VGPU_CMD_CHANNEL_CYCLESTATS_SNAPSHOT; | 209 | msg.cmd = TEGRA_VGPU_CMD_CHANNEL_CYCLESTATS_SNAPSHOT; |
210 | msg.handle = vgpu_get_handle(g); | 210 | msg.handle = vgpu_get_handle(g); |
211 | p->handle = ch->virt_ctx; | 211 | p->handle = ch->virt_ctx; |
212 | p->subcmd = NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT_CMD_DETACH; | 212 | p->subcmd = TEGRA_VGPU_CYCLE_STATS_SNAPSHOT_CMD_DETACH; |
213 | p->perfmon_start = cs_client->perfmon_start; | 213 | p->perfmon_start = cs_client->perfmon_start; |
214 | p->perfmon_count = cs_client->perfmon_count; | 214 | p->perfmon_count = cs_client->perfmon_count; |
215 | 215 | ||
@@ -233,4 +233,5 @@ int vgpu_css_enable_snapshot_buffer(struct channel_gk20a *ch, | |||
233 | ret = vgpu_css_init_snapshot_buffer(&ch->g->gr); | 233 | ret = vgpu_css_init_snapshot_buffer(&ch->g->gr); |
234 | return ret; | 234 | return ret; |
235 | } | 235 | } |
236 | |||
236 | #endif /* CONFIG_GK20A_CYCLE_STATS */ | 237 | #endif /* CONFIG_GK20A_CYCLE_STATS */ |