diff options
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/subctx_gv11b.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c index 05d7dee0..12a606bf 100644 --- a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c | |||
@@ -32,6 +32,7 @@ | |||
32 | 32 | ||
33 | #include <nvgpu/hw/gv11b/hw_ram_gv11b.h> | 33 | #include <nvgpu/hw/gv11b/hw_ram_gv11b.h> |
34 | #include <nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h> | 34 | #include <nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h> |
35 | #include <nvgpu/hw/gv11b/hw_gr_gv11b.h> | ||
35 | 36 | ||
36 | static void gv11b_subctx_commit_valid_mask(struct vm_gk20a *vm, | 37 | static void gv11b_subctx_commit_valid_mask(struct vm_gk20a *vm, |
37 | struct nvgpu_mem *inst_block); | 38 | struct nvgpu_mem *inst_block); |
@@ -170,12 +171,12 @@ void gv11b_subctx_commit_pdb(struct vm_gk20a *vm, | |||
170 | struct nvgpu_mem *inst_block) | 171 | struct nvgpu_mem *inst_block) |
171 | { | 172 | { |
172 | struct gk20a *g = gk20a_from_vm(vm); | 173 | struct gk20a *g = gk20a_from_vm(vm); |
173 | struct fifo_gk20a *f = &g->fifo; | ||
174 | u32 lo, hi; | 174 | u32 lo, hi; |
175 | u32 subctx_id = 0; | 175 | u32 subctx_id = 0; |
176 | u32 format_word; | 176 | u32 format_word; |
177 | u32 pdb_addr_lo, pdb_addr_hi; | 177 | u32 pdb_addr_lo, pdb_addr_hi; |
178 | u64 pdb_addr; | 178 | u64 pdb_addr; |
179 | u32 max_subctx_count = gr_pri_fe_chip_def_info_max_veid_count_init_v(); | ||
179 | u32 aperture = nvgpu_aperture_mask(g, vm->pdb.mem, | 180 | u32 aperture = nvgpu_aperture_mask(g, vm->pdb.mem, |
180 | ram_in_sc_page_dir_base_target_sys_mem_ncoh_v(), | 181 | ram_in_sc_page_dir_base_target_sys_mem_ncoh_v(), |
181 | ram_in_sc_page_dir_base_target_vid_mem_v()); | 182 | ram_in_sc_page_dir_base_target_vid_mem_v()); |
@@ -194,7 +195,7 @@ void gv11b_subctx_commit_pdb(struct vm_gk20a *vm, | |||
194 | ram_in_sc_page_dir_base_lo_0_f(pdb_addr_lo); | 195 | ram_in_sc_page_dir_base_lo_0_f(pdb_addr_lo); |
195 | nvgpu_log(g, gpu_dbg_info, " pdb info lo %x hi %x", | 196 | nvgpu_log(g, gpu_dbg_info, " pdb info lo %x hi %x", |
196 | format_word, pdb_addr_hi); | 197 | format_word, pdb_addr_hi); |
197 | for (subctx_id = 0; subctx_id < f->max_subctx_count; subctx_id++) { | 198 | for (subctx_id = 0; subctx_id < max_subctx_count; subctx_id++) { |
198 | lo = ram_in_sc_page_dir_base_vol_0_w() + (4 * subctx_id); | 199 | lo = ram_in_sc_page_dir_base_vol_0_w() + (4 * subctx_id); |
199 | hi = ram_in_sc_page_dir_base_hi_0_w() + (4 * subctx_id); | 200 | hi = ram_in_sc_page_dir_base_hi_0_w() + (4 * subctx_id); |
200 | nvgpu_mem_wr32(g, inst_block, lo, format_word); | 201 | nvgpu_mem_wr32(g, inst_block, lo, format_word); |