diff options
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_gk20a.h | 24 |
1 files changed, 21 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h index 3dd16ec4..e00991cb 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h | |||
@@ -49,7 +49,7 @@ | |||
49 | /* Mapping between AP_CTRLs and Idle counters */ | 49 | /* Mapping between AP_CTRLs and Idle counters */ |
50 | #define PMU_AP_IDLE_MASK_GRAPHICS (PMU_AP_IDLE_MASK_HIST_IDX_1) | 50 | #define PMU_AP_IDLE_MASK_GRAPHICS (PMU_AP_IDLE_MASK_HIST_IDX_1) |
51 | 51 | ||
52 | #define APP_VERSION_T186_0 19816464 | 52 | #define APP_VERSION_T186_0 19842227 |
53 | #define APP_VERSION_GM20B_4 19008461 | 53 | #define APP_VERSION_GM20B_4 19008461 |
54 | #define APP_VERSION_GM20B_3 18935575 | 54 | #define APP_VERSION_GM20B_3 18935575 |
55 | #define APP_VERSION_GM20B_2 18694072 | 55 | #define APP_VERSION_GM20B_2 18694072 |
@@ -337,6 +337,22 @@ struct pmu_mem_v2 { | |||
337 | u16 fb_size; | 337 | u16 fb_size; |
338 | }; | 338 | }; |
339 | 339 | ||
340 | struct pmu_mem_desc_v0 { | ||
341 | /*! | ||
342 | * Start address of memory surface that is being communicated to the falcon. | ||
343 | */ | ||
344 | u64 dma_addr; | ||
345 | /*! | ||
346 | * Max allowed DMA transfer size (size of the memory surface). Accesses past | ||
347 | * this point may result in page faults and/or memory corruptions. | ||
348 | */ | ||
349 | u16 dma_sizemax; | ||
350 | /*! | ||
351 | * DMA channel index to be used when accessing this surface. | ||
352 | */ | ||
353 | u8 dma_idx; | ||
354 | }; | ||
355 | |||
340 | struct pmu_dmem { | 356 | struct pmu_dmem { |
341 | u16 size; | 357 | u16 size; |
342 | u32 offset; | 358 | u32 offset; |
@@ -392,7 +408,7 @@ struct pmu_cmdline_args_v4 { | |||
392 | u8 secure_mode; | 408 | u8 secure_mode; |
393 | u8 raise_priv_sec; /*Raise priv level required for desired | 409 | u8 raise_priv_sec; /*Raise priv level required for desired |
394 | registers*/ | 410 | registers*/ |
395 | struct pmu_mem_v2 gc6_ctx; /* dmem offset of gc6 context */ | 411 | struct pmu_mem_desc_v0 gc6_ctx; /* dmem offset of gc6 context */ |
396 | u8 pad; | 412 | u8 pad; |
397 | }; | 413 | }; |
398 | 414 | ||
@@ -483,7 +499,7 @@ struct pmu_allocation_v1 { | |||
483 | struct pmu_allocation_v2 { | 499 | struct pmu_allocation_v2 { |
484 | struct { | 500 | struct { |
485 | struct pmu_dmem dmem; | 501 | struct pmu_dmem dmem; |
486 | struct pmu_mem_v2 fb; | 502 | struct pmu_mem_desc_v0 fb; |
487 | } alloc; | 503 | } alloc; |
488 | }; | 504 | }; |
489 | 505 | ||
@@ -1074,10 +1090,12 @@ struct pmu_sequence { | |||
1074 | union { | 1090 | union { |
1075 | struct pmu_allocation_v0 in_v0; | 1091 | struct pmu_allocation_v0 in_v0; |
1076 | struct pmu_allocation_v1 in_v1; | 1092 | struct pmu_allocation_v1 in_v1; |
1093 | struct pmu_allocation_v2 in_v2; | ||
1077 | }; | 1094 | }; |
1078 | union { | 1095 | union { |
1079 | struct pmu_allocation_v0 out_v0; | 1096 | struct pmu_allocation_v0 out_v0; |
1080 | struct pmu_allocation_v1 out_v1; | 1097 | struct pmu_allocation_v1 out_v1; |
1098 | struct pmu_allocation_v2 out_v2; | ||
1081 | }; | 1099 | }; |
1082 | u8 *out_payload; | 1100 | u8 *out_payload; |
1083 | pmu_callback callback; | 1101 | pmu_callback callback; |