diff options
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_gr_gm20b.c | 23 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_gr_gm20b.h | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_hal_gm20b.c | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/linux/vgpu/gr_vgpu.c | 65 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/linux/vgpu/gr_vgpu.h | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_hal_gv11b.c | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 11 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/gr_gv100.c | 8 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/gr_gv100.h | 4 |
12 files changed, 95 insertions, 45 deletions
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_gr_gm20b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_gr_gm20b.c index 260ce080..fc39b3f5 100644 --- a/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_gr_gm20b.c +++ b/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_gr_gm20b.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2015-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -40,24 +40,3 @@ void vgpu_gr_gm20b_init_cyclestats(struct gk20a *g) | |||
40 | #endif | 40 | #endif |
41 | } | 41 | } |
42 | 42 | ||
43 | int vgpu_gm20b_init_fs_state(struct gk20a *g) | ||
44 | { | ||
45 | struct gr_gk20a *gr = &g->gr; | ||
46 | u32 tpc_index, gpc_index; | ||
47 | u32 sm_id = 0; | ||
48 | |||
49 | gk20a_dbg_fn(""); | ||
50 | |||
51 | for (gpc_index = 0; gpc_index < gr->gpc_count; gpc_index++) { | ||
52 | for (tpc_index = 0; tpc_index < gr->gpc_tpc_count[gpc_index]; | ||
53 | tpc_index++) { | ||
54 | g->gr.sm_to_cluster[sm_id].tpc_index = tpc_index; | ||
55 | g->gr.sm_to_cluster[sm_id].gpc_index = gpc_index; | ||
56 | |||
57 | sm_id++; | ||
58 | } | ||
59 | } | ||
60 | |||
61 | gr->no_of_sm = sm_id; | ||
62 | return 0; | ||
63 | } | ||
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_gr_gm20b.h b/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_gr_gm20b.h index f17de450..77b83cbe 100644 --- a/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_gr_gm20b.h +++ b/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_gr_gm20b.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2015-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -20,6 +20,5 @@ | |||
20 | #include "gk20a/gk20a.h" | 20 | #include "gk20a/gk20a.h" |
21 | 21 | ||
22 | void vgpu_gr_gm20b_init_cyclestats(struct gk20a *g); | 22 | void vgpu_gr_gm20b_init_cyclestats(struct gk20a *g); |
23 | int vgpu_gm20b_init_fs_state(struct gk20a *g); | ||
24 | 23 | ||
25 | #endif | 24 | #endif |
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_hal_gm20b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_hal_gm20b.c index 74fa65f3..eeeccf62 100644 --- a/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_hal_gm20b.c +++ b/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_hal_gm20b.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2015-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -92,7 +92,7 @@ static const struct gpu_ops vgpu_gm20b_ops = { | |||
92 | .is_valid_compute_class = gr_gm20b_is_valid_compute_class, | 92 | .is_valid_compute_class = gr_gm20b_is_valid_compute_class, |
93 | .get_sm_dsm_perf_regs = gr_gm20b_get_sm_dsm_perf_regs, | 93 | .get_sm_dsm_perf_regs = gr_gm20b_get_sm_dsm_perf_regs, |
94 | .get_sm_dsm_perf_ctrl_regs = gr_gm20b_get_sm_dsm_perf_ctrl_regs, | 94 | .get_sm_dsm_perf_ctrl_regs = gr_gm20b_get_sm_dsm_perf_ctrl_regs, |
95 | .init_fs_state = vgpu_gm20b_init_fs_state, | 95 | .init_fs_state = vgpu_gr_init_fs_state, |
96 | .set_hww_esr_report_mask = gr_gm20b_set_hww_esr_report_mask, | 96 | .set_hww_esr_report_mask = gr_gm20b_set_hww_esr_report_mask, |
97 | .falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments, | 97 | .falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments, |
98 | .load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode, | 98 | .load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode, |
@@ -145,7 +145,7 @@ static const struct gpu_ops vgpu_gm20b_ops = { | |||
145 | .suspend_contexts = vgpu_gr_suspend_contexts, | 145 | .suspend_contexts = vgpu_gr_suspend_contexts, |
146 | .resume_contexts = vgpu_gr_resume_contexts, | 146 | .resume_contexts = vgpu_gr_resume_contexts, |
147 | .get_preemption_mode_flags = gr_gm20b_get_preemption_mode_flags, | 147 | .get_preemption_mode_flags = gr_gm20b_get_preemption_mode_flags, |
148 | .init_sm_id_table = gr_gk20a_init_sm_id_table, | 148 | .init_sm_id_table = vgpu_gr_init_sm_id_table, |
149 | .load_smid_config = gr_gm20b_load_smid_config, | 149 | .load_smid_config = gr_gm20b_load_smid_config, |
150 | .program_sm_id_numbering = gr_gm20b_program_sm_id_numbering, | 150 | .program_sm_id_numbering = gr_gm20b_program_sm_id_numbering, |
151 | .is_ltcs_ltss_addr = gr_gm20b_is_ltcs_ltss_addr, | 151 | .is_ltcs_ltss_addr = gr_gm20b_is_ltcs_ltss_addr, |
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c index 66ef6e00..aa520690 100644 --- a/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c +++ b/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2015-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -106,7 +106,7 @@ static const struct gpu_ops vgpu_gp10b_ops = { | |||
106 | .is_valid_compute_class = gr_gp10b_is_valid_compute_class, | 106 | .is_valid_compute_class = gr_gp10b_is_valid_compute_class, |
107 | .get_sm_dsm_perf_regs = gr_gm20b_get_sm_dsm_perf_regs, | 107 | .get_sm_dsm_perf_regs = gr_gm20b_get_sm_dsm_perf_regs, |
108 | .get_sm_dsm_perf_ctrl_regs = gr_gm20b_get_sm_dsm_perf_ctrl_regs, | 108 | .get_sm_dsm_perf_ctrl_regs = gr_gm20b_get_sm_dsm_perf_ctrl_regs, |
109 | .init_fs_state = vgpu_gm20b_init_fs_state, | 109 | .init_fs_state = vgpu_gr_init_fs_state, |
110 | .set_hww_esr_report_mask = gr_gm20b_set_hww_esr_report_mask, | 110 | .set_hww_esr_report_mask = gr_gm20b_set_hww_esr_report_mask, |
111 | .falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments, | 111 | .falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments, |
112 | .load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode, | 112 | .load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode, |
@@ -159,7 +159,7 @@ static const struct gpu_ops vgpu_gp10b_ops = { | |||
159 | .suspend_contexts = vgpu_gr_suspend_contexts, | 159 | .suspend_contexts = vgpu_gr_suspend_contexts, |
160 | .resume_contexts = vgpu_gr_resume_contexts, | 160 | .resume_contexts = vgpu_gr_resume_contexts, |
161 | .get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags, | 161 | .get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags, |
162 | .init_sm_id_table = gr_gk20a_init_sm_id_table, | 162 | .init_sm_id_table = vgpu_gr_init_sm_id_table, |
163 | .load_smid_config = gr_gp10b_load_smid_config, | 163 | .load_smid_config = gr_gp10b_load_smid_config, |
164 | .program_sm_id_numbering = gr_gm20b_program_sm_id_numbering, | 164 | .program_sm_id_numbering = gr_gm20b_program_sm_id_numbering, |
165 | .is_ltcs_ltss_addr = gr_gm20b_is_ltcs_ltss_addr, | 165 | .is_ltcs_ltss_addr = gr_gm20b_is_ltcs_ltss_addr, |
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gr_vgpu.c b/drivers/gpu/nvgpu/common/linux/vgpu/gr_vgpu.c index fa2010cd..a0662956 100644 --- a/drivers/gpu/nvgpu/common/linux/vgpu/gr_vgpu.c +++ b/drivers/gpu/nvgpu/common/linux/vgpu/gr_vgpu.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * Virtualized GPU Graphics | 2 | * Virtualized GPU Graphics |
3 | * | 3 | * |
4 | * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | 6 | * This program is free software; you can redistribute it and/or modify it |
7 | * under the terms and conditions of the GNU General Public License, | 7 | * under the terms and conditions of the GNU General Public License, |
@@ -610,6 +610,7 @@ static int vgpu_gr_init_gr_config(struct gk20a *g, struct gr_gk20a *gr) | |||
610 | { | 610 | { |
611 | struct vgpu_priv_data *priv = vgpu_get_priv_data(g); | 611 | struct vgpu_priv_data *priv = vgpu_get_priv_data(g); |
612 | u32 gpc_index; | 612 | u32 gpc_index; |
613 | u32 sm_per_tpc; | ||
613 | int err = -ENOMEM; | 614 | int err = -ENOMEM; |
614 | 615 | ||
615 | gk20a_dbg_fn(""); | 616 | gk20a_dbg_fn(""); |
@@ -628,8 +629,10 @@ static int vgpu_gr_init_gr_config(struct gk20a *g, struct gr_gk20a *gr) | |||
628 | if (!gr->gpc_tpc_mask) | 629 | if (!gr->gpc_tpc_mask) |
629 | goto cleanup; | 630 | goto cleanup; |
630 | 631 | ||
632 | sm_per_tpc = priv->constants.sm_per_tpc; | ||
631 | gr->sm_to_cluster = nvgpu_kzalloc(g, gr->gpc_count * | 633 | gr->sm_to_cluster = nvgpu_kzalloc(g, gr->gpc_count * |
632 | gr->max_tpc_per_gpc_count * | 634 | gr->max_tpc_per_gpc_count * |
635 | sm_per_tpc * | ||
633 | sizeof(struct sm_info)); | 636 | sizeof(struct sm_info)); |
634 | if (!gr->sm_to_cluster) | 637 | if (!gr->sm_to_cluster) |
635 | goto cleanup; | 638 | goto cleanup; |
@@ -1215,3 +1218,63 @@ void vgpu_gr_handle_sm_esr_event(struct gk20a *g, | |||
1215 | 1218 | ||
1216 | nvgpu_mutex_release(&g->dbg_sessions_lock); | 1219 | nvgpu_mutex_release(&g->dbg_sessions_lock); |
1217 | } | 1220 | } |
1221 | |||
1222 | int vgpu_gr_init_sm_id_table(struct gk20a *g) | ||
1223 | { | ||
1224 | struct tegra_vgpu_cmd_msg msg = {}; | ||
1225 | struct tegra_vgpu_vsms_mapping_params *p = &msg.params.vsms_mapping; | ||
1226 | struct tegra_vgpu_vsms_mapping_entry *entry; | ||
1227 | struct vgpu_priv_data *priv = vgpu_get_priv_data(g); | ||
1228 | struct sm_info *sm_info; | ||
1229 | int err; | ||
1230 | struct gr_gk20a *gr = &g->gr; | ||
1231 | size_t oob_size; | ||
1232 | void *handle = NULL; | ||
1233 | u32 sm_id; | ||
1234 | u32 max_sm; | ||
1235 | |||
1236 | msg.cmd = TEGRA_VGPU_CMD_GET_VSMS_MAPPING; | ||
1237 | msg.handle = vgpu_get_handle(g); | ||
1238 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
1239 | err = err ? err : msg.ret; | ||
1240 | if (err) { | ||
1241 | nvgpu_err(g, "get vsms mapping failed err %d", err); | ||
1242 | return err; | ||
1243 | } | ||
1244 | |||
1245 | handle = tegra_gr_comm_oob_get_ptr(TEGRA_GR_COMM_CTX_CLIENT, | ||
1246 | tegra_gr_comm_get_server_vmid(), | ||
1247 | TEGRA_VGPU_QUEUE_CMD, | ||
1248 | (void **)&entry, &oob_size); | ||
1249 | if (!handle) | ||
1250 | return -EINVAL; | ||
1251 | |||
1252 | max_sm = gr->gpc_count * | ||
1253 | gr->max_tpc_per_gpc_count * | ||
1254 | priv->constants.sm_per_tpc; | ||
1255 | if (p->num_sm > max_sm) | ||
1256 | return -EINVAL; | ||
1257 | |||
1258 | if ((p->num_sm * sizeof(*entry)) > oob_size) | ||
1259 | return -EINVAL; | ||
1260 | |||
1261 | gr->no_of_sm = p->num_sm; | ||
1262 | for (sm_id = 0; sm_id < p->num_sm; sm_id++, entry++) { | ||
1263 | sm_info = &gr->sm_to_cluster[sm_id]; | ||
1264 | sm_info->tpc_index = entry->tpc_index; | ||
1265 | sm_info->gpc_index = entry->gpc_index; | ||
1266 | sm_info->sm_index = entry->sm_index; | ||
1267 | sm_info->global_tpc_index = entry->global_tpc_index; | ||
1268 | } | ||
1269 | tegra_gr_comm_oob_put_ptr(handle); | ||
1270 | |||
1271 | return 0; | ||
1272 | } | ||
1273 | |||
1274 | int vgpu_gr_init_fs_state(struct gk20a *g) | ||
1275 | { | ||
1276 | if (!g->ops.gr.init_sm_id_table) | ||
1277 | return -EINVAL; | ||
1278 | |||
1279 | return g->ops.gr.init_sm_id_table(g); | ||
1280 | } | ||
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gr_vgpu.h b/drivers/gpu/nvgpu/common/linux/vgpu/gr_vgpu.h index 7815201e..16aa92a9 100644 --- a/drivers/gpu/nvgpu/common/linux/vgpu/gr_vgpu.h +++ b/drivers/gpu/nvgpu/common/linux/vgpu/gr_vgpu.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -60,5 +60,7 @@ int vgpu_gr_resume_contexts(struct gk20a *g, | |||
60 | struct dbg_session_gk20a *dbg_s, | 60 | struct dbg_session_gk20a *dbg_s, |
61 | int *ctx_resident_ch_fd); | 61 | int *ctx_resident_ch_fd); |
62 | int vgpu_gr_commit_inst(struct channel_gk20a *c, u64 gpu_va); | 62 | int vgpu_gr_commit_inst(struct channel_gk20a *c, u64 gpu_va); |
63 | int vgpu_gr_init_sm_id_table(struct gk20a *g); | ||
64 | int vgpu_gr_init_fs_state(struct gk20a *g); | ||
63 | 65 | ||
64 | #endif | 66 | #endif |
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_hal_gv11b.c index 1523c2de..6f85b4ee 100644 --- a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_hal_gv11b.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -126,7 +126,7 @@ static const struct gpu_ops vgpu_gv11b_ops = { | |||
126 | .is_valid_compute_class = gr_gv11b_is_valid_compute_class, | 126 | .is_valid_compute_class = gr_gv11b_is_valid_compute_class, |
127 | .get_sm_dsm_perf_regs = gv11b_gr_get_sm_dsm_perf_regs, | 127 | .get_sm_dsm_perf_regs = gv11b_gr_get_sm_dsm_perf_regs, |
128 | .get_sm_dsm_perf_ctrl_regs = gv11b_gr_get_sm_dsm_perf_ctrl_regs, | 128 | .get_sm_dsm_perf_ctrl_regs = gv11b_gr_get_sm_dsm_perf_ctrl_regs, |
129 | .init_fs_state = vgpu_gm20b_init_fs_state, | 129 | .init_fs_state = vgpu_gr_init_fs_state, |
130 | .set_hww_esr_report_mask = gv11b_gr_set_hww_esr_report_mask, | 130 | .set_hww_esr_report_mask = gv11b_gr_set_hww_esr_report_mask, |
131 | .falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments, | 131 | .falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments, |
132 | .load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode, | 132 | .load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode, |
@@ -179,7 +179,7 @@ static const struct gpu_ops vgpu_gv11b_ops = { | |||
179 | .suspend_contexts = vgpu_gr_suspend_contexts, | 179 | .suspend_contexts = vgpu_gr_suspend_contexts, |
180 | .resume_contexts = vgpu_gr_resume_contexts, | 180 | .resume_contexts = vgpu_gr_resume_contexts, |
181 | .get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags, | 181 | .get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags, |
182 | .init_sm_id_table = gr_gv100_init_sm_id_table, | 182 | .init_sm_id_table = vgpu_gr_init_sm_id_table, |
183 | .load_smid_config = gr_gv11b_load_smid_config, | 183 | .load_smid_config = gr_gv11b_load_smid_config, |
184 | .program_sm_id_numbering = gr_gv11b_program_sm_id_numbering, | 184 | .program_sm_id_numbering = gr_gv11b_program_sm_id_numbering, |
185 | .is_ltcs_ltss_addr = gr_gm20b_is_ltcs_ltss_addr, | 185 | .is_ltcs_ltss_addr = gr_gm20b_is_ltcs_ltss_addr, |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index a1c9c2bd..4f05ba8f 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -392,7 +392,7 @@ struct gpu_ops { | |||
392 | void (*update_boosted_ctx)(struct gk20a *g, | 392 | void (*update_boosted_ctx)(struct gk20a *g, |
393 | struct nvgpu_mem *mem, | 393 | struct nvgpu_mem *mem, |
394 | struct gr_ctx_desc *gr_ctx); | 394 | struct gr_ctx_desc *gr_ctx); |
395 | void (*init_sm_id_table)(struct gk20a *g); | 395 | int (*init_sm_id_table)(struct gk20a *g); |
396 | int (*load_smid_config)(struct gk20a *g); | 396 | int (*load_smid_config)(struct gk20a *g); |
397 | void (*program_sm_id_numbering)(struct gk20a *g, | 397 | void (*program_sm_id_numbering)(struct gk20a *g, |
398 | u32 gpc, u32 tpc, u32 smid); | 398 | u32 gpc, u32 tpc, u32 smid); |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 11054087..0f6bebe7 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GK20A Graphics | 2 | * GK20A Graphics |
3 | * | 3 | * |
4 | * Copyright (c) 2011-2017, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2011-2018, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -1137,7 +1137,7 @@ static inline u32 count_bits(u32 mask) | |||
1137 | return count; | 1137 | return count; |
1138 | } | 1138 | } |
1139 | 1139 | ||
1140 | void gr_gk20a_init_sm_id_table(struct gk20a *g) | 1140 | int gr_gk20a_init_sm_id_table(struct gk20a *g) |
1141 | { | 1141 | { |
1142 | u32 gpc, tpc; | 1142 | u32 gpc, tpc; |
1143 | u32 sm_id = 0; | 1143 | u32 sm_id = 0; |
@@ -1156,6 +1156,7 @@ void gr_gk20a_init_sm_id_table(struct gk20a *g) | |||
1156 | } | 1156 | } |
1157 | } | 1157 | } |
1158 | g->gr.no_of_sm = sm_id; | 1158 | g->gr.no_of_sm = sm_id; |
1159 | return 0; | ||
1159 | } | 1160 | } |
1160 | 1161 | ||
1161 | /* | 1162 | /* |
@@ -1178,11 +1179,15 @@ int gr_gk20a_init_fs_state(struct gk20a *g) | |||
1178 | u32 tpc_per_gpc; | 1179 | u32 tpc_per_gpc; |
1179 | u32 fuse_tpc_mask; | 1180 | u32 fuse_tpc_mask; |
1180 | u32 reg_index; | 1181 | u32 reg_index; |
1182 | int err; | ||
1181 | 1183 | ||
1182 | gk20a_dbg_fn(""); | 1184 | gk20a_dbg_fn(""); |
1183 | 1185 | ||
1184 | if (g->ops.gr.init_sm_id_table) { | 1186 | if (g->ops.gr.init_sm_id_table) { |
1185 | g->ops.gr.init_sm_id_table(g); | 1187 | err = g->ops.gr.init_sm_id_table(g); |
1188 | if (err) | ||
1189 | return err; | ||
1190 | |||
1186 | /* Is table empty ? */ | 1191 | /* Is table empty ? */ |
1187 | if (g->gr.no_of_sm == 0) | 1192 | if (g->gr.no_of_sm == 0) |
1188 | return -EINVAL; | 1193 | return -EINVAL; |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h index b6d5c14b..1c22923b 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h | |||
@@ -766,7 +766,7 @@ u32 gr_gk20a_tpc_enabled_exceptions(struct gk20a *g); | |||
766 | 766 | ||
767 | int gr_gk20a_commit_global_timeslice(struct gk20a *g, struct channel_gk20a *c); | 767 | int gr_gk20a_commit_global_timeslice(struct gk20a *g, struct channel_gk20a *c); |
768 | 768 | ||
769 | void gr_gk20a_init_sm_id_table(struct gk20a *g); | 769 | int gr_gk20a_init_sm_id_table(struct gk20a *g); |
770 | 770 | ||
771 | int gr_gk20a_commit_inst(struct channel_gk20a *c, u64 gpu_va); | 771 | int gr_gk20a_commit_inst(struct channel_gk20a *c, u64 gpu_va); |
772 | 772 | ||
diff --git a/drivers/gpu/nvgpu/gv100/gr_gv100.c b/drivers/gpu/nvgpu/gv100/gr_gv100.c index 430c7cd0..f90fd075 100644 --- a/drivers/gpu/nvgpu/gv100/gr_gv100.c +++ b/drivers/gpu/nvgpu/gv100/gr_gv100.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GV100 GPU GR | 2 | * GV100 GPU GR |
3 | * | 3 | * |
4 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -199,14 +199,14 @@ void gr_gv100_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) | |||
199 | { | 199 | { |
200 | } | 200 | } |
201 | 201 | ||
202 | void gr_gv100_init_sm_id_table(struct gk20a *g) | 202 | int gr_gv100_init_sm_id_table(struct gk20a *g) |
203 | { | 203 | { |
204 | u32 gpc, tpc, sm, pes, gtpc; | 204 | u32 gpc, tpc, sm, pes, gtpc; |
205 | u32 sm_id = 0; | 205 | u32 sm_id = 0; |
206 | u32 sm_per_tpc = nvgpu_get_litter_value(g, GPU_LIT_NUM_SM_PER_TPC); | 206 | u32 sm_per_tpc = nvgpu_get_litter_value(g, GPU_LIT_NUM_SM_PER_TPC); |
207 | u32 num_sm = sm_per_tpc * g->gr.tpc_count; | 207 | u32 num_sm = sm_per_tpc * g->gr.tpc_count; |
208 | int perf, maxperf; | 208 | int perf, maxperf; |
209 | int err; | 209 | int err = 0; |
210 | unsigned long *gpc_tpc_mask; | 210 | unsigned long *gpc_tpc_mask; |
211 | u32 *tpc_table, *gpc_table; | 211 | u32 *tpc_table, *gpc_table; |
212 | 212 | ||
@@ -217,6 +217,7 @@ void gr_gv100_init_sm_id_table(struct gk20a *g) | |||
217 | 217 | ||
218 | if (!gpc_table || !tpc_table || !gpc_tpc_mask) { | 218 | if (!gpc_table || !tpc_table || !gpc_tpc_mask) { |
219 | nvgpu_err(g, "Error allocating memory for sm tables"); | 219 | nvgpu_err(g, "Error allocating memory for sm tables"); |
220 | err = -ENOMEM; | ||
220 | goto exit_build_table; | 221 | goto exit_build_table; |
221 | } | 222 | } |
222 | 223 | ||
@@ -273,6 +274,7 @@ exit_build_table: | |||
273 | nvgpu_kfree(g, gpc_table); | 274 | nvgpu_kfree(g, gpc_table); |
274 | nvgpu_kfree(g, tpc_table); | 275 | nvgpu_kfree(g, tpc_table); |
275 | nvgpu_kfree(g, gpc_tpc_mask); | 276 | nvgpu_kfree(g, gpc_tpc_mask); |
277 | return err; | ||
276 | } | 278 | } |
277 | 279 | ||
278 | void gr_gv100_load_tpc_mask(struct gk20a *g) | 280 | void gr_gv100_load_tpc_mask(struct gk20a *g) |
diff --git a/drivers/gpu/nvgpu/gv100/gr_gv100.h b/drivers/gpu/nvgpu/gv100/gr_gv100.h index 612f76f9..690bba57 100644 --- a/drivers/gpu/nvgpu/gv100/gr_gv100.h +++ b/drivers/gpu/nvgpu/gv100/gr_gv100.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GV100 GPU GR | 2 | * GV100 GPU GR |
3 | * | 3 | * |
4 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -28,7 +28,7 @@ | |||
28 | void gr_gv100_bundle_cb_defaults(struct gk20a *g); | 28 | void gr_gv100_bundle_cb_defaults(struct gk20a *g); |
29 | void gr_gv100_cb_size_default(struct gk20a *g); | 29 | void gr_gv100_cb_size_default(struct gk20a *g); |
30 | void gr_gv100_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index); | 30 | void gr_gv100_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index); |
31 | void gr_gv100_init_sm_id_table(struct gk20a *g); | 31 | int gr_gv100_init_sm_id_table(struct gk20a *g); |
32 | void gr_gv100_program_sm_id_numbering(struct gk20a *g, | 32 | void gr_gv100_program_sm_id_numbering(struct gk20a *g, |
33 | u32 gpc, u32 tpc, u32 smid); | 33 | u32 gpc, u32 tpc, u32 smid); |
34 | int gr_gv100_load_smid_config(struct gk20a *g); | 34 | int gr_gv100_load_smid_config(struct gk20a *g); |