diff options
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/common/mm/pd_cache.c | 15 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/gmmu.h | 19 |
2 files changed, 30 insertions, 4 deletions
diff --git a/drivers/gpu/nvgpu/common/mm/pd_cache.c b/drivers/gpu/nvgpu/common/mm/pd_cache.c index a5b3d134..8f7003e5 100644 --- a/drivers/gpu/nvgpu/common/mm/pd_cache.c +++ b/drivers/gpu/nvgpu/common/mm/pd_cache.c | |||
@@ -423,12 +423,19 @@ static void nvgpu_pd_cache_do_free(struct gk20a *g, | |||
423 | * this just re-adds it. | 423 | * this just re-adds it. |
424 | * | 424 | * |
425 | * Since the memory used for the entries is still mapped, if | 425 | * Since the memory used for the entries is still mapped, if |
426 | * igpu make sure the entries are invalidated so that the hw | 426 | * iommu is being used, make sure PTE entries in particular |
427 | * doesn't accidentally try to prefetch non-existent fb memory. | 427 | * are invalidated so that the hw doesn't accidentally try to |
428 | * prefetch non-existent fb memory. | ||
428 | * | 429 | * |
429 | * TBD: what about dgpu? (Not supported in Drive 5.0) | 430 | * Notes: |
431 | * - The check for NVGPU_PD_CACHE_SIZE > PAGE_SIZE effectively | ||
432 | * determines whether PTE entries use the cache. | ||
433 | * - In the case where PTE entries ues the cache, we also | ||
434 | * end up invalidating the PDE entries, but that's a minor | ||
435 | * performance hit, as there are far fewer of those | ||
436 | * typically than there are PTE entries. | ||
430 | */ | 437 | */ |
431 | if (pd->mem->cpu_va != NULL) { | 438 | if (nvgpu_iommuable(g) && (NVGPU_PD_CACHE_SIZE > PAGE_SIZE)) { |
432 | memset((void *)((u64)pd->mem->cpu_va + pd->mem_offs), 0, | 439 | memset((void *)((u64)pd->mem->cpu_va + pd->mem_offs), 0, |
433 | pentry->pd_size); | 440 | pentry->pd_size); |
434 | } | 441 | } |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gmmu.h b/drivers/gpu/nvgpu/include/nvgpu/gmmu.h index ee2207b8..2fc0d44e 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gmmu.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gmmu.h | |||
@@ -29,6 +29,7 @@ | |||
29 | #include <nvgpu/rbtree.h> | 29 | #include <nvgpu/rbtree.h> |
30 | #include <nvgpu/lock.h> | 30 | #include <nvgpu/lock.h> |
31 | #include <nvgpu/bitops.h> | 31 | #include <nvgpu/bitops.h> |
32 | #include <nvgpu/mm.h> | ||
32 | 33 | ||
33 | /* | 34 | /* |
34 | * This is the GMMU API visible to blocks outside of the GMMU. Basically this | 35 | * This is the GMMU API visible to blocks outside of the GMMU. Basically this |
@@ -54,10 +55,28 @@ enum gk20a_mem_rw_flag { | |||
54 | * Minimum size of a cache. The number of different caches in the nvgpu_pd_cache | 55 | * Minimum size of a cache. The number of different caches in the nvgpu_pd_cache |
55 | * structure is of course depending on this. The MIN_SHIFT define is the right | 56 | * structure is of course depending on this. The MIN_SHIFT define is the right |
56 | * number of bits to shift to determine which list to use in the array of lists. | 57 | * number of bits to shift to determine which list to use in the array of lists. |
58 | * | ||
59 | * For Linux, limit the use of the cache to entries less than the page size, to | ||
60 | * avoid potential problems with running out of CMA memory when allocating large, | ||
61 | * contiguous slabs, as would be required for non-iommmuable chips. | ||
57 | */ | 62 | */ |
58 | #define NVGPU_PD_CACHE_MIN 256U | 63 | #define NVGPU_PD_CACHE_MIN 256U |
59 | #define NVGPU_PD_CACHE_MIN_SHIFT 9U | 64 | #define NVGPU_PD_CACHE_MIN_SHIFT 9U |
65 | |||
66 | #ifdef __KERNEL__ | ||
67 | |||
68 | #if PAGE_SIZE == 4096 | ||
69 | #define NVGPU_PD_CACHE_COUNT 4U | ||
70 | #elif PAGE_SIZE == 65536 | ||
60 | #define NVGPU_PD_CACHE_COUNT 8U | 71 | #define NVGPU_PD_CACHE_COUNT 8U |
72 | #else | ||
73 | #error "Unsupported page size." | ||
74 | #endif | ||
75 | |||
76 | #else | ||
77 | #define NVGPU_PD_CACHE_COUNT 8U | ||
78 | #endif | ||
79 | |||
61 | #define NVGPU_PD_CACHE_SIZE (NVGPU_PD_CACHE_MIN * (1U << NVGPU_PD_CACHE_COUNT)) | 80 | #define NVGPU_PD_CACHE_SIZE (NVGPU_PD_CACHE_MIN * (1U << NVGPU_PD_CACHE_COUNT)) |
62 | 81 | ||
63 | struct nvgpu_pd_mem_entry { | 82 | struct nvgpu_pd_mem_entry { |