diff options
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 19 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/gr_gm20b.c | 19 |
2 files changed, 24 insertions, 14 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 3354c05e..2c7423c0 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -58,7 +58,6 @@ | |||
58 | #include "semaphore_gk20a.h" | 58 | #include "semaphore_gk20a.h" |
59 | #include "platform_gk20a.h" | 59 | #include "platform_gk20a.h" |
60 | #include "ctxsw_trace_gk20a.h" | 60 | #include "ctxsw_trace_gk20a.h" |
61 | #include "hw_proj_gk20a.h" | ||
62 | 61 | ||
63 | #define BLK_SIZE (256) | 62 | #define BLK_SIZE (256) |
64 | #define NV_PMM_FBP_STRIDE 0x1000 | 63 | #define NV_PMM_FBP_STRIDE 0x1000 |
@@ -5513,8 +5512,10 @@ static int gk20a_gr_record_sm_error_state(struct gk20a *g, u32 gpc, u32 tpc) | |||
5513 | { | 5512 | { |
5514 | int sm_id; | 5513 | int sm_id; |
5515 | struct gr_gk20a *gr = &g->gr; | 5514 | struct gr_gk20a *gr = &g->gr; |
5516 | u32 offset = proj_gpc_stride_v() * gpc + | 5515 | u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE); |
5517 | proj_tpc_in_gpc_stride_v() * tpc; | 5516 | u32 tpc_in_gpc_stride = nvgpu_get_litter_value(g, |
5517 | GPU_LIT_TPC_IN_GPC_STRIDE); | ||
5518 | u32 offset = gpc_stride * gpc + tpc_in_gpc_stride * tpc; | ||
5518 | 5519 | ||
5519 | mutex_lock(&g->dbg_sessions_lock); | 5520 | mutex_lock(&g->dbg_sessions_lock); |
5520 | 5521 | ||
@@ -5542,6 +5543,9 @@ static int gk20a_gr_update_sm_error_state(struct gk20a *g, | |||
5542 | u32 gpc, tpc, offset; | 5543 | u32 gpc, tpc, offset; |
5543 | struct gr_gk20a *gr = &g->gr; | 5544 | struct gr_gk20a *gr = &g->gr; |
5544 | struct channel_ctx_gk20a *ch_ctx = &ch->ch_ctx; | 5545 | struct channel_ctx_gk20a *ch_ctx = &ch->ch_ctx; |
5546 | u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE); | ||
5547 | u32 tpc_in_gpc_stride = nvgpu_get_litter_value(g, | ||
5548 | GPU_LIT_TPC_IN_GPC_STRIDE); | ||
5545 | int err = 0; | 5549 | int err = 0; |
5546 | 5550 | ||
5547 | mutex_lock(&g->dbg_sessions_lock); | 5551 | mutex_lock(&g->dbg_sessions_lock); |
@@ -5564,8 +5568,7 @@ static int gk20a_gr_update_sm_error_state(struct gk20a *g, | |||
5564 | gpc = g->gr.sm_to_cluster[sm_id].gpc_index; | 5568 | gpc = g->gr.sm_to_cluster[sm_id].gpc_index; |
5565 | tpc = g->gr.sm_to_cluster[sm_id].tpc_index; | 5569 | tpc = g->gr.sm_to_cluster[sm_id].tpc_index; |
5566 | 5570 | ||
5567 | offset = proj_gpc_stride_v() * gpc + | 5571 | offset = gpc_stride * gpc + tpc_in_gpc_stride * tpc; |
5568 | proj_tpc_in_gpc_stride_v() * tpc; | ||
5569 | 5572 | ||
5570 | if (gk20a_is_channel_ctx_resident(ch)) { | 5573 | if (gk20a_is_channel_ctx_resident(ch)) { |
5571 | gk20a_writel(g, gr_gpc0_tpc0_sm_hww_global_esr_r() + offset, | 5574 | gk20a_writel(g, gr_gpc0_tpc0_sm_hww_global_esr_r() + offset, |
@@ -5607,6 +5610,9 @@ static int gk20a_gr_clear_sm_error_state(struct gk20a *g, | |||
5607 | u32 gpc, tpc, offset; | 5610 | u32 gpc, tpc, offset; |
5608 | u32 val; | 5611 | u32 val; |
5609 | struct gr_gk20a *gr = &g->gr; | 5612 | struct gr_gk20a *gr = &g->gr; |
5613 | u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE); | ||
5614 | u32 tpc_in_gpc_stride = nvgpu_get_litter_value(g, | ||
5615 | GPU_LIT_TPC_IN_GPC_STRIDE); | ||
5610 | int err = 0; | 5616 | int err = 0; |
5611 | 5617 | ||
5612 | mutex_lock(&g->dbg_sessions_lock); | 5618 | mutex_lock(&g->dbg_sessions_lock); |
@@ -5623,8 +5629,7 @@ static int gk20a_gr_clear_sm_error_state(struct gk20a *g, | |||
5623 | gpc = g->gr.sm_to_cluster[sm_id].gpc_index; | 5629 | gpc = g->gr.sm_to_cluster[sm_id].gpc_index; |
5624 | tpc = g->gr.sm_to_cluster[sm_id].tpc_index; | 5630 | tpc = g->gr.sm_to_cluster[sm_id].tpc_index; |
5625 | 5631 | ||
5626 | offset = proj_gpc_stride_v() * gpc + | 5632 | offset = gpc_stride * gpc + tpc_in_gpc_stride * tpc; |
5627 | proj_tpc_in_gpc_stride_v() * tpc; | ||
5628 | 5633 | ||
5629 | val = gk20a_readl(g, gr_gpc0_tpc0_sm_hww_global_esr_r() + offset); | 5634 | val = gk20a_readl(g, gr_gpc0_tpc0_sm_hww_global_esr_r() + offset); |
5630 | gk20a_writel(g, gr_gpc0_tpc0_sm_hww_global_esr_r() + offset, | 5635 | gk20a_writel(g, gr_gpc0_tpc0_sm_hww_global_esr_r() + offset, |
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index 9d269365..40925f48 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c | |||
@@ -31,7 +31,6 @@ | |||
31 | #include "hw_fuse_gm20b.h" | 31 | #include "hw_fuse_gm20b.h" |
32 | #include "pmu_gm20b.h" | 32 | #include "pmu_gm20b.h" |
33 | #include "acr_gm20b.h" | 33 | #include "acr_gm20b.h" |
34 | #include "hw_proj_gm20b.h" | ||
35 | 34 | ||
36 | static void gr_gm20b_init_gpc_mmu(struct gk20a *g) | 35 | static void gr_gm20b_init_gpc_mmu(struct gk20a *g) |
37 | { | 36 | { |
@@ -1195,8 +1194,10 @@ static int gm20b_gr_record_sm_error_state(struct gk20a *g, u32 gpc, u32 tpc) | |||
1195 | { | 1194 | { |
1196 | int sm_id; | 1195 | int sm_id; |
1197 | struct gr_gk20a *gr = &g->gr; | 1196 | struct gr_gk20a *gr = &g->gr; |
1198 | u32 offset = proj_gpc_stride_v() * gpc + | 1197 | u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE); |
1199 | proj_tpc_in_gpc_stride_v() * tpc; | 1198 | u32 tpc_in_gpc_stride = nvgpu_get_litter_value(g, |
1199 | GPU_LIT_TPC_IN_GPC_STRIDE); | ||
1200 | u32 offset = gpc_stride * gpc + tpc_in_gpc_stride * tpc; | ||
1200 | 1201 | ||
1201 | mutex_lock(&g->dbg_sessions_lock); | 1202 | mutex_lock(&g->dbg_sessions_lock); |
1202 | 1203 | ||
@@ -1226,6 +1227,9 @@ static int gm20b_gr_update_sm_error_state(struct gk20a *g, | |||
1226 | u32 gpc, tpc, offset; | 1227 | u32 gpc, tpc, offset; |
1227 | struct gr_gk20a *gr = &g->gr; | 1228 | struct gr_gk20a *gr = &g->gr; |
1228 | struct channel_ctx_gk20a *ch_ctx = &ch->ch_ctx; | 1229 | struct channel_ctx_gk20a *ch_ctx = &ch->ch_ctx; |
1230 | u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE); | ||
1231 | u32 tpc_in_gpc_stride = nvgpu_get_litter_value(g, | ||
1232 | GPU_LIT_TPC_IN_GPC_STRIDE); | ||
1229 | int err = 0; | 1233 | int err = 0; |
1230 | 1234 | ||
1231 | mutex_lock(&g->dbg_sessions_lock); | 1235 | mutex_lock(&g->dbg_sessions_lock); |
@@ -1250,8 +1254,7 @@ static int gm20b_gr_update_sm_error_state(struct gk20a *g, | |||
1250 | gpc = g->gr.sm_to_cluster[sm_id].gpc_index; | 1254 | gpc = g->gr.sm_to_cluster[sm_id].gpc_index; |
1251 | tpc = g->gr.sm_to_cluster[sm_id].tpc_index; | 1255 | tpc = g->gr.sm_to_cluster[sm_id].tpc_index; |
1252 | 1256 | ||
1253 | offset = proj_gpc_stride_v() * gpc + | 1257 | offset = gpc_stride * gpc + tpc_in_gpc_stride * tpc; |
1254 | proj_tpc_in_gpc_stride_v() * tpc; | ||
1255 | 1258 | ||
1256 | if (gk20a_is_channel_ctx_resident(ch)) { | 1259 | if (gk20a_is_channel_ctx_resident(ch)) { |
1257 | gk20a_writel(g, gr_gpc0_tpc0_sm_hww_global_esr_r() + offset, | 1260 | gk20a_writel(g, gr_gpc0_tpc0_sm_hww_global_esr_r() + offset, |
@@ -1295,6 +1298,9 @@ static int gm20b_gr_clear_sm_error_state(struct gk20a *g, | |||
1295 | u32 gpc, tpc, offset; | 1298 | u32 gpc, tpc, offset; |
1296 | u32 val; | 1299 | u32 val; |
1297 | struct gr_gk20a *gr = &g->gr; | 1300 | struct gr_gk20a *gr = &g->gr; |
1301 | u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE); | ||
1302 | u32 tpc_in_gpc_stride = nvgpu_get_litter_value(g, | ||
1303 | GPU_LIT_TPC_IN_GPC_STRIDE); | ||
1298 | int err = 0; | 1304 | int err = 0; |
1299 | 1305 | ||
1300 | mutex_lock(&g->dbg_sessions_lock); | 1306 | mutex_lock(&g->dbg_sessions_lock); |
@@ -1311,8 +1317,7 @@ static int gm20b_gr_clear_sm_error_state(struct gk20a *g, | |||
1311 | gpc = g->gr.sm_to_cluster[sm_id].gpc_index; | 1317 | gpc = g->gr.sm_to_cluster[sm_id].gpc_index; |
1312 | tpc = g->gr.sm_to_cluster[sm_id].tpc_index; | 1318 | tpc = g->gr.sm_to_cluster[sm_id].tpc_index; |
1313 | 1319 | ||
1314 | offset = proj_gpc_stride_v() * gpc + | 1320 | offset = gpc_stride * gpc + tpc_in_gpc_stride * tpc; |
1315 | proj_tpc_in_gpc_stride_v() * tpc; | ||
1316 | 1321 | ||
1317 | val = gk20a_readl(g, gr_gpc0_tpc0_sm_hww_global_esr_r() + offset); | 1322 | val = gk20a_readl(g, gr_gpc0_tpc0_sm_hww_global_esr_r() + offset); |
1318 | gk20a_writel(g, gr_gpc0_tpc0_sm_hww_global_esr_r() + offset, | 1323 | gk20a_writel(g, gr_gpc0_tpc0_sm_hww_global_esr_r() + offset, |