diff options
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 93 |
1 files changed, 37 insertions, 56 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 293ccd97..4a98514b 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -3390,26 +3390,7 @@ static void gr_gk20a_detect_sm_arch(struct gk20a *g) | |||
3390 | int gr_gk20a_add_zbc_color(struct gk20a *g, struct gr_gk20a *gr, | 3390 | int gr_gk20a_add_zbc_color(struct gk20a *g, struct gr_gk20a *gr, |
3391 | struct zbc_entry *color_val, u32 index) | 3391 | struct zbc_entry *color_val, u32 index) |
3392 | { | 3392 | { |
3393 | struct fifo_gk20a *f = &g->fifo; | ||
3394 | struct fifo_engine_info_gk20a *gr_info = f->engine_info + ENGINE_GR_GK20A; | ||
3395 | u32 i; | 3393 | u32 i; |
3396 | unsigned long end_jiffies = jiffies + | ||
3397 | msecs_to_jiffies(gk20a_get_gr_idle_timeout(g)); | ||
3398 | u32 ret; | ||
3399 | |||
3400 | ret = gk20a_fifo_disable_engine_activity(g, gr_info, true); | ||
3401 | if (ret) { | ||
3402 | gk20a_err(dev_from_gk20a(g), | ||
3403 | "failed to disable gr engine activity\n"); | ||
3404 | return ret; | ||
3405 | } | ||
3406 | |||
3407 | ret = gr_gk20a_wait_idle(g, end_jiffies, GR_IDLE_CHECK_DEFAULT); | ||
3408 | if (ret) { | ||
3409 | gk20a_err(dev_from_gk20a(g), | ||
3410 | "failed to idle graphics\n"); | ||
3411 | goto clean_up; | ||
3412 | } | ||
3413 | 3394 | ||
3414 | /* update l2 table */ | 3395 | /* update l2 table */ |
3415 | g->ops.ltc.set_zbc_color_entry(g, color_val, index); | 3396 | g->ops.ltc.set_zbc_color_entry(g, color_val, index); |
@@ -3444,39 +3425,12 @@ int gr_gk20a_add_zbc_color(struct gk20a *g, struct gr_gk20a *gr, | |||
3444 | gr->zbc_col_tbl[index].format = color_val->format; | 3425 | gr->zbc_col_tbl[index].format = color_val->format; |
3445 | gr->zbc_col_tbl[index].ref_cnt++; | 3426 | gr->zbc_col_tbl[index].ref_cnt++; |
3446 | 3427 | ||
3447 | clean_up: | 3428 | return 0; |
3448 | ret = gk20a_fifo_enable_engine_activity(g, gr_info); | ||
3449 | if (ret) { | ||
3450 | gk20a_err(dev_from_gk20a(g), | ||
3451 | "failed to enable gr engine activity\n"); | ||
3452 | } | ||
3453 | |||
3454 | return ret; | ||
3455 | } | 3429 | } |
3456 | 3430 | ||
3457 | int gr_gk20a_add_zbc_depth(struct gk20a *g, struct gr_gk20a *gr, | 3431 | int gr_gk20a_add_zbc_depth(struct gk20a *g, struct gr_gk20a *gr, |
3458 | struct zbc_entry *depth_val, u32 index) | 3432 | struct zbc_entry *depth_val, u32 index) |
3459 | { | 3433 | { |
3460 | struct fifo_gk20a *f = &g->fifo; | ||
3461 | struct fifo_engine_info_gk20a *gr_info = f->engine_info + ENGINE_GR_GK20A; | ||
3462 | unsigned long end_jiffies = jiffies + | ||
3463 | msecs_to_jiffies(gk20a_get_gr_idle_timeout(g)); | ||
3464 | u32 ret; | ||
3465 | |||
3466 | ret = gk20a_fifo_disable_engine_activity(g, gr_info, true); | ||
3467 | if (ret) { | ||
3468 | gk20a_err(dev_from_gk20a(g), | ||
3469 | "failed to disable gr engine activity\n"); | ||
3470 | return ret; | ||
3471 | } | ||
3472 | |||
3473 | ret = gr_gk20a_wait_idle(g, end_jiffies, GR_IDLE_CHECK_DEFAULT); | ||
3474 | if (ret) { | ||
3475 | gk20a_err(dev_from_gk20a(g), | ||
3476 | "failed to idle graphics\n"); | ||
3477 | goto clean_up; | ||
3478 | } | ||
3479 | |||
3480 | /* update l2 table */ | 3434 | /* update l2 table */ |
3481 | g->ops.ltc.set_zbc_depth_entry(g, depth_val, index); | 3435 | g->ops.ltc.set_zbc_depth_entry(g, depth_val, index); |
3482 | 3436 | ||
@@ -3501,14 +3455,7 @@ int gr_gk20a_add_zbc_depth(struct gk20a *g, struct gr_gk20a *gr, | |||
3501 | gr->zbc_dep_tbl[index].format = depth_val->format; | 3455 | gr->zbc_dep_tbl[index].format = depth_val->format; |
3502 | gr->zbc_dep_tbl[index].ref_cnt++; | 3456 | gr->zbc_dep_tbl[index].ref_cnt++; |
3503 | 3457 | ||
3504 | clean_up: | 3458 | return 0; |
3505 | ret = gk20a_fifo_enable_engine_activity(g, gr_info); | ||
3506 | if (ret) { | ||
3507 | gk20a_err(dev_from_gk20a(g), | ||
3508 | "failed to enable gr engine activity\n"); | ||
3509 | } | ||
3510 | |||
3511 | return ret; | ||
3512 | } | 3459 | } |
3513 | 3460 | ||
3514 | void gr_gk20a_pmu_save_zbc(struct gk20a *g, u32 entries) | 3461 | void gr_gk20a_pmu_save_zbc(struct gk20a *g, u32 entries) |
@@ -3794,13 +3741,47 @@ int gr_gk20a_load_zbc_default_table(struct gk20a *g, struct gr_gk20a *gr) | |||
3794 | return 0; | 3741 | return 0; |
3795 | } | 3742 | } |
3796 | 3743 | ||
3744 | static int _gk20a_gr_zbc_set_table(struct gk20a *g, struct gr_gk20a *gr, | ||
3745 | struct zbc_entry *zbc_val) | ||
3746 | { | ||
3747 | struct fifo_gk20a *f = &g->fifo; | ||
3748 | struct fifo_engine_info_gk20a *gr_info = f->engine_info + ENGINE_GR_GK20A; | ||
3749 | unsigned long end_jiffies; | ||
3750 | int ret; | ||
3751 | |||
3752 | ret = gk20a_fifo_disable_engine_activity(g, gr_info, true); | ||
3753 | if (ret) { | ||
3754 | gk20a_err(dev_from_gk20a(g), | ||
3755 | "failed to disable gr engine activity\n"); | ||
3756 | return ret; | ||
3757 | } | ||
3758 | |||
3759 | end_jiffies = jiffies + msecs_to_jiffies(gk20a_get_gr_idle_timeout(g)); | ||
3760 | ret = gr_gk20a_wait_idle(g, end_jiffies, GR_IDLE_CHECK_DEFAULT); | ||
3761 | if (ret) { | ||
3762 | gk20a_err(dev_from_gk20a(g), | ||
3763 | "failed to idle graphics\n"); | ||
3764 | goto clean_up; | ||
3765 | } | ||
3766 | |||
3767 | ret = gr_gk20a_add_zbc(g, gr, zbc_val); | ||
3768 | |||
3769 | clean_up: | ||
3770 | if (gk20a_fifo_enable_engine_activity(g, gr_info)) { | ||
3771 | gk20a_err(dev_from_gk20a(g), | ||
3772 | "failed to enable gr engine activity\n"); | ||
3773 | } | ||
3774 | |||
3775 | return ret; | ||
3776 | } | ||
3777 | |||
3797 | int gk20a_gr_zbc_set_table(struct gk20a *g, struct gr_gk20a *gr, | 3778 | int gk20a_gr_zbc_set_table(struct gk20a *g, struct gr_gk20a *gr, |
3798 | struct zbc_entry *zbc_val) | 3779 | struct zbc_entry *zbc_val) |
3799 | { | 3780 | { |
3800 | gk20a_dbg_fn(""); | 3781 | gk20a_dbg_fn(""); |
3801 | 3782 | ||
3802 | return gr_gk20a_elpg_protected_call(g, | 3783 | return gr_gk20a_elpg_protected_call(g, |
3803 | gr_gk20a_add_zbc(g, gr, zbc_val)); | 3784 | _gk20a_gr_zbc_set_table(g, gr, zbc_val)); |
3804 | } | 3785 | } |
3805 | 3786 | ||
3806 | void gr_gk20a_init_blcg_mode(struct gk20a *g, u32 mode, u32 engine) | 3787 | void gr_gk20a_init_blcg_mode(struct gk20a *g, u32 mode, u32 engine) |