diff options
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/common/as.c | 5 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/fb/fb_gv11b.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/pmu/pmu.c | 5 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/channel_gk20a.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 64 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 10 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/fifo_gv100.c | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/ptimer.h | 18 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/utils.h | 52 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/os/linux/sysfs.c | 1 |
13 files changed, 100 insertions, 63 deletions
diff --git a/drivers/gpu/nvgpu/common/as.c b/drivers/gpu/nvgpu/common/as.c index 5458614e..75537ecc 100644 --- a/drivers/gpu/nvgpu/common/as.c +++ b/drivers/gpu/nvgpu/common/as.c | |||
@@ -168,3 +168,8 @@ release_fail: | |||
168 | 168 | ||
169 | return err; | 169 | return err; |
170 | } | 170 | } |
171 | |||
172 | struct gk20a *gk20a_from_as(struct gk20a_as *as) | ||
173 | { | ||
174 | return container_of(as, struct gk20a, as); | ||
175 | } | ||
diff --git a/drivers/gpu/nvgpu/common/fb/fb_gv11b.c b/drivers/gpu/nvgpu/common/fb/fb_gv11b.c index 53f04188..a7e5de68 100644 --- a/drivers/gpu/nvgpu/common/fb/fb_gv11b.c +++ b/drivers/gpu/nvgpu/common/fb/fb_gv11b.c | |||
@@ -29,6 +29,7 @@ | |||
29 | #include <nvgpu/barrier.h> | 29 | #include <nvgpu/barrier.h> |
30 | #include <nvgpu/bug.h> | 30 | #include <nvgpu/bug.h> |
31 | #include <nvgpu/soc.h> | 31 | #include <nvgpu/soc.h> |
32 | #include <nvgpu/ptimer.h> | ||
32 | 33 | ||
33 | #include "gk20a/gk20a.h" | 34 | #include "gk20a/gk20a.h" |
34 | #include "gk20a/mm_gk20a.h" | 35 | #include "gk20a/mm_gk20a.h" |
diff --git a/drivers/gpu/nvgpu/common/pmu/pmu.c b/drivers/gpu/nvgpu/common/pmu/pmu.c index c642a7bc..b9ac50be 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu.c | |||
@@ -594,3 +594,8 @@ void nvgpu_pmu_surface_free(struct gk20a *g, struct nvgpu_mem *mem) | |||
594 | nvgpu_dma_free(g, mem); | 594 | nvgpu_dma_free(g, mem); |
595 | memset(mem, 0, sizeof(struct nvgpu_mem)); | 595 | memset(mem, 0, sizeof(struct nvgpu_mem)); |
596 | } | 596 | } |
597 | |||
598 | struct gk20a *gk20a_from_pmu(struct nvgpu_pmu *pmu) | ||
599 | { | ||
600 | return container_of(pmu, struct gk20a, pmu); | ||
601 | } | ||
diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c index 53134f71..8d6c3b70 100644 --- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c | |||
@@ -42,6 +42,7 @@ | |||
42 | #include <nvgpu/error_notifier.h> | 42 | #include <nvgpu/error_notifier.h> |
43 | #include <nvgpu/os_sched.h> | 43 | #include <nvgpu/os_sched.h> |
44 | #include <nvgpu/log2.h> | 44 | #include <nvgpu/log2.h> |
45 | #include <nvgpu/ptimer.h> | ||
45 | 46 | ||
46 | #include "gk20a.h" | 47 | #include "gk20a.h" |
47 | #include "dbg_gpu_gk20a.h" | 48 | #include "dbg_gpu_gk20a.h" |
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index 57cb0019..9086e468 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | |||
@@ -40,6 +40,7 @@ | |||
40 | #include <nvgpu/barrier.h> | 40 | #include <nvgpu/barrier.h> |
41 | #include <nvgpu/ctxsw_trace.h> | 41 | #include <nvgpu/ctxsw_trace.h> |
42 | #include <nvgpu/error_notifier.h> | 42 | #include <nvgpu/error_notifier.h> |
43 | #include <nvgpu/ptimer.h> | ||
43 | 44 | ||
44 | #include "gk20a.h" | 45 | #include "gk20a.h" |
45 | #include "mm_gk20a.h" | 46 | #include "mm_gk20a.h" |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index afd18658..4fe93e3b 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -64,12 +64,12 @@ struct nvgpu_ctxsw_trace_filter; | |||
64 | #include <nvgpu/nvlink.h> | 64 | #include <nvgpu/nvlink.h> |
65 | #include <nvgpu/sim.h> | 65 | #include <nvgpu/sim.h> |
66 | #include <nvgpu/ecc.h> | 66 | #include <nvgpu/ecc.h> |
67 | #include <nvgpu/utils.h> | ||
67 | 68 | ||
68 | #include "clk_gk20a.h" | 69 | #include "clk_gk20a.h" |
69 | #include "ce2_gk20a.h" | 70 | #include "ce2_gk20a.h" |
70 | #include "fifo_gk20a.h" | 71 | #include "fifo_gk20a.h" |
71 | #include "tsg_gk20a.h" | 72 | #include "tsg_gk20a.h" |
72 | #include "gr_gk20a.h" | ||
73 | #include "pmu_gk20a.h" | 73 | #include "pmu_gk20a.h" |
74 | #include "priv_ring_gk20a.h" | 74 | #include "priv_ring_gk20a.h" |
75 | #include "therm_gk20a.h" | 75 | #include "therm_gk20a.h" |
@@ -78,10 +78,6 @@ struct nvgpu_ctxsw_trace_filter; | |||
78 | #include "pmgr/pmgr.h" | 78 | #include "pmgr/pmgr.h" |
79 | #include "therm/thrm.h" | 79 | #include "therm/thrm.h" |
80 | 80 | ||
81 | /* PTIMER_REF_FREQ_HZ corresponds to a period of 32 nanoseconds. | ||
82 | 32 ns is the resolution of ptimer. */ | ||
83 | #define PTIMER_REF_FREQ_HZ 31250000 | ||
84 | |||
85 | #ifdef CONFIG_DEBUG_FS | 81 | #ifdef CONFIG_DEBUG_FS |
86 | struct railgate_stats { | 82 | struct railgate_stats { |
87 | unsigned long last_rail_gate_start; | 83 | unsigned long last_rail_gate_start; |
@@ -1652,50 +1648,8 @@ enum gk20a_nonstall_ops { | |||
1652 | void __nvgpu_check_gpu_state(struct gk20a *g); | 1648 | void __nvgpu_check_gpu_state(struct gk20a *g); |
1653 | void __gk20a_warn_on_no_regs(void); | 1649 | void __gk20a_warn_on_no_regs(void); |
1654 | 1650 | ||
1655 | /* convenience */ | 1651 | struct gk20a *gk20a_from_as(struct gk20a_as *as); |
1656 | static inline struct gk20a *gk20a_from_as(struct gk20a_as *as) | 1652 | struct gk20a *gk20a_from_pmu(struct nvgpu_pmu *pmu); |
1657 | { | ||
1658 | return container_of(as, struct gk20a, as); | ||
1659 | } | ||
1660 | static inline struct gk20a *gk20a_from_pmu(struct nvgpu_pmu *pmu) | ||
1661 | { | ||
1662 | return container_of(pmu, struct gk20a, pmu); | ||
1663 | } | ||
1664 | |||
1665 | static inline u32 u64_hi32(u64 n) | ||
1666 | { | ||
1667 | return (u32)((n >> 32) & ~(u32)0); | ||
1668 | } | ||
1669 | |||
1670 | static inline u32 u64_lo32(u64 n) | ||
1671 | { | ||
1672 | return (u32)(n & ~(u32)0); | ||
1673 | } | ||
1674 | |||
1675 | static inline u64 hi32_lo32_to_u64(u32 hi, u32 lo) | ||
1676 | { | ||
1677 | return (((u64)hi) << 32) | (u64)lo; | ||
1678 | } | ||
1679 | |||
1680 | static inline u32 set_field(u32 val, u32 mask, u32 field) | ||
1681 | { | ||
1682 | return ((val & ~mask) | field); | ||
1683 | } | ||
1684 | |||
1685 | static inline u32 get_field(u32 reg, u32 mask) | ||
1686 | { | ||
1687 | return (reg & mask); | ||
1688 | } | ||
1689 | |||
1690 | /* invalidate channel lookup tlb */ | ||
1691 | static inline void gk20a_gr_flush_channel_tlb(struct gr_gk20a *gr) | ||
1692 | { | ||
1693 | nvgpu_spinlock_acquire(&gr->ch_tlb_lock); | ||
1694 | memset(gr->chid_tlb, 0, | ||
1695 | sizeof(struct gr_channel_map_tlb_entry) * | ||
1696 | GR_CHANNEL_MAP_TLB_SIZE); | ||
1697 | nvgpu_spinlock_release(&gr->ch_tlb_lock); | ||
1698 | } | ||
1699 | 1653 | ||
1700 | /* classes that the device supports */ | 1654 | /* classes that the device supports */ |
1701 | /* TBD: get these from an open-sourced SDK? */ | 1655 | /* TBD: get these from an open-sourced SDK? */ |
@@ -1736,18 +1690,6 @@ int gk20a_wait_for_idle(struct gk20a *g); | |||
1736 | 1690 | ||
1737 | int gk20a_init_gpu_characteristics(struct gk20a *g); | 1691 | int gk20a_init_gpu_characteristics(struct gk20a *g); |
1738 | 1692 | ||
1739 | static inline u32 ptimer_scalingfactor10x(u32 ptimer_src_freq) | ||
1740 | { | ||
1741 | return (u32)(((u64)(PTIMER_REF_FREQ_HZ * 10)) / ptimer_src_freq); | ||
1742 | } | ||
1743 | static inline u32 scale_ptimer(u32 timeout , u32 scale10x) | ||
1744 | { | ||
1745 | if (((timeout*10) % scale10x) >= (scale10x/2)) | ||
1746 | return ((timeout * 10) / scale10x) + 1; | ||
1747 | else | ||
1748 | return (timeout * 10) / scale10x; | ||
1749 | } | ||
1750 | |||
1751 | int gk20a_prepare_poweroff(struct gk20a *g); | 1693 | int gk20a_prepare_poweroff(struct gk20a *g); |
1752 | int gk20a_finalize_poweron(struct gk20a *g); | 1694 | int gk20a_finalize_poweron(struct gk20a *g); |
1753 | 1695 | ||
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 38570041..40bd5413 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -8777,3 +8777,13 @@ u32 gk20a_gr_get_sm_no_lock_down_hww_global_esr_mask(struct gk20a *g) | |||
8777 | 8777 | ||
8778 | return global_esr_mask; | 8778 | return global_esr_mask; |
8779 | } | 8779 | } |
8780 | |||
8781 | /* invalidate channel lookup tlb */ | ||
8782 | void gk20a_gr_flush_channel_tlb(struct gr_gk20a *gr) | ||
8783 | { | ||
8784 | nvgpu_spinlock_acquire(&gr->ch_tlb_lock); | ||
8785 | memset(gr->chid_tlb, 0, | ||
8786 | sizeof(struct gr_channel_map_tlb_entry) * | ||
8787 | GR_CHANNEL_MAP_TLB_SIZE); | ||
8788 | nvgpu_spinlock_release(&gr->ch_tlb_lock); | ||
8789 | } | ||
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h index 92e1dff5..0c6be57b 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h | |||
@@ -857,4 +857,5 @@ void gk20a_gr_destroy_ctx_buffer(struct gk20a *g, | |||
857 | struct gr_ctx_buffer_desc *desc); | 857 | struct gr_ctx_buffer_desc *desc); |
858 | int gk20a_gr_alloc_ctx_buffer(struct gk20a *g, | 858 | int gk20a_gr_alloc_ctx_buffer(struct gk20a *g, |
859 | struct gr_ctx_buffer_desc *desc, size_t size); | 859 | struct gr_ctx_buffer_desc *desc, size_t size); |
860 | void gk20a_gr_flush_channel_tlb(struct gr_gk20a *gr); | ||
860 | #endif /*__GR_GK20A_H__*/ | 861 | #endif /*__GR_GK20A_H__*/ |
diff --git a/drivers/gpu/nvgpu/gv100/fifo_gv100.c b/drivers/gpu/nvgpu/gv100/fifo_gv100.c index f5e43ea7..242e48f9 100644 --- a/drivers/gpu/nvgpu/gv100/fifo_gv100.c +++ b/drivers/gpu/nvgpu/gv100/fifo_gv100.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GV100 fifo | 2 | * GV100 fifo |
3 | * | 3 | * |
4 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -25,6 +25,7 @@ | |||
25 | #include "gk20a/gk20a.h" | 25 | #include "gk20a/gk20a.h" |
26 | #include "fifo_gv100.h" | 26 | #include "fifo_gv100.h" |
27 | #include <nvgpu/timers.h> | 27 | #include <nvgpu/timers.h> |
28 | #include <nvgpu/ptimer.h> | ||
28 | 29 | ||
29 | #include <nvgpu/hw/gv100/hw_ccsr_gv100.h> | 30 | #include <nvgpu/hw/gv100/hw_ccsr_gv100.h> |
30 | #include <nvgpu/hw/gk20a/hw_fifo_gk20a.h> | 31 | #include <nvgpu/hw/gk20a/hw_fifo_gk20a.h> |
diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 210a863b..548371d6 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | |||
@@ -36,6 +36,7 @@ | |||
36 | #include <nvgpu/log2.h> | 36 | #include <nvgpu/log2.h> |
37 | #include <nvgpu/ctxsw_trace.h> | 37 | #include <nvgpu/ctxsw_trace.h> |
38 | #include <nvgpu/io_usermode.h> | 38 | #include <nvgpu/io_usermode.h> |
39 | #include <nvgpu/ptimer.h> | ||
39 | 40 | ||
40 | #include "gk20a/gk20a.h" | 41 | #include "gk20a/gk20a.h" |
41 | #include "gk20a/fifo_gk20a.h" | 42 | #include "gk20a/fifo_gk20a.h" |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/ptimer.h b/drivers/gpu/nvgpu/include/nvgpu/ptimer.h index 54c6b20c..598e064f 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/ptimer.h +++ b/drivers/gpu/nvgpu/include/nvgpu/ptimer.h | |||
@@ -31,8 +31,24 @@ struct nvgpu_cpu_time_correlation_sample { | |||
31 | u64 gpu_timestamp; | 31 | u64 gpu_timestamp; |
32 | }; | 32 | }; |
33 | 33 | ||
34 | /* PTIMER_REF_FREQ_HZ corresponds to a period of 32 nanoseconds. | ||
35 | 32 ns is the resolution of ptimer. */ | ||
36 | #define PTIMER_REF_FREQ_HZ 31250000 | ||
37 | |||
38 | static inline u32 ptimer_scalingfactor10x(u32 ptimer_src_freq) | ||
39 | { | ||
40 | return (u32)(((u64)(PTIMER_REF_FREQ_HZ * 10)) / ptimer_src_freq); | ||
41 | } | ||
42 | |||
43 | static inline u32 scale_ptimer(u32 timeout , u32 scale10x) | ||
44 | { | ||
45 | if (((timeout*10) % scale10x) >= (scale10x/2)) | ||
46 | return ((timeout * 10) / scale10x) + 1; | ||
47 | else | ||
48 | return (timeout * 10) / scale10x; | ||
49 | } | ||
50 | |||
34 | int nvgpu_get_timestamps_zipper(struct gk20a *g, | 51 | int nvgpu_get_timestamps_zipper(struct gk20a *g, |
35 | u32 source_id, u32 count, | 52 | u32 source_id, u32 count, |
36 | struct nvgpu_cpu_time_correlation_sample *samples); | 53 | struct nvgpu_cpu_time_correlation_sample *samples); |
37 | |||
38 | #endif | 54 | #endif |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/utils.h b/drivers/gpu/nvgpu/include/nvgpu/utils.h new file mode 100644 index 00000000..22102fa3 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/utils.h | |||
@@ -0,0 +1,52 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | |||
23 | #ifndef NVGPU_UTILS_H | ||
24 | #define NVGPU_UTILS_H | ||
25 | |||
26 | #include <nvgpu/types.h> | ||
27 | |||
28 | static inline u32 u64_hi32(u64 n) | ||
29 | { | ||
30 | return (u32)((n >> 32) & ~(u32)0); | ||
31 | } | ||
32 | |||
33 | static inline u32 u64_lo32(u64 n) | ||
34 | { | ||
35 | return (u32)(n & ~(u32)0); | ||
36 | } | ||
37 | |||
38 | static inline u64 hi32_lo32_to_u64(u32 hi, u32 lo) | ||
39 | { | ||
40 | return (((u64)hi) << 32) | (u64)lo; | ||
41 | } | ||
42 | |||
43 | static inline u32 set_field(u32 val, u32 mask, u32 field) | ||
44 | { | ||
45 | return ((val & ~mask) | field); | ||
46 | } | ||
47 | |||
48 | static inline u32 get_field(u32 reg, u32 mask) | ||
49 | { | ||
50 | return (reg & mask); | ||
51 | } | ||
52 | #endif /* NVGPU_UTILS_H */ | ||
diff --git a/drivers/gpu/nvgpu/os/linux/sysfs.c b/drivers/gpu/nvgpu/os/linux/sysfs.c index b607768a..d0a29300 100644 --- a/drivers/gpu/nvgpu/os/linux/sysfs.c +++ b/drivers/gpu/nvgpu/os/linux/sysfs.c | |||
@@ -20,6 +20,7 @@ | |||
20 | 20 | ||
21 | #include <nvgpu/kmem.h> | 21 | #include <nvgpu/kmem.h> |
22 | #include <nvgpu/nvhost.h> | 22 | #include <nvgpu/nvhost.h> |
23 | #include <nvgpu/ptimer.h> | ||
23 | 24 | ||
24 | #include "sysfs.h" | 25 | #include "sysfs.h" |
25 | #include "platform_gk20a.h" | 26 | #include "platform_gk20a.h" |