diff options
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fb_gk20a.c | 8 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.c | 53 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 7 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 8 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/mc_gk20a.c | 62 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/mc_gk20a.h | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/mc_gm20b.c | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/mc_gp10b.c | 5 |
11 files changed, 96 insertions, 67 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/fb_gk20a.c b/drivers/gpu/nvgpu/gk20a/fb_gk20a.c index 4b8baad5..a1d348a4 100644 --- a/drivers/gpu/nvgpu/gk20a/fb_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fb_gk20a.c | |||
@@ -30,10 +30,10 @@ void fb_gk20a_reset(struct gk20a *g) | |||
30 | 30 | ||
31 | gk20a_dbg_info("reset gk20a fb"); | 31 | gk20a_dbg_info("reset gk20a fb"); |
32 | 32 | ||
33 | gk20a_reset(g, mc_enable_pfb_enabled_f() | 33 | g->ops.mc.reset(g, mc_enable_pfb_enabled_f() | |
34 | | mc_enable_l2_enabled_f() | 34 | mc_enable_l2_enabled_f() | |
35 | | mc_enable_xbar_enabled_f() | 35 | mc_enable_xbar_enabled_f() | |
36 | | mc_enable_hub_enabled_f()); | 36 | mc_enable_hub_enabled_f()); |
37 | 37 | ||
38 | val = gk20a_readl(g, mc_elpg_enable_r()); | 38 | val = gk20a_readl(g, mc_elpg_enable_r()); |
39 | val |= mc_elpg_enable_xbar_enabled_f() | 39 | val |= mc_elpg_enable_xbar_enabled_f() |
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index 8f7a2e22..6c4f12df 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | |||
@@ -766,7 +766,7 @@ int gk20a_init_fifo_reset_enable_hw(struct gk20a *g) | |||
766 | 766 | ||
767 | gk20a_dbg_fn(""); | 767 | gk20a_dbg_fn(""); |
768 | /* enable pmc pfifo */ | 768 | /* enable pmc pfifo */ |
769 | gk20a_reset(g, mc_enable_pfifo_enabled_f()); | 769 | g->ops.mc.reset(g, mc_enable_pfifo_enabled_f()); |
770 | 770 | ||
771 | if (g->ops.clock_gating.slcg_ce2_load_gating_prod) | 771 | if (g->ops.clock_gating.slcg_ce2_load_gating_prod) |
772 | g->ops.clock_gating.slcg_ce2_load_gating_prod(g, | 772 | g->ops.clock_gating.slcg_ce2_load_gating_prod(g, |
@@ -1249,7 +1249,7 @@ void gk20a_fifo_reset_engine(struct gk20a *g, u32 engine_id) | |||
1249 | } | 1249 | } |
1250 | if ((engine_enum == ENGINE_GRCE_GK20A) || | 1250 | if ((engine_enum == ENGINE_GRCE_GK20A) || |
1251 | (engine_enum == ENGINE_ASYNC_CE_GK20A)) { | 1251 | (engine_enum == ENGINE_ASYNC_CE_GK20A)) { |
1252 | gk20a_reset(g, engine_info->reset_mask); | 1252 | g->ops.mc.reset(g, engine_info->reset_mask); |
1253 | } | 1253 | } |
1254 | } | 1254 | } |
1255 | 1255 | ||
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.c b/drivers/gpu/nvgpu/gk20a/gk20a.c index 694f0e93..e77986be 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gk20a.c | |||
@@ -54,6 +54,7 @@ | |||
54 | #include "gk20a_scale.h" | 54 | #include "gk20a_scale.h" |
55 | #include "ctxsw_trace_gk20a.h" | 55 | #include "ctxsw_trace_gk20a.h" |
56 | #include "dbg_gpu_gk20a.h" | 56 | #include "dbg_gpu_gk20a.h" |
57 | #include "mc_gk20a.h" | ||
57 | #include "hal.h" | 58 | #include "hal.h" |
58 | #include "vgpu/vgpu.h" | 59 | #include "vgpu/vgpu.h" |
59 | #include "pci.h" | 60 | #include "pci.h" |
@@ -70,7 +71,6 @@ | |||
70 | #include "nvgpu_gpuid_t19x.h" | 71 | #include "nvgpu_gpuid_t19x.h" |
71 | #endif | 72 | #endif |
72 | 73 | ||
73 | #include <nvgpu/hw/gk20a/hw_mc_gk20a.h> | ||
74 | #include <nvgpu/hw/gk20a/hw_top_gk20a.h> | 74 | #include <nvgpu/hw/gk20a/hw_top_gk20a.h> |
75 | #include <nvgpu/hw/gk20a/hw_ltc_gk20a.h> | 75 | #include <nvgpu/hw/gk20a/hw_ltc_gk20a.h> |
76 | #include <nvgpu/hw/gk20a/hw_fb_gk20a.h> | 76 | #include <nvgpu/hw/gk20a/hw_fb_gk20a.h> |
@@ -263,7 +263,7 @@ static const struct file_operations gk20a_sched_ops = { | |||
263 | 263 | ||
264 | void __nvgpu_check_gpu_state(struct gk20a *g) | 264 | void __nvgpu_check_gpu_state(struct gk20a *g) |
265 | { | 265 | { |
266 | u32 boot_0 = readl(g->regs + mc_boot_0_r()); | 266 | u32 boot_0 = g->ops.mc.boot_0(g, NULL, NULL, NULL); |
267 | 267 | ||
268 | if (boot_0 == 0xffffffff) { | 268 | if (boot_0 == 0xffffffff) { |
269 | pr_err("nvgpu: GPU has disappeared from bus!!\n"); | 269 | pr_err("nvgpu: GPU has disappeared from bus!!\n"); |
@@ -474,18 +474,12 @@ done: | |||
474 | static int gk20a_detect_chip(struct gk20a *g) | 474 | static int gk20a_detect_chip(struct gk20a *g) |
475 | { | 475 | { |
476 | struct nvgpu_gpu_characteristics *gpu = &g->gpu_characteristics; | 476 | struct nvgpu_gpu_characteristics *gpu = &g->gpu_characteristics; |
477 | u32 mc_boot_0_value; | 477 | u32 val; |
478 | 478 | ||
479 | if (gpu->arch) | 479 | if (gpu->arch) |
480 | return 0; | 480 | return 0; |
481 | 481 | ||
482 | mc_boot_0_value = gk20a_readl(g, mc_boot_0_r()); | 482 | val = gk20a_mc_boot_0(g, &gpu->arch, &gpu->impl, &gpu->rev); |
483 | gpu->arch = mc_boot_0_architecture_v(mc_boot_0_value) << | ||
484 | NVGPU_GPU_ARCHITECTURE_SHIFT; | ||
485 | gpu->impl = mc_boot_0_implementation_v(mc_boot_0_value); | ||
486 | gpu->rev = | ||
487 | (mc_boot_0_major_revision_v(mc_boot_0_value) << 4) | | ||
488 | mc_boot_0_minor_revision_v(mc_boot_0_value); | ||
489 | 483 | ||
490 | gk20a_dbg_info("arch: %x, impl: %x, rev: %x\n", | 484 | gk20a_dbg_info("arch: %x, impl: %x, rev: %x\n", |
491 | g->gpu_characteristics.arch, | 485 | g->gpu_characteristics.arch, |
@@ -1513,45 +1507,6 @@ fail: | |||
1513 | up_read(&g->busy_lock); | 1507 | up_read(&g->busy_lock); |
1514 | } | 1508 | } |
1515 | 1509 | ||
1516 | void gk20a_disable(struct gk20a *g, u32 units) | ||
1517 | { | ||
1518 | u32 pmc; | ||
1519 | |||
1520 | gk20a_dbg(gpu_dbg_info, "pmc disable: %08x\n", units); | ||
1521 | |||
1522 | nvgpu_spinlock_acquire(&g->mc_enable_lock); | ||
1523 | pmc = gk20a_readl(g, mc_enable_r()); | ||
1524 | pmc &= ~units; | ||
1525 | gk20a_writel(g, mc_enable_r(), pmc); | ||
1526 | nvgpu_spinlock_release(&g->mc_enable_lock); | ||
1527 | } | ||
1528 | |||
1529 | void gk20a_enable(struct gk20a *g, u32 units) | ||
1530 | { | ||
1531 | u32 pmc; | ||
1532 | |||
1533 | gk20a_dbg(gpu_dbg_info, "pmc enable: %08x\n", units); | ||
1534 | |||
1535 | nvgpu_spinlock_acquire(&g->mc_enable_lock); | ||
1536 | pmc = gk20a_readl(g, mc_enable_r()); | ||
1537 | pmc |= units; | ||
1538 | gk20a_writel(g, mc_enable_r(), pmc); | ||
1539 | gk20a_readl(g, mc_enable_r()); | ||
1540 | nvgpu_spinlock_release(&g->mc_enable_lock); | ||
1541 | |||
1542 | udelay(20); | ||
1543 | } | ||
1544 | |||
1545 | void gk20a_reset(struct gk20a *g, u32 units) | ||
1546 | { | ||
1547 | gk20a_disable(g, units); | ||
1548 | if (units & gk20a_fifo_get_all_ce_engine_reset_mask(g)) | ||
1549 | udelay(500); | ||
1550 | else | ||
1551 | udelay(20); | ||
1552 | gk20a_enable(g, units); | ||
1553 | } | ||
1554 | |||
1555 | #ifdef CONFIG_PM | 1510 | #ifdef CONFIG_PM |
1556 | /** | 1511 | /** |
1557 | * __gk20a_do_idle() - force the GPU to idle and railgate | 1512 | * __gk20a_do_idle() - force the GPU to idle and railgate |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index f4ca5649..4e1c4ff4 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -748,6 +748,10 @@ struct gpu_ops { | |||
748 | void (*isr_thread_nonstall)(struct gk20a *g, u32 intr); | 748 | void (*isr_thread_nonstall)(struct gk20a *g, u32 intr); |
749 | void (*isr_nonstall_cb)(struct work_struct *work); | 749 | void (*isr_nonstall_cb)(struct work_struct *work); |
750 | u32 intr_mask_restore[4]; | 750 | u32 intr_mask_restore[4]; |
751 | void (*enable)(struct gk20a *g, u32 units); | ||
752 | void (*disable)(struct gk20a *g, u32 units); | ||
753 | void (*reset)(struct gk20a *g, u32 units); | ||
754 | u32 (*boot_0)(struct gk20a *g, u32 *arch, u32 *impl, u32 *rev); | ||
751 | } mc; | 755 | } mc; |
752 | struct { | 756 | struct { |
753 | void (*show_dump)(struct gk20a *g, | 757 | void (*show_dump)(struct gk20a *g, |
@@ -1406,9 +1410,6 @@ void gk20a_busy_noresume(struct device *dev); | |||
1406 | void gk20a_idle_nosuspend(struct device *dev); | 1410 | void gk20a_idle_nosuspend(struct device *dev); |
1407 | int __must_check gk20a_busy(struct gk20a *g); | 1411 | int __must_check gk20a_busy(struct gk20a *g); |
1408 | void gk20a_idle(struct gk20a *g); | 1412 | void gk20a_idle(struct gk20a *g); |
1409 | void gk20a_disable(struct gk20a *g, u32 units); | ||
1410 | void gk20a_enable(struct gk20a *g, u32 units); | ||
1411 | void gk20a_reset(struct gk20a *g, u32 units); | ||
1412 | int gk20a_do_idle(void); | 1413 | int gk20a_do_idle(void); |
1413 | int gk20a_do_unidle(void); | 1414 | int gk20a_do_unidle(void); |
1414 | int __gk20a_do_idle(struct device *dev, bool force_reset); | 1415 | int __gk20a_do_idle(struct device *dev, bool force_reset); |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 5121d6e9..63ae1da1 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -4970,10 +4970,10 @@ static int gk20a_init_gr_prepare(struct gk20a *g) | |||
4970 | } | 4970 | } |
4971 | 4971 | ||
4972 | /* reset gr engine */ | 4972 | /* reset gr engine */ |
4973 | gk20a_reset(g, mc_enable_pgraph_enabled_f() | 4973 | g->ops.mc.reset(g, mc_enable_pgraph_enabled_f() | |
4974 | | mc_enable_blg_enabled_f() | 4974 | mc_enable_blg_enabled_f() | |
4975 | | mc_enable_perfmon_enabled_f() | 4975 | mc_enable_perfmon_enabled_f() | |
4976 | | ce_reset_mask); | 4976 | ce_reset_mask); |
4977 | 4977 | ||
4978 | gr_gk20a_load_gating_prod(g); | 4978 | gr_gk20a_load_gating_prod(g); |
4979 | 4979 | ||
diff --git a/drivers/gpu/nvgpu/gk20a/mc_gk20a.c b/drivers/gpu/nvgpu/gk20a/mc_gk20a.c index e51c4a29..3d6919c5 100644 --- a/drivers/gpu/nvgpu/gk20a/mc_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/mc_gk20a.c | |||
@@ -14,6 +14,7 @@ | |||
14 | */ | 14 | */ |
15 | 15 | ||
16 | #include <linux/types.h> | 16 | #include <linux/types.h> |
17 | #include <linux/delay.h> | ||
17 | #include <trace/events/gk20a.h> | 18 | #include <trace/events/gk20a.h> |
18 | 19 | ||
19 | #include "gk20a.h" | 20 | #include "gk20a.h" |
@@ -248,6 +249,63 @@ void mc_gk20a_intr_unit_config(struct gk20a *g, bool enable, | |||
248 | } | 249 | } |
249 | } | 250 | } |
250 | 251 | ||
252 | void gk20a_mc_disable(struct gk20a *g, u32 units) | ||
253 | { | ||
254 | u32 pmc; | ||
255 | |||
256 | gk20a_dbg(gpu_dbg_info, "pmc disable: %08x\n", units); | ||
257 | |||
258 | nvgpu_spinlock_acquire(&g->mc_enable_lock); | ||
259 | pmc = gk20a_readl(g, mc_enable_r()); | ||
260 | pmc &= ~units; | ||
261 | gk20a_writel(g, mc_enable_r(), pmc); | ||
262 | nvgpu_spinlock_release(&g->mc_enable_lock); | ||
263 | } | ||
264 | |||
265 | void gk20a_mc_enable(struct gk20a *g, u32 units) | ||
266 | { | ||
267 | u32 pmc; | ||
268 | |||
269 | gk20a_dbg(gpu_dbg_info, "pmc enable: %08x\n", units); | ||
270 | |||
271 | nvgpu_spinlock_acquire(&g->mc_enable_lock); | ||
272 | pmc = gk20a_readl(g, mc_enable_r()); | ||
273 | pmc |= units; | ||
274 | gk20a_writel(g, mc_enable_r(), pmc); | ||
275 | gk20a_readl(g, mc_enable_r()); | ||
276 | nvgpu_spinlock_release(&g->mc_enable_lock); | ||
277 | |||
278 | udelay(20); | ||
279 | } | ||
280 | |||
281 | void gk20a_mc_reset(struct gk20a *g, u32 units) | ||
282 | { | ||
283 | g->ops.mc.disable(g, units); | ||
284 | if (units & gk20a_fifo_get_all_ce_engine_reset_mask(g)) | ||
285 | udelay(500); | ||
286 | else | ||
287 | udelay(20); | ||
288 | g->ops.mc.enable(g, units); | ||
289 | } | ||
290 | |||
291 | u32 gk20a_mc_boot_0(struct gk20a *g, u32 *arch, u32 *impl, u32 *rev) | ||
292 | { | ||
293 | u32 val = gk20a_readl(g, mc_boot_0_r()); | ||
294 | |||
295 | if (arch) | ||
296 | *arch = mc_boot_0_architecture_v(val) << | ||
297 | NVGPU_GPU_ARCHITECTURE_SHIFT; | ||
298 | |||
299 | if (impl) | ||
300 | *impl = mc_boot_0_implementation_v(val); | ||
301 | |||
302 | if (rev) | ||
303 | *rev = (mc_boot_0_major_revision_v(val) << 4) | | ||
304 | mc_boot_0_minor_revision_v(val); | ||
305 | |||
306 | return val; | ||
307 | } | ||
308 | |||
251 | void gk20a_init_mc(struct gpu_ops *gops) | 309 | void gk20a_init_mc(struct gpu_ops *gops) |
252 | { | 310 | { |
253 | gops->mc.intr_enable = mc_gk20a_intr_enable; | 311 | gops->mc.intr_enable = mc_gk20a_intr_enable; |
@@ -257,4 +315,8 @@ void gk20a_init_mc(struct gpu_ops *gops) | |||
257 | gops->mc.isr_thread_stall = mc_gk20a_intr_thread_stall; | 315 | gops->mc.isr_thread_stall = mc_gk20a_intr_thread_stall; |
258 | gops->mc.isr_thread_nonstall = mc_gk20a_intr_thread_nonstall; | 316 | gops->mc.isr_thread_nonstall = mc_gk20a_intr_thread_nonstall; |
259 | gops->mc.isr_nonstall_cb = mc_gk20a_nonstall_cb; | 317 | gops->mc.isr_nonstall_cb = mc_gk20a_nonstall_cb; |
318 | gops->mc.enable = gk20a_mc_enable; | ||
319 | gops->mc.disable = gk20a_mc_disable; | ||
320 | gops->mc.reset = gk20a_mc_reset; | ||
321 | gops->mc.boot_0 = gk20a_mc_boot_0; | ||
260 | } | 322 | } |
diff --git a/drivers/gpu/nvgpu/gk20a/mc_gk20a.h b/drivers/gpu/nvgpu/gk20a/mc_gk20a.h index 1aad1a0b..9c70eba1 100644 --- a/drivers/gpu/nvgpu/gk20a/mc_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/mc_gk20a.h | |||
@@ -24,4 +24,8 @@ irqreturn_t mc_gk20a_isr_nonstall(struct gk20a *g); | |||
24 | irqreturn_t mc_gk20a_intr_thread_stall(struct gk20a *g); | 24 | irqreturn_t mc_gk20a_intr_thread_stall(struct gk20a *g); |
25 | void mc_gk20a_intr_thread_nonstall(struct gk20a *g, u32 intr); | 25 | void mc_gk20a_intr_thread_nonstall(struct gk20a *g, u32 intr); |
26 | void mc_gk20a_nonstall_cb(struct work_struct *work); | 26 | void mc_gk20a_nonstall_cb(struct work_struct *work); |
27 | void gk20a_mc_enable(struct gk20a *g, u32 units); | ||
28 | void gk20a_mc_disable(struct gk20a *g, u32 units); | ||
29 | void gk20a_mc_reset(struct gk20a *g, u32 units); | ||
30 | u32 gk20a_mc_boot_0(struct gk20a *g, u32 *arch, u32 *impl, u32 *rev); | ||
27 | #endif | 31 | #endif |
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c index a240ccf1..993cef7b 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | |||
@@ -2380,7 +2380,7 @@ int pmu_enable_hw(struct pmu_gk20a *pmu, bool enable) | |||
2380 | if (enable) { | 2380 | if (enable) { |
2381 | int retries = PMU_MEM_SCRUBBING_TIMEOUT_MAX / | 2381 | int retries = PMU_MEM_SCRUBBING_TIMEOUT_MAX / |
2382 | PMU_MEM_SCRUBBING_TIMEOUT_DEFAULT; | 2382 | PMU_MEM_SCRUBBING_TIMEOUT_DEFAULT; |
2383 | gk20a_enable(g, mc_enable_pwr_enabled_f()); | 2383 | g->ops.mc.enable(g, mc_enable_pwr_enabled_f()); |
2384 | 2384 | ||
2385 | if (g->ops.clock_gating.slcg_pmu_load_gating_prod) | 2385 | if (g->ops.clock_gating.slcg_pmu_load_gating_prod) |
2386 | g->ops.clock_gating.slcg_pmu_load_gating_prod(g, | 2386 | g->ops.clock_gating.slcg_pmu_load_gating_prod(g, |
@@ -2401,12 +2401,12 @@ int pmu_enable_hw(struct pmu_gk20a *pmu, bool enable) | |||
2401 | udelay(PMU_MEM_SCRUBBING_TIMEOUT_DEFAULT); | 2401 | udelay(PMU_MEM_SCRUBBING_TIMEOUT_DEFAULT); |
2402 | } while (--retries || !tegra_platform_is_silicon()); | 2402 | } while (--retries || !tegra_platform_is_silicon()); |
2403 | 2403 | ||
2404 | gk20a_disable(g, mc_enable_pwr_enabled_f()); | 2404 | g->ops.mc.disable(g, mc_enable_pwr_enabled_f()); |
2405 | gk20a_err(dev_from_gk20a(g), "Falcon mem scrubbing timeout"); | 2405 | gk20a_err(dev_from_gk20a(g), "Falcon mem scrubbing timeout"); |
2406 | 2406 | ||
2407 | return -ETIMEDOUT; | 2407 | return -ETIMEDOUT; |
2408 | } else { | 2408 | } else { |
2409 | gk20a_disable(g, mc_enable_pwr_enabled_f()); | 2409 | g->ops.mc.disable(g, mc_enable_pwr_enabled_f()); |
2410 | return 0; | 2410 | return 0; |
2411 | } | 2411 | } |
2412 | } | 2412 | } |
diff --git a/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c b/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c index a44df1e8..752ee121 100644 --- a/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c | |||
@@ -50,7 +50,7 @@ static void gk20a_reset_priv_ring(struct gk20a *g) | |||
50 | { | 50 | { |
51 | u32 val; | 51 | u32 val; |
52 | 52 | ||
53 | gk20a_reset(g, mc_enable_priv_ring_enabled_f()); | 53 | g->ops.mc.reset(g, mc_enable_priv_ring_enabled_f()); |
54 | 54 | ||
55 | val = gk20a_readl(g, pri_ringstation_sys_decode_config_r()); | 55 | val = gk20a_readl(g, pri_ringstation_sys_decode_config_r()); |
56 | val = set_field(val, | 56 | val = set_field(val, |
diff --git a/drivers/gpu/nvgpu/gm20b/mc_gm20b.c b/drivers/gpu/nvgpu/gm20b/mc_gm20b.c index c8a42cd7..7d0d052d 100644 --- a/drivers/gpu/nvgpu/gm20b/mc_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/mc_gm20b.c | |||
@@ -28,4 +28,8 @@ void gm20b_init_mc(struct gpu_ops *gops) | |||
28 | gops->mc.isr_thread_stall = mc_gk20a_intr_thread_stall; | 28 | gops->mc.isr_thread_stall = mc_gk20a_intr_thread_stall; |
29 | gops->mc.isr_thread_nonstall = mc_gk20a_intr_thread_nonstall; | 29 | gops->mc.isr_thread_nonstall = mc_gk20a_intr_thread_nonstall; |
30 | gops->mc.isr_nonstall_cb = mc_gk20a_nonstall_cb; | 30 | gops->mc.isr_nonstall_cb = mc_gk20a_nonstall_cb; |
31 | gops->mc.enable = gk20a_mc_enable; | ||
32 | gops->mc.disable = gk20a_mc_disable; | ||
33 | gops->mc.reset = gk20a_mc_reset; | ||
34 | gops->mc.boot_0 = gk20a_mc_boot_0; | ||
31 | } | 35 | } |
diff --git a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c index 547169ed..4b0cbc1c 100644 --- a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c | |||
@@ -184,5 +184,8 @@ void gp10b_init_mc(struct gpu_ops *gops) | |||
184 | gops->mc.isr_thread_stall = mc_gp10b_intr_thread_stall; | 184 | gops->mc.isr_thread_stall = mc_gp10b_intr_thread_stall; |
185 | gops->mc.isr_thread_nonstall = mc_gk20a_intr_thread_nonstall; | 185 | gops->mc.isr_thread_nonstall = mc_gk20a_intr_thread_nonstall; |
186 | gops->mc.isr_nonstall_cb = mc_gk20a_nonstall_cb; | 186 | gops->mc.isr_nonstall_cb = mc_gk20a_nonstall_cb; |
187 | 187 | gops->mc.enable = gk20a_mc_enable; | |
188 | gops->mc.disable = gk20a_mc_disable; | ||
189 | gops->mc.reset = gk20a_mc_reset; | ||
190 | gops->mc.boot_0 = gk20a_mc_boot_0; | ||
188 | } | 191 | } |