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-rw-r--r--drivers/gpu/nvgpu/gv11b/gr_gv11b.c86
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h152
2 files changed, 238 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
index f44c60b0..eefbdf3b 100644
--- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
@@ -3253,6 +3253,87 @@ static int gr_gv11b_handle_tpc_mpc_exception(struct gk20a *g,
3253 return 0; 3253 return 0;
3254} 3254}
3255 3255
3256static const u32 _num_ovr_perf_regs = 20;
3257static u32 _ovr_perf_regs[20] = { 0, };
3258
3259static void gv11b_gr_init_ovr_sm_dsm_perf(void)
3260{
3261 if (_ovr_perf_regs[0] != 0)
3262 return;
3263
3264 _ovr_perf_regs[0] = gr_egpc0_etpc0_sm_dsm_perf_counter_control_sel0_r();
3265 _ovr_perf_regs[1] = gr_egpc0_etpc0_sm_dsm_perf_counter_control_sel1_r();
3266 _ovr_perf_regs[2] = gr_egpc0_etpc0_sm_dsm_perf_counter_control0_r();
3267 _ovr_perf_regs[3] = gr_egpc0_etpc0_sm_dsm_perf_counter_control1_r();
3268 _ovr_perf_regs[4] = gr_egpc0_etpc0_sm_dsm_perf_counter_control2_r();
3269 _ovr_perf_regs[5] = gr_egpc0_etpc0_sm_dsm_perf_counter_control3_r();
3270 _ovr_perf_regs[6] = gr_egpc0_etpc0_sm_dsm_perf_counter_control4_r();
3271 _ovr_perf_regs[7] = gr_egpc0_etpc0_sm_dsm_perf_counter_control5_r();
3272 _ovr_perf_regs[8] = gr_egpc0_etpc0_sm_dsm_perf_counter0_control_r();
3273 _ovr_perf_regs[9] = gr_egpc0_etpc0_sm_dsm_perf_counter1_control_r();
3274 _ovr_perf_regs[10] = gr_egpc0_etpc0_sm_dsm_perf_counter2_control_r();
3275 _ovr_perf_regs[11] = gr_egpc0_etpc0_sm_dsm_perf_counter3_control_r();
3276 _ovr_perf_regs[12] = gr_egpc0_etpc0_sm_dsm_perf_counter4_control_r();
3277 _ovr_perf_regs[13] = gr_egpc0_etpc0_sm_dsm_perf_counter5_control_r();
3278 _ovr_perf_regs[14] = gr_egpc0_etpc0_sm_dsm_perf_counter6_control_r();
3279 _ovr_perf_regs[15] = gr_egpc0_etpc0_sm_dsm_perf_counter7_control_r();
3280
3281 _ovr_perf_regs[16] = gr_egpc0_etpc0_sm0_dsm_perf_counter4_r();
3282 _ovr_perf_regs[17] = gr_egpc0_etpc0_sm0_dsm_perf_counter5_r();
3283 _ovr_perf_regs[18] = gr_egpc0_etpc0_sm0_dsm_perf_counter6_r();
3284 _ovr_perf_regs[19] = gr_egpc0_etpc0_sm0_dsm_perf_counter7_r();
3285}
3286
3287/* Following are the blocks of registers that the ucode
3288 * stores in the extended region.
3289 */
3290/* == ctxsw_extended_sm_dsm_perf_counter_register_stride_v() ? */
3291static const u32 _num_sm_dsm_perf_regs;
3292/* == ctxsw_extended_sm_dsm_perf_counter_control_register_stride_v() ?*/
3293static const u32 _num_sm_dsm_perf_ctrl_regs = 2;
3294static u32 *_sm_dsm_perf_regs;
3295static u32 _sm_dsm_perf_ctrl_regs[2];
3296
3297static void gv11b_gr_init_sm_dsm_reg_info(void)
3298{
3299 if (_sm_dsm_perf_ctrl_regs[0] != 0)
3300 return;
3301
3302 _sm_dsm_perf_ctrl_regs[0] =
3303 gr_egpc0_etpc0_sm_dsm_perf_counter_control0_r();
3304 _sm_dsm_perf_ctrl_regs[1] =
3305 gr_egpc0_etpc0_sm_dsm_perf_counter_control5_r();
3306}
3307
3308static void gv11b_gr_get_sm_dsm_perf_regs(struct gk20a *g,
3309 u32 *num_sm_dsm_perf_regs,
3310 u32 **sm_dsm_perf_regs,
3311 u32 *perf_register_stride)
3312{
3313 *num_sm_dsm_perf_regs = _num_sm_dsm_perf_regs;
3314 *sm_dsm_perf_regs = _sm_dsm_perf_regs;
3315 *perf_register_stride =
3316 ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v();
3317}
3318
3319static void gv11b_gr_get_sm_dsm_perf_ctrl_regs(struct gk20a *g,
3320 u32 *num_sm_dsm_perf_ctrl_regs,
3321 u32 **sm_dsm_perf_ctrl_regs,
3322 u32 *ctrl_register_stride)
3323{
3324 *num_sm_dsm_perf_ctrl_regs = _num_sm_dsm_perf_ctrl_regs;
3325 *sm_dsm_perf_ctrl_regs = _sm_dsm_perf_ctrl_regs;
3326 *ctrl_register_stride =
3327 ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v();
3328}
3329
3330static void gv11b_gr_get_ovr_perf_regs(struct gk20a *g, u32 *num_ovr_perf_regs,
3331 u32 **ovr_perf_regs)
3332{
3333 *num_ovr_perf_regs = _num_ovr_perf_regs;
3334 *ovr_perf_regs = _ovr_perf_regs;
3335}
3336
3256void gv11b_init_gr(struct gpu_ops *gops) 3337void gv11b_init_gr(struct gpu_ops *gops)
3257{ 3338{
3258 gp10b_init_gr(gops); 3339 gp10b_init_gr(gops);
@@ -3337,4 +3418,9 @@ void gv11b_init_gr(struct gpu_ops *gops)
3337 gr_gv11b_handle_tpc_sm_ecc_exception; 3418 gr_gv11b_handle_tpc_sm_ecc_exception;
3338 gops->gr.handle_tpc_mpc_exception = 3419 gops->gr.handle_tpc_mpc_exception =
3339 gr_gv11b_handle_tpc_mpc_exception; 3420 gr_gv11b_handle_tpc_mpc_exception;
3421 gops->gr.init_ovr_sm_dsm_perf = gv11b_gr_init_ovr_sm_dsm_perf;
3422 gops->gr.init_sm_dsm_reg_info = gv11b_gr_init_sm_dsm_reg_info;
3423 gops->gr.get_sm_dsm_perf_regs = gv11b_gr_get_sm_dsm_perf_regs;
3424 gops->gr.get_sm_dsm_perf_ctrl_regs = gv11b_gr_get_sm_dsm_perf_ctrl_regs;
3425 gops->gr.get_ovr_perf_regs = gv11b_gr_get_ovr_perf_regs;
3340} 3426}
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h
index c9dbee52..153aef2f 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h
@@ -3998,6 +3998,158 @@ static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_m(void)
3998{ 3998{
3999 return 0x1 << 10; 3999 return 0x1 << 10;
4000} 4000}
4001static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control_sel0_r(void)
4002{
4003 return 0x00584200;
4004}
4005static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control_sel1_r(void)
4006{
4007 return 0x00584204;
4008}
4009static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control0_r(void)
4010{
4011 return 0x00584208;
4012}
4013static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control1_r(void)
4014{
4015 return 0x00584210;
4016}
4017static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control2_r(void)
4018{
4019 return 0x00584214;
4020}
4021static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control3_r(void)
4022{
4023 return 0x00584218;
4024}
4025static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control4_r(void)
4026{
4027 return 0x0058421c;
4028}
4029static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control5_r(void)
4030{
4031 return 0x0058420c;
4032}
4033static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter0_control_r(void)
4034{
4035 return 0x00584220;
4036}
4037static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter1_control_r(void)
4038{
4039 return 0x00584224;
4040}
4041static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter2_control_r(void)
4042{
4043 return 0x00584228;
4044}
4045static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter3_control_r(void)
4046{
4047 return 0x0058422c;
4048}
4049static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter4_control_r(void)
4050{
4051 return 0x00584230;
4052}
4053static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter5_control_r(void)
4054{
4055 return 0x00584234;
4056}
4057static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter6_control_r(void)
4058{
4059 return 0x00584238;
4060}
4061static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter7_control_r(void)
4062{
4063 return 0x0058423c;
4064}
4065static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter_status_s0_r(void)
4066{
4067 return 0x00584600;
4068}
4069static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter_status_s1_r(void)
4070{
4071 return 0x00584604;
4072}
4073static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter0_s0_r(void)
4074{
4075 return 0x00584624;
4076}
4077static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter1_s0_r(void)
4078{
4079 return 0x00584628;
4080}
4081static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter2_s0_r(void)
4082{
4083 return 0x0058462c;
4084}
4085static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter3_s0_r(void)
4086{
4087 return 0x00584630;
4088}
4089static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter0_s1_r(void)
4090{
4091 return 0x00584634;
4092}
4093static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter1_s1_r(void)
4094{
4095 return 0x00584638;
4096}
4097static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter2_s1_r(void)
4098{
4099 return 0x0058463c;
4100}
4101static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter3_s1_r(void)
4102{
4103 return 0x00584640;
4104}
4105static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter0_s2_r(void)
4106{
4107 return 0x00584644;
4108}
4109static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter1_s2_r(void)
4110{
4111 return 0x00584648;
4112}
4113static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter2_s2_r(void)
4114{
4115 return 0x0058464c;
4116}
4117static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter3_s2_r(void)
4118{
4119 return 0x00584650;
4120}
4121static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter0_s3_r(void)
4122{
4123 return 0x00584654;
4124}
4125static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter1_s3_r(void)
4126{
4127 return 0x00584658;
4128}
4129static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter2_s3_r(void)
4130{
4131 return 0x0058465c;
4132}
4133static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter3_s3_r(void)
4134{
4135 return 0x00584660;
4136}
4137static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter4_r(void)
4138{
4139 return 0x00584614;
4140}
4141static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter5_r(void)
4142{
4143 return 0x00584618;
4144}
4145static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter6_r(void)
4146{
4147 return 0x0058461c;
4148}
4149static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter7_r(void)
4150{
4151 return 0x00584620;
4152}
4001static inline u32 gr_fe_pwr_mode_r(void) 4153static inline u32 gr_fe_pwr_mode_r(void)
4002{ 4154{
4003 return 0x00404170; 4155 return 0x00404170;