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-rw-r--r--drivers/gpu/nvgpu/gk20a/clk_gk20a.h1
-rw-r--r--drivers/gpu/nvgpu/gm20b/clk_gm20b.c16
2 files changed, 13 insertions, 4 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/clk_gk20a.h b/drivers/gpu/nvgpu/gk20a/clk_gk20a.h
index eb9ce069..f07efa40 100644
--- a/drivers/gpu/nvgpu/gk20a/clk_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/clk_gk20a.h
@@ -96,6 +96,7 @@ struct clk_gk20a {
96 bool sw_ready; 96 bool sw_ready;
97 bool clk_hw_on; 97 bool clk_hw_on;
98 bool debugfs_set; 98 bool debugfs_set;
99 int pll_poweron_uv;
99}; 100};
100 101
101#if defined(CONFIG_COMMON_CLK) 102#if defined(CONFIG_COMMON_CLK)
diff --git a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c
index 8156fa00..96a8a5bc 100644
--- a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c
@@ -48,7 +48,8 @@
48#define DFS_EXT_CAL_EN BIT(9) 48#define DFS_EXT_CAL_EN BIT(9)
49#define DFS_EXT_STROBE BIT(16) 49#define DFS_EXT_STROBE BIT(16)
50 50
51#define BOOT_GPU_UV 1000000 /* gpu rail boot voltage 1.0V */ 51#define BOOT_GPU_UV_B1 1000000 /* gpu rail boot voltage 1.0V */
52#define BOOT_GPU_UV_C1 800000 /* gpu rail boot voltage 0.8V */
52#define ADC_SLOPE_UV 10000 /* default ADC detection slope 10mV */ 53#define ADC_SLOPE_UV 10000 /* default ADC detection slope 10mV */
53 54
54#define DVFS_SAFE_MARGIN 10 /* 10% */ 55#define DVFS_SAFE_MARGIN 10 /* 10% */
@@ -558,7 +559,7 @@ static int clk_enbale_pll_dvfs(struct gk20a *g)
558 559
559 data = gk20a_readl(g, trim_sys_gpcpll_cfg3_r()); 560 data = gk20a_readl(g, trim_sys_gpcpll_cfg3_r());
560 data = trim_sys_gpcpll_cfg3_dfs_testout_v(data); 561 data = trim_sys_gpcpll_cfg3_dfs_testout_v(data);
561 p->uvdet_offs = BOOT_GPU_UV - data * ADC_SLOPE_UV; 562 p->uvdet_offs = g->clk.pll_poweron_uv - data * ADC_SLOPE_UV;
562 p->uvdet_slope = ADC_SLOPE_UV; 563 p->uvdet_slope = ADC_SLOPE_UV;
563 return 0; 564 return 0;
564} 565}
@@ -1154,8 +1155,15 @@ static int gm20b_init_clk_setup_sw(struct gk20a *g)
1154 return 0; 1155 return 0;
1155 } 1156 }
1156 1157
1157 gpc_pll_params = (clk->gpc_pll.id == GM20B_GPC_PLL_C1) ? 1158 if (clk->gpc_pll.id == GM20B_GPC_PLL_C1) {
1158 gpc_pll_params_c1 : gpc_pll_params_b1; 1159 gpc_pll_params = gpc_pll_params_c1;
1160 if (!clk->pll_poweron_uv)
1161 clk->pll_poweron_uv = BOOT_GPU_UV_C1;
1162 } else {
1163 gpc_pll_params = gpc_pll_params_b1;
1164 if (!clk->pll_poweron_uv)
1165 clk->pll_poweron_uv = BOOT_GPU_UV_B1;
1166 }
1159 1167
1160 if (!gk20a_clk_get(g)) { 1168 if (!gk20a_clk_get(g)) {
1161 err = -EINVAL; 1169 err = -EINVAL;