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-rw-r--r--drivers/gpu/nvgpu/ctrl/ctrlvolt.h4
-rw-r--r--drivers/gpu/nvgpu/gk20a/gk20a.h1
2 files changed, 4 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/ctrl/ctrlvolt.h b/drivers/gpu/nvgpu/ctrl/ctrlvolt.h
index 04c7c4d1..9a095043 100644
--- a/drivers/gpu/nvgpu/ctrl/ctrlvolt.h
+++ b/drivers/gpu/nvgpu/ctrl/ctrlvolt.h
@@ -26,6 +26,7 @@
26#define CTRL_VOLT_DOMAIN_INVALID 0x00 26#define CTRL_VOLT_DOMAIN_INVALID 0x00
27#define CTRL_VOLT_DOMAIN_LOGIC 0x01 27#define CTRL_VOLT_DOMAIN_LOGIC 0x01
28#define CLK_PROG_VFE_ENTRY_LOGIC 0x00 28#define CLK_PROG_VFE_ENTRY_LOGIC 0x00
29#define CLK_PROG_VFE_ENTRY_SRAM 0x01
29 30
30/* 31/*
31 * Macros for Voltage Domain HAL. 32 * Macros for Voltage Domain HAL.
@@ -60,7 +61,8 @@
60 61
61enum nv_pmu_pmgr_pwm_source { 62enum nv_pmu_pmgr_pwm_source {
62 NV_PMU_PMGR_PWM_SOURCE_INVALID = 0, 63 NV_PMU_PMGR_PWM_SOURCE_INVALID = 0,
63 NV_PMU_PMGR_PWM_SOURCE_THERM_VID_PWM_1 = 5, 64 NV_PMU_PMGR_PWM_SOURCE_THERM_VID_PWM_0 = 4,
65 NV_PMU_PMGR_PWM_SOURCE_THERM_VID_PWM_1,
64 NV_PMU_PMGR_PWM_SOURCE_RSVD_0 = 7, 66 NV_PMU_PMGR_PWM_SOURCE_RSVD_0 = 7,
65 NV_PMU_PMGR_PWM_SOURCE_RSVD_1 = 8, 67 NV_PMU_PMGR_PWM_SOURCE_RSVD_1 = 8,
66}; 68};
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 22a9ce4c..ec0b4ba9 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -624,6 +624,7 @@ struct gpu_ops {
624 void (*disable_slowboot)(struct gk20a *g); 624 void (*disable_slowboot)(struct gk20a *g);
625 int (*init_clk_support)(struct gk20a *g); 625 int (*init_clk_support)(struct gk20a *g);
626 int (*suspend_clk_support)(struct gk20a *g); 626 int (*suspend_clk_support)(struct gk20a *g);
627 u32 (*get_crystal_clk_hz)(struct gk20a *g);
627 } clk; 628 } clk;
628 bool privsecurity; 629 bool privsecurity;
629 bool securegpccs; 630 bool securegpccs;