diff options
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/mc_gp10b.c | 16 |
2 files changed, 9 insertions, 9 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index dee74fdd..c7ade5f6 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -887,7 +887,6 @@ struct gpu_ops { | |||
887 | void (*reset)(struct gk20a *g, u32 units); | 887 | void (*reset)(struct gk20a *g, u32 units); |
888 | u32 (*boot_0)(struct gk20a *g, u32 *arch, u32 *impl, u32 *rev); | 888 | u32 (*boot_0)(struct gk20a *g, u32 *arch, u32 *impl, u32 *rev); |
889 | bool (*is_intr1_pending)(struct gk20a *g, enum nvgpu_unit unit, u32 mc_intr_1); | 889 | bool (*is_intr1_pending)(struct gk20a *g, enum nvgpu_unit unit, u32 mc_intr_1); |
890 | u32 intr_mask_restore[4]; | ||
891 | } mc; | 890 | } mc; |
892 | struct { | 891 | struct { |
893 | void (*show_dump)(struct gk20a *g, | 892 | void (*show_dump)(struct gk20a *g, |
@@ -1204,6 +1203,7 @@ struct gk20a { | |||
1204 | int client_refcount; /* open channels and ctrl nodes */ | 1203 | int client_refcount; /* open channels and ctrl nodes */ |
1205 | 1204 | ||
1206 | struct gpu_ops ops; | 1205 | struct gpu_ops ops; |
1206 | u32 mc_intr_mask_restore[4]; | ||
1207 | 1207 | ||
1208 | int irqs_enabled; | 1208 | int irqs_enabled; |
1209 | int irq_stall; /* can be same as irq_nonstall in case of PCI */ | 1209 | int irq_stall; /* can be same as irq_nonstall in case of PCI */ |
diff --git a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c index 5a1d5dcc..718869f6 100644 --- a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c | |||
@@ -29,7 +29,7 @@ void mc_gp10b_intr_enable(struct gk20a *g) | |||
29 | 29 | ||
30 | gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING), | 30 | gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING), |
31 | 0xffffffff); | 31 | 0xffffffff); |
32 | g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING] = | 32 | g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING] = |
33 | mc_intr_pfifo_pending_f() | | 33 | mc_intr_pfifo_pending_f() | |
34 | mc_intr_priv_ring_pending_f() | | 34 | mc_intr_priv_ring_pending_f() | |
35 | mc_intr_pbus_pending_f() | | 35 | mc_intr_pbus_pending_f() | |
@@ -37,15 +37,15 @@ void mc_gp10b_intr_enable(struct gk20a *g) | |||
37 | mc_intr_replayable_fault_pending_f() | | 37 | mc_intr_replayable_fault_pending_f() | |
38 | eng_intr_mask; | 38 | eng_intr_mask; |
39 | gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING), | 39 | gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING), |
40 | g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING]); | 40 | g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING]); |
41 | 41 | ||
42 | gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING), | 42 | gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING), |
43 | 0xffffffff); | 43 | 0xffffffff); |
44 | g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING] = | 44 | g->mc_intr_mask_restore[NVGPU_MC_INTR_NONSTALLING] = |
45 | mc_intr_pfifo_pending_f() | | 45 | mc_intr_pfifo_pending_f() | |
46 | eng_intr_mask; | 46 | eng_intr_mask; |
47 | gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING), | 47 | gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING), |
48 | g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]); | 48 | g->mc_intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]); |
49 | } | 49 | } |
50 | 50 | ||
51 | void mc_gp10b_intr_unit_config(struct gk20a *g, bool enable, | 51 | void mc_gp10b_intr_unit_config(struct gk20a *g, bool enable, |
@@ -58,11 +58,11 @@ void mc_gp10b_intr_unit_config(struct gk20a *g, bool enable, | |||
58 | NVGPU_MC_INTR_NONSTALLING); | 58 | NVGPU_MC_INTR_NONSTALLING); |
59 | if (enable) { | 59 | if (enable) { |
60 | reg = mc_intr_en_set_r(intr_index); | 60 | reg = mc_intr_en_set_r(intr_index); |
61 | g->ops.mc.intr_mask_restore[intr_index] |= mask; | 61 | g->mc_intr_mask_restore[intr_index] |= mask; |
62 | 62 | ||
63 | } else { | 63 | } else { |
64 | reg = mc_intr_en_clear_r(intr_index); | 64 | reg = mc_intr_en_clear_r(intr_index); |
65 | g->ops.mc.intr_mask_restore[intr_index] &= ~mask; | 65 | g->mc_intr_mask_restore[intr_index] &= ~mask; |
66 | } | 66 | } |
67 | 67 | ||
68 | gk20a_writel(g, reg, mask); | 68 | gk20a_writel(g, reg, mask); |
@@ -136,7 +136,7 @@ void mc_gp10b_intr_stall_pause(struct gk20a *g) | |||
136 | void mc_gp10b_intr_stall_resume(struct gk20a *g) | 136 | void mc_gp10b_intr_stall_resume(struct gk20a *g) |
137 | { | 137 | { |
138 | gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING), | 138 | gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING), |
139 | g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING]); | 139 | g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING]); |
140 | } | 140 | } |
141 | 141 | ||
142 | u32 mc_gp10b_intr_nonstall(struct gk20a *g) | 142 | u32 mc_gp10b_intr_nonstall(struct gk20a *g) |
@@ -153,7 +153,7 @@ void mc_gp10b_intr_nonstall_pause(struct gk20a *g) | |||
153 | void mc_gp10b_intr_nonstall_resume(struct gk20a *g) | 153 | void mc_gp10b_intr_nonstall_resume(struct gk20a *g) |
154 | { | 154 | { |
155 | gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING), | 155 | gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING), |
156 | g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]); | 156 | g->mc_intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]); |
157 | } | 157 | } |
158 | 158 | ||
159 | bool mc_gp10b_is_intr1_pending(struct gk20a *g, | 159 | bool mc_gp10b_is_intr1_pending(struct gk20a *g, |