diff options
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 5 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.h | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_pri_gk20a.h | 32 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/hal_gp106.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/hal_gv100.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 111 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/gr_pri_gv11b.h | 50 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | 1 |
14 files changed, 205 insertions, 14 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index efb425c2..164668cb 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -461,6 +461,11 @@ struct gpu_ops { | |||
461 | struct aiv_list_gk20a *regs, | 461 | struct aiv_list_gk20a *regs, |
462 | u32 *count, u32 *offset, | 462 | u32 *count, u32 *offset, |
463 | u32 max_cnt, u32 base, u32 mask); | 463 | u32 max_cnt, u32 base, u32 mask); |
464 | int (*decode_priv_addr)(struct gk20a *g, u32 addr, | ||
465 | int *addr_type, | ||
466 | u32 *gpc_num, u32 *tpc_num, | ||
467 | u32 *ppc_num, u32 *be_num, | ||
468 | u32 *broadcast_flags); | ||
464 | } gr; | 469 | } gr; |
465 | struct { | 470 | struct { |
466 | void (*init_hw)(struct gk20a *g); | 471 | void (*init_hw)(struct gk20a *g); |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 65144cc5..3912a1df 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -6247,7 +6247,7 @@ static int gr_gk20a_find_priv_offset_in_pm_buffer(struct gk20a *g, | |||
6247 | u32 *priv_offset); | 6247 | u32 *priv_offset); |
6248 | 6248 | ||
6249 | /* This function will decode a priv address and return the partition type and numbers. */ | 6249 | /* This function will decode a priv address and return the partition type and numbers. */ |
6250 | static int gr_gk20a_decode_priv_addr(struct gk20a *g, u32 addr, | 6250 | int gr_gk20a_decode_priv_addr(struct gk20a *g, u32 addr, |
6251 | int *addr_type, /* enum ctxsw_addr_type */ | 6251 | int *addr_type, /* enum ctxsw_addr_type */ |
6252 | u32 *gpc_num, u32 *tpc_num, u32 *ppc_num, u32 *be_num, | 6252 | u32 *gpc_num, u32 *tpc_num, u32 *ppc_num, u32 *be_num, |
6253 | u32 *broadcast_flags) | 6253 | u32 *broadcast_flags) |
@@ -6365,7 +6365,7 @@ static int gr_gk20a_create_priv_addr_table(struct gk20a *g, | |||
6365 | 6365 | ||
6366 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, "addr=0x%x", addr); | 6366 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, "addr=0x%x", addr); |
6367 | 6367 | ||
6368 | err = gr_gk20a_decode_priv_addr(g, addr, &addr_type, | 6368 | err = g->ops.gr.decode_priv_addr(g, addr, &addr_type, |
6369 | &gpc_num, &tpc_num, &ppc_num, &be_num, | 6369 | &gpc_num, &tpc_num, &ppc_num, &be_num, |
6370 | &broadcast_flags); | 6370 | &broadcast_flags); |
6371 | gk20a_dbg(gpu_dbg_gpu_dbg, "addr_type = %d", addr_type); | 6371 | gk20a_dbg(gpu_dbg_gpu_dbg, "addr_type = %d", addr_type); |
@@ -7211,7 +7211,7 @@ static int gr_gk20a_find_priv_offset_in_buffer(struct gk20a *g, | |||
7211 | 7211 | ||
7212 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, "addr=0x%x", addr); | 7212 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, "addr=0x%x", addr); |
7213 | 7213 | ||
7214 | err = gr_gk20a_decode_priv_addr(g, addr, &addr_type, | 7214 | err = g->ops.gr.decode_priv_addr(g, addr, &addr_type, |
7215 | &gpc_num, &tpc_num, &ppc_num, &be_num, | 7215 | &gpc_num, &tpc_num, &ppc_num, &be_num, |
7216 | &broadcast_flags); | 7216 | &broadcast_flags); |
7217 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, | 7217 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h index a80116b7..ee76148a 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h | |||
@@ -821,4 +821,8 @@ int gr_gk20a_add_ctxsw_reg_perf_pma(struct ctxsw_buf_offset_map_entry *map, | |||
821 | struct aiv_list_gk20a *regs, | 821 | struct aiv_list_gk20a *regs, |
822 | u32 *count, u32 *offset, | 822 | u32 *count, u32 *offset, |
823 | u32 max_cnt, u32 base, u32 mask); | 823 | u32 max_cnt, u32 base, u32 mask); |
824 | int gr_gk20a_decode_priv_addr(struct gk20a *g, u32 addr, | ||
825 | int *addr_type, | ||
826 | u32 *gpc_num, u32 *tpc_num, u32 *ppc_num, u32 *be_num, | ||
827 | u32 *broadcast_flags); | ||
824 | #endif /*__GR_GK20A_H__*/ | 828 | #endif /*__GR_GK20A_H__*/ |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_pri_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_pri_gk20a.h index d0b6df47..af390833 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_pri_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_pri_gk20a.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GK20A Graphics Context Pri Register Addressing | 2 | * GK20A Graphics Context Pri Register Addressing |
3 | * | 3 | * |
4 | * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -245,17 +245,27 @@ enum ctxsw_addr_type { | |||
245 | CTXSW_ADDR_TYPE_FBPA = 6, | 245 | CTXSW_ADDR_TYPE_FBPA = 6, |
246 | CTXSW_ADDR_TYPE_EGPC = 7, | 246 | CTXSW_ADDR_TYPE_EGPC = 7, |
247 | CTXSW_ADDR_TYPE_ETPC = 8, | 247 | CTXSW_ADDR_TYPE_ETPC = 8, |
248 | CTXSW_ADDR_TYPE_ROP = 9, | ||
249 | CTXSW_ADDR_TYPE_FBP = 10, | ||
248 | }; | 250 | }; |
249 | 251 | ||
250 | #define PRI_BROADCAST_FLAGS_NONE 0 | 252 | #define PRI_BROADCAST_FLAGS_NONE 0 |
251 | #define PRI_BROADCAST_FLAGS_GPC BIT(0) | 253 | #define PRI_BROADCAST_FLAGS_GPC BIT(0) |
252 | #define PRI_BROADCAST_FLAGS_TPC BIT(1) | 254 | #define PRI_BROADCAST_FLAGS_TPC BIT(1) |
253 | #define PRI_BROADCAST_FLAGS_BE BIT(2) | 255 | #define PRI_BROADCAST_FLAGS_BE BIT(2) |
254 | #define PRI_BROADCAST_FLAGS_PPC BIT(3) | 256 | #define PRI_BROADCAST_FLAGS_PPC BIT(3) |
255 | #define PRI_BROADCAST_FLAGS_LTCS BIT(4) | 257 | #define PRI_BROADCAST_FLAGS_LTCS BIT(4) |
256 | #define PRI_BROADCAST_FLAGS_LTSS BIT(5) | 258 | #define PRI_BROADCAST_FLAGS_LTSS BIT(5) |
257 | #define PRI_BROADCAST_FLAGS_FBPA BIT(6) | 259 | #define PRI_BROADCAST_FLAGS_FBPA BIT(6) |
258 | #define PRI_BROADCAST_FLAGS_EGPC BIT(7) | 260 | #define PRI_BROADCAST_FLAGS_EGPC BIT(7) |
259 | #define PRI_BROADCAST_FLAGS_ETPC BIT(8) | 261 | #define PRI_BROADCAST_FLAGS_ETPC BIT(8) |
262 | #define PRI_BROADCAST_FLAGS_PMMGPC BIT(9) | ||
263 | #define PRI_BROADCAST_FLAGS_PMM_GPCS BIT(10) | ||
264 | #define PRI_BROADCAST_FLAGS_PMM_GPCGS_GPCTPCA BIT(11) | ||
265 | #define PRI_BROADCAST_FLAGS_PMM_GPCGS_GPCTPCB BIT(12) | ||
266 | #define PRI_BROADCAST_FLAGS_PMMFBP BIT(13) | ||
267 | #define PRI_BROADCAST_FLAGS_PMM_FBPS BIT(14) | ||
268 | #define PRI_BROADCAST_FLAGS_PMM_FBPGS_LTC BIT(15) | ||
269 | #define PRI_BROADCAST_FLAGS_PMM_FBPGS_ROP BIT(16) | ||
260 | 270 | ||
261 | #endif /* GR_PRI_GK20A_H */ | 271 | #endif /* GR_PRI_GK20A_H */ |
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index 82e8826e..65e75374 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c | |||
@@ -320,6 +320,7 @@ static const struct gpu_ops gm20b_ops = { | |||
320 | .handle_semaphore_pending = gk20a_gr_handle_semaphore_pending, | 320 | .handle_semaphore_pending = gk20a_gr_handle_semaphore_pending, |
321 | .add_ctxsw_reg_pm_fbpa = gr_gk20a_add_ctxsw_reg_pm_fbpa, | 321 | .add_ctxsw_reg_pm_fbpa = gr_gk20a_add_ctxsw_reg_pm_fbpa, |
322 | .add_ctxsw_reg_perf_pma = gr_gk20a_add_ctxsw_reg_perf_pma, | 322 | .add_ctxsw_reg_perf_pma = gr_gk20a_add_ctxsw_reg_perf_pma, |
323 | .decode_priv_addr = gr_gk20a_decode_priv_addr, | ||
323 | }, | 324 | }, |
324 | .fb = { | 325 | .fb = { |
325 | .reset = fb_gk20a_reset, | 326 | .reset = fb_gk20a_reset, |
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c index cad8ed97..4daa510c 100644 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c | |||
@@ -383,6 +383,7 @@ static const struct gpu_ops gp106_ops = { | |||
383 | .handle_semaphore_pending = gk20a_gr_handle_semaphore_pending, | 383 | .handle_semaphore_pending = gk20a_gr_handle_semaphore_pending, |
384 | .add_ctxsw_reg_pm_fbpa = gr_gk20a_add_ctxsw_reg_pm_fbpa, | 384 | .add_ctxsw_reg_pm_fbpa = gr_gk20a_add_ctxsw_reg_pm_fbpa, |
385 | .add_ctxsw_reg_perf_pma = gr_gk20a_add_ctxsw_reg_perf_pma, | 385 | .add_ctxsw_reg_perf_pma = gr_gk20a_add_ctxsw_reg_perf_pma, |
386 | .decode_priv_addr = gr_gk20a_decode_priv_addr, | ||
386 | }, | 387 | }, |
387 | .fb = { | 388 | .fb = { |
388 | .reset = gp106_fb_reset, | 389 | .reset = gp106_fb_reset, |
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 97c273cb..2f122e20 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c | |||
@@ -351,6 +351,7 @@ static const struct gpu_ops gp10b_ops = { | |||
351 | .handle_semaphore_pending = gk20a_gr_handle_semaphore_pending, | 351 | .handle_semaphore_pending = gk20a_gr_handle_semaphore_pending, |
352 | .add_ctxsw_reg_pm_fbpa = gr_gk20a_add_ctxsw_reg_pm_fbpa, | 352 | .add_ctxsw_reg_pm_fbpa = gr_gk20a_add_ctxsw_reg_pm_fbpa, |
353 | .add_ctxsw_reg_perf_pma = gr_gk20a_add_ctxsw_reg_perf_pma, | 353 | .add_ctxsw_reg_perf_pma = gr_gk20a_add_ctxsw_reg_perf_pma, |
354 | .decode_priv_addr = gr_gk20a_decode_priv_addr, | ||
354 | }, | 355 | }, |
355 | .fb = { | 356 | .fb = { |
356 | .reset = fb_gk20a_reset, | 357 | .reset = fb_gk20a_reset, |
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index cf751135..5cafcaae 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c | |||
@@ -430,6 +430,7 @@ static const struct gpu_ops gv100_ops = { | |||
430 | .handle_semaphore_pending = gk20a_gr_handle_semaphore_pending, | 430 | .handle_semaphore_pending = gk20a_gr_handle_semaphore_pending, |
431 | .add_ctxsw_reg_pm_fbpa = gr_gv100_add_ctxsw_reg_pm_fbpa, | 431 | .add_ctxsw_reg_pm_fbpa = gr_gv100_add_ctxsw_reg_pm_fbpa, |
432 | .add_ctxsw_reg_perf_pma = gr_gv100_add_ctxsw_reg_perf_pma, | 432 | .add_ctxsw_reg_perf_pma = gr_gv100_add_ctxsw_reg_perf_pma, |
433 | .decode_priv_addr = gr_gv11b_decode_priv_addr, | ||
433 | }, | 434 | }, |
434 | .fb = { | 435 | .fb = { |
435 | .reset = gv100_fb_reset, | 436 | .reset = gv100_fb_reset, |
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index c43c6e83..61649d06 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c | |||
@@ -46,6 +46,7 @@ | |||
46 | #include "gv11b/mm_gv11b.h" | 46 | #include "gv11b/mm_gv11b.h" |
47 | #include "gv11b/subctx_gv11b.h" | 47 | #include "gv11b/subctx_gv11b.h" |
48 | #include "gv11b/gv11b.h" | 48 | #include "gv11b/gv11b.h" |
49 | #include "gv11b/gr_pri_gv11b.h" | ||
49 | 50 | ||
50 | #include <nvgpu/hw/gv11b/hw_gr_gv11b.h> | 51 | #include <nvgpu/hw/gv11b/hw_gr_gv11b.h> |
51 | #include <nvgpu/hw/gv11b/hw_fifo_gv11b.h> | 52 | #include <nvgpu/hw/gv11b/hw_fifo_gv11b.h> |
@@ -4400,3 +4401,113 @@ int gr_gv11b_handle_ssync_hww(struct gk20a *g) | |||
4400 | gr_ssync_hww_esr_reset_active_f()); | 4401 | gr_ssync_hww_esr_reset_active_f()); |
4401 | return -EFAULT; | 4402 | return -EFAULT; |
4402 | } | 4403 | } |
4404 | |||
4405 | /* | ||
4406 | * This function will decode a priv address and return the partition | ||
4407 | * type and numbers | ||
4408 | */ | ||
4409 | int gr_gv11b_decode_priv_addr(struct gk20a *g, u32 addr, | ||
4410 | int *addr_type, /* enum ctxsw_addr_type */ | ||
4411 | u32 *gpc_num, u32 *tpc_num, u32 *ppc_num, u32 *be_num, | ||
4412 | u32 *broadcast_flags) | ||
4413 | { | ||
4414 | u32 gpc_addr; | ||
4415 | |||
4416 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, "addr=0x%x", addr); | ||
4417 | |||
4418 | /* setup defaults */ | ||
4419 | *addr_type = CTXSW_ADDR_TYPE_SYS; | ||
4420 | *broadcast_flags = PRI_BROADCAST_FLAGS_NONE; | ||
4421 | *gpc_num = 0; | ||
4422 | *tpc_num = 0; | ||
4423 | *ppc_num = 0; | ||
4424 | *be_num = 0; | ||
4425 | |||
4426 | if (pri_is_gpc_addr(g, addr)) { | ||
4427 | *addr_type = CTXSW_ADDR_TYPE_GPC; | ||
4428 | gpc_addr = pri_gpccs_addr_mask(addr); | ||
4429 | if (pri_is_gpc_addr_shared(g, addr)) { | ||
4430 | *addr_type = CTXSW_ADDR_TYPE_GPC; | ||
4431 | *broadcast_flags |= PRI_BROADCAST_FLAGS_GPC; | ||
4432 | } else | ||
4433 | *gpc_num = pri_get_gpc_num(g, addr); | ||
4434 | |||
4435 | if (pri_is_ppc_addr(g, gpc_addr)) { | ||
4436 | *addr_type = CTXSW_ADDR_TYPE_PPC; | ||
4437 | if (pri_is_ppc_addr_shared(g, gpc_addr)) { | ||
4438 | *broadcast_flags |= PRI_BROADCAST_FLAGS_PPC; | ||
4439 | return 0; | ||
4440 | } | ||
4441 | } | ||
4442 | if (g->ops.gr.is_tpc_addr(g, gpc_addr)) { | ||
4443 | *addr_type = CTXSW_ADDR_TYPE_TPC; | ||
4444 | if (pri_is_tpc_addr_shared(g, gpc_addr)) { | ||
4445 | *broadcast_flags |= PRI_BROADCAST_FLAGS_TPC; | ||
4446 | return 0; | ||
4447 | } | ||
4448 | *tpc_num = g->ops.gr.get_tpc_num(g, gpc_addr); | ||
4449 | } | ||
4450 | return 0; | ||
4451 | } else if (pri_is_be_addr(g, addr)) { | ||
4452 | *addr_type = CTXSW_ADDR_TYPE_BE; | ||
4453 | if (pri_is_be_addr_shared(g, addr)) { | ||
4454 | *broadcast_flags |= PRI_BROADCAST_FLAGS_BE; | ||
4455 | return 0; | ||
4456 | } | ||
4457 | *be_num = pri_get_be_num(g, addr); | ||
4458 | return 0; | ||
4459 | } else if (pri_is_ltc_addr(addr)) { | ||
4460 | *addr_type = CTXSW_ADDR_TYPE_LTCS; | ||
4461 | if (g->ops.gr.is_ltcs_ltss_addr(g, addr)) | ||
4462 | *broadcast_flags |= PRI_BROADCAST_FLAGS_LTCS; | ||
4463 | else if (g->ops.gr.is_ltcn_ltss_addr(g, addr)) | ||
4464 | *broadcast_flags |= PRI_BROADCAST_FLAGS_LTSS; | ||
4465 | return 0; | ||
4466 | } else if (pri_is_fbpa_addr(g, addr)) { | ||
4467 | *addr_type = CTXSW_ADDR_TYPE_FBPA; | ||
4468 | if (pri_is_fbpa_addr_shared(g, addr)) { | ||
4469 | *broadcast_flags |= PRI_BROADCAST_FLAGS_FBPA; | ||
4470 | return 0; | ||
4471 | } | ||
4472 | return 0; | ||
4473 | } else if (g->ops.gr.is_egpc_addr && g->ops.gr.is_egpc_addr(g, addr)) { | ||
4474 | return g->ops.gr.decode_egpc_addr(g, | ||
4475 | addr, addr_type, gpc_num, | ||
4476 | tpc_num, broadcast_flags); | ||
4477 | } else if (PRI_PMMGS_BASE_ADDR_MASK(addr) == | ||
4478 | NV_PERF_PMMGPC_GPCGS_GPCTPCA) { | ||
4479 | *broadcast_flags |= (PRI_BROADCAST_FLAGS_PMM_GPCGS_GPCTPCA | | ||
4480 | PRI_BROADCAST_FLAGS_PMMGPC); | ||
4481 | *addr_type = CTXSW_ADDR_TYPE_GPC; | ||
4482 | return 0; | ||
4483 | } else if (PRI_PMMGS_BASE_ADDR_MASK(addr) == | ||
4484 | NV_PERF_PMMGPC_GPCGS_GPCTPCB) { | ||
4485 | *broadcast_flags |= (PRI_BROADCAST_FLAGS_PMM_GPCGS_GPCTPCB | | ||
4486 | PRI_BROADCAST_FLAGS_PMMGPC); | ||
4487 | *addr_type = CTXSW_ADDR_TYPE_GPC; | ||
4488 | return 0; | ||
4489 | } else if (PRI_PMMGS_BASE_ADDR_MASK(addr) == NV_PERF_PMMFBP_FBPGS_LTC) { | ||
4490 | *broadcast_flags |= (PRI_BROADCAST_FLAGS_PMM_FBPGS_LTC | | ||
4491 | PRI_BROADCAST_FLAGS_PMMFBP); | ||
4492 | *addr_type = CTXSW_ADDR_TYPE_LTCS; | ||
4493 | return 0; | ||
4494 | } else if (PRI_PMMGS_BASE_ADDR_MASK(addr) == NV_PERF_PMMFBP_FBPGS_ROP) { | ||
4495 | *broadcast_flags |= (PRI_BROADCAST_FLAGS_PMM_FBPGS_ROP | | ||
4496 | PRI_BROADCAST_FLAGS_PMMFBP); | ||
4497 | *addr_type = CTXSW_ADDR_TYPE_ROP; | ||
4498 | return 0; | ||
4499 | } else if (PRI_PMMS_BASE_ADDR_MASK(addr) == NV_PERF_PMMGPC_GPCS) { | ||
4500 | *broadcast_flags |= (PRI_BROADCAST_FLAGS_PMM_GPCS | | ||
4501 | PRI_BROADCAST_FLAGS_PMMGPC); | ||
4502 | *addr_type = CTXSW_ADDR_TYPE_GPC; | ||
4503 | return 0; | ||
4504 | } else if (PRI_PMMS_BASE_ADDR_MASK(addr) == NV_PERF_PMMFBP_FBPS) { | ||
4505 | *broadcast_flags |= (PRI_BROADCAST_FLAGS_PMM_FBPS | | ||
4506 | PRI_BROADCAST_FLAGS_PMMFBP); | ||
4507 | *addr_type = CTXSW_ADDR_TYPE_FBP; | ||
4508 | return 0; | ||
4509 | } | ||
4510 | |||
4511 | *addr_type = CTXSW_ADDR_TYPE_SYS; | ||
4512 | return 0; | ||
4513 | } | ||
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index 018938f6..7d286535 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h | |||
@@ -234,4 +234,8 @@ void gr_gv11b_update_ctxsw_preemption_mode(struct gk20a *g, | |||
234 | int gr_gv11b_handle_ssync_hww(struct gk20a *g); | 234 | int gr_gv11b_handle_ssync_hww(struct gk20a *g); |
235 | u32 gv11b_gr_sm_offset(struct gk20a *g, u32 sm); | 235 | u32 gv11b_gr_sm_offset(struct gk20a *g, u32 sm); |
236 | 236 | ||
237 | int gr_gv11b_decode_priv_addr(struct gk20a *g, u32 addr, | ||
238 | int *addr_type, | ||
239 | u32 *gpc_num, u32 *tpc_num, u32 *ppc_num, u32 *be_num, | ||
240 | u32 *broadcast_flags); | ||
237 | #endif | 241 | #endif |
diff --git a/drivers/gpu/nvgpu/gv11b/gr_pri_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_pri_gv11b.h new file mode 100644 index 00000000..c71f4c9c --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/gr_pri_gv11b.h | |||
@@ -0,0 +1,50 @@ | |||
1 | /* | ||
2 | * GV11B/GV100 Graphics Context Pri Register Addressing | ||
3 | * | ||
4 | * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice shall be included in | ||
14 | * all copies or substantial portions of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
22 | * DEALINGS IN THE SOFTWARE. | ||
23 | */ | ||
24 | #ifndef GR_PRI_GV11B_H | ||
25 | #define GR_PRI_GV11B_H | ||
26 | |||
27 | /* | ||
28 | * These convenience macros are generally for use in the management/modificaiton | ||
29 | * of the context state store for gr/compute contexts. | ||
30 | */ | ||
31 | |||
32 | /* Broadcast PMM defines */ | ||
33 | #define NV_PERF_PMMFBP_FBPGS_LTC 0x00250800 | ||
34 | #define NV_PERF_PMMFBP_FBPGS_ROP 0x00250A00 | ||
35 | #define NV_PERF_PMMGPC_GPCGS_GPCTPCA 0x00250000 | ||
36 | #define NV_PERF_PMMGPC_GPCGS_GPCTPCB 0x00250200 | ||
37 | #define NV_PERF_PMMGPC_GPCS 0x00278000 | ||
38 | #define NV_PERF_PMMFBP_FBPS 0x0027C000 | ||
39 | |||
40 | #define PRI_PMMGS_ADDR_WIDTH 9 | ||
41 | #define PRI_PMMS_ADDR_WIDTH 14 | ||
42 | |||
43 | /* Get the offset to be added to the chiplet base addr to get the unicast address */ | ||
44 | #define PRI_PMMGS_OFFSET_MASK(addr) ((addr) & ((1 << PRI_PMMGS_ADDR_WIDTH) - 1)) | ||
45 | #define PRI_PMMGS_BASE_ADDR_MASK(addr) ((addr) & (~((1 << PRI_PMMGS_ADDR_WIDTH) - 1))) | ||
46 | |||
47 | #define PRI_PMMS_ADDR_MASK(addr) ((addr) & ((1 << PRI_PMMS_ADDR_WIDTH) - 1)) | ||
48 | #define PRI_PMMS_BASE_ADDR_MASK(addr) ((addr) & (~((1 << PRI_PMMS_ADDR_WIDTH) - 1))) | ||
49 | |||
50 | #endif /* GR_PRI_GV11B_H */ | ||
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 9fccce0b..c33844dc 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c | |||
@@ -403,6 +403,7 @@ static const struct gpu_ops gv11b_ops = { | |||
403 | .handle_semaphore_pending = gk20a_gr_handle_semaphore_pending, | 403 | .handle_semaphore_pending = gk20a_gr_handle_semaphore_pending, |
404 | .add_ctxsw_reg_pm_fbpa = gr_gk20a_add_ctxsw_reg_pm_fbpa, | 404 | .add_ctxsw_reg_pm_fbpa = gr_gk20a_add_ctxsw_reg_pm_fbpa, |
405 | .add_ctxsw_reg_perf_pma = gr_gk20a_add_ctxsw_reg_perf_pma, | 405 | .add_ctxsw_reg_perf_pma = gr_gk20a_add_ctxsw_reg_perf_pma, |
406 | .decode_priv_addr = gr_gv11b_decode_priv_addr, | ||
406 | }, | 407 | }, |
407 | .fb = { | 408 | .fb = { |
408 | .reset = gv11b_fb_reset, | 409 | .reset = gv11b_fb_reset, |
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c index 4ee50f25..34d0fc16 100644 --- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c | |||
@@ -225,6 +225,7 @@ static const struct gpu_ops vgpu_gp10b_ops = { | |||
225 | gr_gp10b_get_max_gfxp_wfi_timeout_count, | 225 | gr_gp10b_get_max_gfxp_wfi_timeout_count, |
226 | .add_ctxsw_reg_pm_fbpa = gr_gk20a_add_ctxsw_reg_pm_fbpa, | 226 | .add_ctxsw_reg_pm_fbpa = gr_gk20a_add_ctxsw_reg_pm_fbpa, |
227 | .add_ctxsw_reg_perf_pma = gr_gk20a_add_ctxsw_reg_perf_pma, | 227 | .add_ctxsw_reg_perf_pma = gr_gk20a_add_ctxsw_reg_perf_pma, |
228 | .decode_priv_addr = gr_gk20a_decode_priv_addr, | ||
228 | }, | 229 | }, |
229 | .fb = { | 230 | .fb = { |
230 | .reset = fb_gk20a_reset, | 231 | .reset = fb_gk20a_reset, |
diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c index ae30246f..d63b91fc 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | |||
@@ -261,6 +261,7 @@ static const struct gpu_ops vgpu_gv11b_ops = { | |||
261 | gr_gv11b_get_max_gfxp_wfi_timeout_count, | 261 | gr_gv11b_get_max_gfxp_wfi_timeout_count, |
262 | .add_ctxsw_reg_pm_fbpa = gr_gk20a_add_ctxsw_reg_pm_fbpa, | 262 | .add_ctxsw_reg_pm_fbpa = gr_gk20a_add_ctxsw_reg_pm_fbpa, |
263 | .add_ctxsw_reg_perf_pma = gr_gk20a_add_ctxsw_reg_perf_pma, | 263 | .add_ctxsw_reg_perf_pma = gr_gk20a_add_ctxsw_reg_perf_pma, |
264 | .decode_priv_addr = gr_gv11b_decode_priv_addr, | ||
264 | }, | 265 | }, |
265 | .fb = { | 266 | .fb = { |
266 | .reset = gv11b_fb_reset, | 267 | .reset = gv11b_fb_reset, |