diff options
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/common/linux/ioctl_channel.c | 15 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/linux/ioctl_tsg.c | 34 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/mm/mm.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/ce2_gk20a.c | 11 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/ce2_gk20a.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | 26 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fifo_gk20a.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/tsg_gk20a.c | 23 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/hal_gp106.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/fifo_vgpu.c | 19 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/fifo_vgpu.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gm20b/vgpu_hal_gm20b.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c | 1 |
16 files changed, 0 insertions, 138 deletions
diff --git a/drivers/gpu/nvgpu/common/linux/ioctl_channel.c b/drivers/gpu/nvgpu/common/linux/ioctl_channel.c index 6feb6fb7..31651795 100644 --- a/drivers/gpu/nvgpu/common/linux/ioctl_channel.c +++ b/drivers/gpu/nvgpu/common/linux/ioctl_channel.c | |||
@@ -1314,21 +1314,6 @@ long gk20a_channel_ioctl(struct file *filp, | |||
1314 | ((struct nvgpu_get_param_args *)buf)->value = | 1314 | ((struct nvgpu_get_param_args *)buf)->value = |
1315 | ch->has_timedout; | 1315 | ch->has_timedout; |
1316 | break; | 1316 | break; |
1317 | case NVGPU_IOCTL_CHANNEL_SET_PRIORITY: | ||
1318 | err = gk20a_busy(ch->g); | ||
1319 | if (err) { | ||
1320 | dev_err(dev, | ||
1321 | "%s: failed to host gk20a for ioctl cmd: 0x%x", | ||
1322 | __func__, cmd); | ||
1323 | break; | ||
1324 | } | ||
1325 | err = ch->g->ops.fifo.channel_set_priority(ch, | ||
1326 | ((struct nvgpu_set_priority_args *)buf)->priority); | ||
1327 | |||
1328 | gk20a_idle(ch->g); | ||
1329 | gk20a_channel_trace_sched_param( | ||
1330 | trace_gk20a_channel_set_priority, ch); | ||
1331 | break; | ||
1332 | case NVGPU_IOCTL_CHANNEL_ENABLE: | 1317 | case NVGPU_IOCTL_CHANNEL_ENABLE: |
1333 | err = gk20a_busy(ch->g); | 1318 | err = gk20a_busy(ch->g); |
1334 | if (err) { | 1319 | if (err) { |
diff --git a/drivers/gpu/nvgpu/common/linux/ioctl_tsg.c b/drivers/gpu/nvgpu/common/linux/ioctl_tsg.c index eb223382..b17d7e74 100644 --- a/drivers/gpu/nvgpu/common/linux/ioctl_tsg.c +++ b/drivers/gpu/nvgpu/common/linux/ioctl_tsg.c | |||
@@ -296,33 +296,6 @@ int nvgpu_ioctl_tsg_dev_release(struct inode *inode, struct file *filp) | |||
296 | return 0; | 296 | return 0; |
297 | } | 297 | } |
298 | 298 | ||
299 | static int gk20a_tsg_ioctl_set_priority(struct gk20a *g, | ||
300 | struct tsg_gk20a *tsg, struct nvgpu_set_priority_args *arg) | ||
301 | { | ||
302 | struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); | ||
303 | struct gk20a_sched_ctrl *sched = &l->sched_ctrl; | ||
304 | int err; | ||
305 | |||
306 | nvgpu_mutex_acquire(&sched->control_lock); | ||
307 | if (sched->control_locked) { | ||
308 | err = -EPERM; | ||
309 | goto done; | ||
310 | } | ||
311 | |||
312 | err = gk20a_busy(g); | ||
313 | if (err) { | ||
314 | nvgpu_err(g, "failed to power on gpu"); | ||
315 | goto done; | ||
316 | } | ||
317 | |||
318 | err = gk20a_tsg_set_priority(g, tsg, arg->priority); | ||
319 | |||
320 | gk20a_idle(g); | ||
321 | done: | ||
322 | nvgpu_mutex_release(&sched->control_lock); | ||
323 | return err; | ||
324 | } | ||
325 | |||
326 | static int gk20a_tsg_ioctl_set_runlist_interleave(struct gk20a *g, | 299 | static int gk20a_tsg_ioctl_set_runlist_interleave(struct gk20a *g, |
327 | struct tsg_gk20a *tsg, struct nvgpu_runlist_interleave_args *arg) | 300 | struct tsg_gk20a *tsg, struct nvgpu_runlist_interleave_args *arg) |
328 | { | 301 | { |
@@ -475,13 +448,6 @@ long nvgpu_ioctl_tsg_dev_ioctl(struct file *filp, unsigned int cmd, | |||
475 | break; | 448 | break; |
476 | } | 449 | } |
477 | 450 | ||
478 | case NVGPU_IOCTL_TSG_SET_PRIORITY: | ||
479 | { | ||
480 | err = gk20a_tsg_ioctl_set_priority(g, tsg, | ||
481 | (struct nvgpu_set_priority_args *)buf); | ||
482 | break; | ||
483 | } | ||
484 | |||
485 | case NVGPU_IOCTL_TSG_EVENT_ID_CTRL: | 451 | case NVGPU_IOCTL_TSG_EVENT_ID_CTRL: |
486 | { | 452 | { |
487 | err = gk20a_tsg_event_id_ctrl(g, tsg, | 453 | err = gk20a_tsg_event_id_ctrl(g, tsg, |
diff --git a/drivers/gpu/nvgpu/common/mm/mm.c b/drivers/gpu/nvgpu/common/mm/mm.c index 86dc46c5..db87c4c4 100644 --- a/drivers/gpu/nvgpu/common/mm/mm.c +++ b/drivers/gpu/nvgpu/common/mm/mm.c | |||
@@ -262,7 +262,6 @@ void nvgpu_init_mm_ce_context(struct gk20a *g) | |||
262 | gk20a_ce_create_context(g, | 262 | gk20a_ce_create_context(g, |
263 | gk20a_fifo_get_fast_ce_runlist_id(g), | 263 | gk20a_fifo_get_fast_ce_runlist_id(g), |
264 | -1, | 264 | -1, |
265 | -1, | ||
266 | -1); | 265 | -1); |
267 | 266 | ||
268 | if (g->mm.vidmem.ce_ctx_id == (u32)~0) | 267 | if (g->mm.vidmem.ce_ctx_id == (u32)~0) |
diff --git a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c index 04ee84f4..99c518b5 100644 --- a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c | |||
@@ -427,7 +427,6 @@ void gk20a_ce_suspend(struct gk20a *g) | |||
427 | /* CE app utility functions */ | 427 | /* CE app utility functions */ |
428 | u32 gk20a_ce_create_context(struct gk20a *g, | 428 | u32 gk20a_ce_create_context(struct gk20a *g, |
429 | int runlist_id, | 429 | int runlist_id, |
430 | int priority, | ||
431 | int timeslice, | 430 | int timeslice, |
432 | int runlist_level) | 431 | int runlist_level) |
433 | { | 432 | { |
@@ -507,16 +506,6 @@ u32 gk20a_ce_create_context(struct gk20a *g, | |||
507 | 506 | ||
508 | memset(ce_ctx->cmd_buf_mem.cpu_va, 0x00, ce_ctx->cmd_buf_mem.size); | 507 | memset(ce_ctx->cmd_buf_mem.cpu_va, 0x00, ce_ctx->cmd_buf_mem.size); |
509 | 508 | ||
510 | /* -1 means default channel priority */ | ||
511 | if (priority != -1) { | ||
512 | err = gk20a_fifo_set_priority(ce_ctx->ch, priority); | ||
513 | if (err) { | ||
514 | nvgpu_err(g, | ||
515 | "ce: could not set the channel priority for CE context"); | ||
516 | goto end; | ||
517 | } | ||
518 | } | ||
519 | |||
520 | /* -1 means default channel timeslice value */ | 509 | /* -1 means default channel timeslice value */ |
521 | if (timeslice != -1) { | 510 | if (timeslice != -1) { |
522 | err = gk20a_fifo_set_timeslice(ce_ctx->ch, timeslice); | 511 | err = gk20a_fifo_set_timeslice(ce_ctx->ch, timeslice); |
diff --git a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.h b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.h index 5c3a1cfc..1d9d8c72 100644 --- a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.h | |||
@@ -128,7 +128,6 @@ void gk20a_ce_destroy(struct gk20a *g); | |||
128 | /* CE app utility functions */ | 128 | /* CE app utility functions */ |
129 | u32 gk20a_ce_create_context(struct gk20a *g, | 129 | u32 gk20a_ce_create_context(struct gk20a *g, |
130 | int runlist_id, | 130 | int runlist_id, |
131 | int priority, | ||
132 | int timeslice, | 131 | int timeslice, |
133 | int runlist_level); | 132 | int runlist_level); |
134 | int gk20a_ce_execute_ops(struct gk20a *g, | 133 | int gk20a_ce_execute_ops(struct gk20a *g, |
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index 1ea7d6b3..648a8c86 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | |||
@@ -3962,32 +3962,6 @@ int gk20a_fifo_set_timeslice(struct channel_gk20a *ch, u32 timeslice) | |||
3962 | return channel_gk20a_set_schedule_params(ch); | 3962 | return channel_gk20a_set_schedule_params(ch); |
3963 | } | 3963 | } |
3964 | 3964 | ||
3965 | int gk20a_fifo_set_priority(struct channel_gk20a *ch, u32 priority) | ||
3966 | { | ||
3967 | if (gk20a_is_channel_marked_as_tsg(ch)) { | ||
3968 | nvgpu_err(ch->g, "invalid operation for TSG!"); | ||
3969 | return -EINVAL; | ||
3970 | } | ||
3971 | |||
3972 | /* set priority of graphics channel */ | ||
3973 | switch (priority) { | ||
3974 | case NVGPU_PRIORITY_LOW: | ||
3975 | ch->timeslice_us = ch->g->timeslice_low_priority_us; | ||
3976 | break; | ||
3977 | case NVGPU_PRIORITY_MEDIUM: | ||
3978 | ch->timeslice_us = ch->g->timeslice_medium_priority_us; | ||
3979 | break; | ||
3980 | case NVGPU_PRIORITY_HIGH: | ||
3981 | ch->timeslice_us = ch->g->timeslice_high_priority_us; | ||
3982 | break; | ||
3983 | default: | ||
3984 | pr_err("Unsupported priority"); | ||
3985 | return -EINVAL; | ||
3986 | } | ||
3987 | |||
3988 | return channel_gk20a_set_schedule_params(ch); | ||
3989 | } | ||
3990 | |||
3991 | void gk20a_fifo_setup_ramfc_for_privileged_channel(struct channel_gk20a *c) | 3965 | void gk20a_fifo_setup_ramfc_for_privileged_channel(struct channel_gk20a *c) |
3992 | { | 3966 | { |
3993 | struct gk20a *g = c->g; | 3967 | struct gk20a *g = c->g; |
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h index fa1d9f72..3587ffa8 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h | |||
@@ -383,7 +383,6 @@ void __locked_fifo_preempt_timeout_rc(struct gk20a *g, u32 id, | |||
383 | int gk20a_fifo_setup_ramfc(struct channel_gk20a *c, | 383 | int gk20a_fifo_setup_ramfc(struct channel_gk20a *c, |
384 | u64 gpfifo_base, u32 gpfifo_entries, | 384 | u64 gpfifo_base, u32 gpfifo_entries, |
385 | unsigned long timeout, u32 flags); | 385 | unsigned long timeout, u32 flags); |
386 | int gk20a_fifo_set_priority(struct channel_gk20a *ch, u32 priority); | ||
387 | int gk20a_fifo_set_timeslice(struct channel_gk20a *ch, unsigned int timeslice); | 386 | int gk20a_fifo_set_timeslice(struct channel_gk20a *ch, unsigned int timeslice); |
388 | void gk20a_fifo_setup_ramfc_for_privileged_channel(struct channel_gk20a *c); | 387 | void gk20a_fifo_setup_ramfc_for_privileged_channel(struct channel_gk20a *c); |
389 | int gk20a_fifo_alloc_inst(struct gk20a *g, struct channel_gk20a *ch); | 388 | int gk20a_fifo_alloc_inst(struct gk20a *g, struct channel_gk20a *ch); |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index fb12d0d2..3381d974 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -513,7 +513,6 @@ struct gpu_ops { | |||
513 | int (*wait_engine_idle)(struct gk20a *g); | 513 | int (*wait_engine_idle)(struct gk20a *g); |
514 | u32 (*get_num_fifos)(struct gk20a *g); | 514 | u32 (*get_num_fifos)(struct gk20a *g); |
515 | u32 (*get_pbdma_signature)(struct gk20a *g); | 515 | u32 (*get_pbdma_signature)(struct gk20a *g); |
516 | int (*channel_set_priority)(struct channel_gk20a *ch, u32 priority); | ||
517 | int (*set_runlist_interleave)(struct gk20a *g, u32 id, | 516 | int (*set_runlist_interleave)(struct gk20a *g, u32 id, |
518 | bool is_tsg, u32 runlist_id, | 517 | bool is_tsg, u32 runlist_id, |
519 | u32 new_level); | 518 | u32 new_level); |
diff --git a/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c b/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c index 5af01a05..636ee8a0 100644 --- a/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c | |||
@@ -200,29 +200,6 @@ int gk20a_init_tsg_support(struct gk20a *g, u32 tsgid) | |||
200 | return 0; | 200 | return 0; |
201 | } | 201 | } |
202 | 202 | ||
203 | int gk20a_tsg_set_priority(struct gk20a *g, struct tsg_gk20a *tsg, | ||
204 | u32 priority) | ||
205 | { | ||
206 | u32 timeslice_us; | ||
207 | |||
208 | switch (priority) { | ||
209 | case NVGPU_PRIORITY_LOW: | ||
210 | timeslice_us = g->timeslice_low_priority_us; | ||
211 | break; | ||
212 | case NVGPU_PRIORITY_MEDIUM: | ||
213 | timeslice_us = g->timeslice_medium_priority_us; | ||
214 | break; | ||
215 | case NVGPU_PRIORITY_HIGH: | ||
216 | timeslice_us = g->timeslice_high_priority_us; | ||
217 | break; | ||
218 | default: | ||
219 | pr_err("Unsupported priority"); | ||
220 | return -EINVAL; | ||
221 | } | ||
222 | |||
223 | return gk20a_tsg_set_timeslice(tsg, timeslice_us); | ||
224 | } | ||
225 | |||
226 | int gk20a_tsg_set_runlist_interleave(struct tsg_gk20a *tsg, u32 level) | 203 | int gk20a_tsg_set_runlist_interleave(struct tsg_gk20a *tsg, u32 level) |
227 | { | 204 | { |
228 | struct gk20a *g = tsg->g; | 205 | struct gk20a *g = tsg->g; |
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index 42df76c9..227b6b6c 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c | |||
@@ -385,7 +385,6 @@ static const struct gpu_ops gm20b_ops = { | |||
385 | .alloc_inst = gk20a_fifo_alloc_inst, | 385 | .alloc_inst = gk20a_fifo_alloc_inst, |
386 | .free_inst = gk20a_fifo_free_inst, | 386 | .free_inst = gk20a_fifo_free_inst, |
387 | .setup_ramfc = gk20a_fifo_setup_ramfc, | 387 | .setup_ramfc = gk20a_fifo_setup_ramfc, |
388 | .channel_set_priority = gk20a_fifo_set_priority, | ||
389 | .channel_set_timeslice = gk20a_fifo_set_timeslice, | 388 | .channel_set_timeslice = gk20a_fifo_set_timeslice, |
390 | .default_timeslice_us = gk20a_fifo_default_timeslice_us, | 389 | .default_timeslice_us = gk20a_fifo_default_timeslice_us, |
391 | .setup_userd = gk20a_fifo_setup_userd, | 390 | .setup_userd = gk20a_fifo_setup_userd, |
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c index 09c82af8..e9ee77fc 100644 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c | |||
@@ -440,7 +440,6 @@ static const struct gpu_ops gp106_ops = { | |||
440 | .alloc_inst = gk20a_fifo_alloc_inst, | 440 | .alloc_inst = gk20a_fifo_alloc_inst, |
441 | .free_inst = gk20a_fifo_free_inst, | 441 | .free_inst = gk20a_fifo_free_inst, |
442 | .setup_ramfc = channel_gp10b_setup_ramfc, | 442 | .setup_ramfc = channel_gp10b_setup_ramfc, |
443 | .channel_set_priority = gk20a_fifo_set_priority, | ||
444 | .channel_set_timeslice = gk20a_fifo_set_timeslice, | 443 | .channel_set_timeslice = gk20a_fifo_set_timeslice, |
445 | .default_timeslice_us = gk20a_fifo_default_timeslice_us, | 444 | .default_timeslice_us = gk20a_fifo_default_timeslice_us, |
446 | .setup_userd = gk20a_fifo_setup_userd, | 445 | .setup_userd = gk20a_fifo_setup_userd, |
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index d0aedd1b..9b3d1a2c 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c | |||
@@ -408,7 +408,6 @@ static const struct gpu_ops gp10b_ops = { | |||
408 | .alloc_inst = gk20a_fifo_alloc_inst, | 408 | .alloc_inst = gk20a_fifo_alloc_inst, |
409 | .free_inst = gk20a_fifo_free_inst, | 409 | .free_inst = gk20a_fifo_free_inst, |
410 | .setup_ramfc = channel_gp10b_setup_ramfc, | 410 | .setup_ramfc = channel_gp10b_setup_ramfc, |
411 | .channel_set_priority = gk20a_fifo_set_priority, | ||
412 | .channel_set_timeslice = gk20a_fifo_set_timeslice, | 411 | .channel_set_timeslice = gk20a_fifo_set_timeslice, |
413 | .default_timeslice_us = gk20a_fifo_default_timeslice_us, | 412 | .default_timeslice_us = gk20a_fifo_default_timeslice_us, |
414 | .setup_userd = gk20a_fifo_setup_userd, | 413 | .setup_userd = gk20a_fifo_setup_userd, |
diff --git a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c index fa9388f2..66b2dbef 100644 --- a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c | |||
@@ -607,25 +607,6 @@ int vgpu_fifo_wait_engine_idle(struct gk20a *g) | |||
607 | return 0; | 607 | return 0; |
608 | } | 608 | } |
609 | 609 | ||
610 | int vgpu_channel_set_priority(struct channel_gk20a *ch, u32 priority) | ||
611 | { | ||
612 | struct tegra_vgpu_cmd_msg msg; | ||
613 | struct tegra_vgpu_channel_priority_params *p = | ||
614 | &msg.params.channel_priority; | ||
615 | int err; | ||
616 | |||
617 | gk20a_dbg_info("channel %d set priority %u", ch->chid, priority); | ||
618 | |||
619 | msg.cmd = TEGRA_VGPU_CMD_CHANNEL_SET_PRIORITY; | ||
620 | msg.handle = vgpu_get_handle(ch->g); | ||
621 | p->handle = ch->virt_ctx; | ||
622 | p->priority = priority; | ||
623 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
624 | WARN_ON(err || msg.ret); | ||
625 | |||
626 | return err ? err : msg.ret; | ||
627 | } | ||
628 | |||
629 | static int vgpu_fifo_tsg_set_runlist_interleave(struct gk20a *g, | 610 | static int vgpu_fifo_tsg_set_runlist_interleave(struct gk20a *g, |
630 | u32 tsgid, | 611 | u32 tsgid, |
631 | u32 runlist_id, | 612 | u32 runlist_id, |
diff --git a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.h b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.h index aa95cc41..7633ad95 100644 --- a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.h +++ b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.h | |||
@@ -46,7 +46,6 @@ int vgpu_fifo_preempt_tsg(struct gk20a *g, u32 tsgid); | |||
46 | int vgpu_fifo_update_runlist(struct gk20a *g, u32 runlist_id, | 46 | int vgpu_fifo_update_runlist(struct gk20a *g, u32 runlist_id, |
47 | u32 chid, bool add, bool wait_for_finish); | 47 | u32 chid, bool add, bool wait_for_finish); |
48 | int vgpu_fifo_wait_engine_idle(struct gk20a *g); | 48 | int vgpu_fifo_wait_engine_idle(struct gk20a *g); |
49 | int vgpu_channel_set_priority(struct channel_gk20a *ch, u32 priority); | ||
50 | int vgpu_fifo_set_runlist_interleave(struct gk20a *g, | 49 | int vgpu_fifo_set_runlist_interleave(struct gk20a *g, |
51 | u32 id, | 50 | u32 id, |
52 | bool is_tsg, | 51 | bool is_tsg, |
diff --git a/drivers/gpu/nvgpu/vgpu/gm20b/vgpu_hal_gm20b.c b/drivers/gpu/nvgpu/vgpu/gm20b/vgpu_hal_gm20b.c index 37a34950..a3eb59ac 100644 --- a/drivers/gpu/nvgpu/vgpu/gm20b/vgpu_hal_gm20b.c +++ b/drivers/gpu/nvgpu/vgpu/gm20b/vgpu_hal_gm20b.c | |||
@@ -264,7 +264,6 @@ static const struct gpu_ops vgpu_gm20b_ops = { | |||
264 | .alloc_inst = vgpu_channel_alloc_inst, | 264 | .alloc_inst = vgpu_channel_alloc_inst, |
265 | .free_inst = vgpu_channel_free_inst, | 265 | .free_inst = vgpu_channel_free_inst, |
266 | .setup_ramfc = vgpu_channel_setup_ramfc, | 266 | .setup_ramfc = vgpu_channel_setup_ramfc, |
267 | .channel_set_priority = vgpu_channel_set_priority, | ||
268 | .channel_set_timeslice = vgpu_channel_set_timeslice, | 267 | .channel_set_timeslice = vgpu_channel_set_timeslice, |
269 | .default_timeslice_us = vgpu_fifo_default_timeslice_us, | 268 | .default_timeslice_us = vgpu_fifo_default_timeslice_us, |
270 | .setup_userd = gk20a_fifo_setup_userd, | 269 | .setup_userd = gk20a_fifo_setup_userd, |
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c index 693709ef..55448f3b 100644 --- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c | |||
@@ -289,7 +289,6 @@ static const struct gpu_ops vgpu_gp10b_ops = { | |||
289 | .alloc_inst = vgpu_channel_alloc_inst, | 289 | .alloc_inst = vgpu_channel_alloc_inst, |
290 | .free_inst = vgpu_channel_free_inst, | 290 | .free_inst = vgpu_channel_free_inst, |
291 | .setup_ramfc = vgpu_channel_setup_ramfc, | 291 | .setup_ramfc = vgpu_channel_setup_ramfc, |
292 | .channel_set_priority = vgpu_channel_set_priority, | ||
293 | .channel_set_timeslice = vgpu_channel_set_timeslice, | 292 | .channel_set_timeslice = vgpu_channel_set_timeslice, |
294 | .default_timeslice_us = vgpu_fifo_default_timeslice_us, | 293 | .default_timeslice_us = vgpu_fifo_default_timeslice_us, |
295 | .setup_userd = gk20a_fifo_setup_userd, | 294 | .setup_userd = gk20a_fifo_setup_userd, |