diff options
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hw_top_gp10b.h | 8 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/mc_gp10b.c | 20 |
2 files changed, 20 insertions, 8 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/hw_top_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_top_gp10b.h index ca6457c7..0982bc09 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_top_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_top_gp10b.h | |||
@@ -102,6 +102,14 @@ static inline u32 top_device_info_runlist_enum_v(u32 r) | |||
102 | { | 102 | { |
103 | return (r >> 21) & 0xf; | 103 | return (r >> 21) & 0xf; |
104 | } | 104 | } |
105 | static inline u32 top_device_info_intr_enum_v(u32 r) | ||
106 | { | ||
107 | return (r >> 15) & 0x1f; | ||
108 | } | ||
109 | static inline u32 top_device_info_reset_enum_v(u32 r) | ||
110 | { | ||
111 | return (r >> 9) & 0x1f; | ||
112 | } | ||
105 | static inline u32 top_device_info_type_enum_v(u32 r) | 113 | static inline u32 top_device_info_type_enum_v(u32 r) |
106 | { | 114 | { |
107 | return (r >> 2) & 0x1fffffff; | 115 | return (r >> 2) & 0x1fffffff; |
diff --git a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c index 4f7ab698..3fae4ea3 100644 --- a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c | |||
@@ -21,17 +21,19 @@ | |||
21 | 21 | ||
22 | void mc_gp10b_intr_enable(struct gk20a *g) | 22 | void mc_gp10b_intr_enable(struct gk20a *g) |
23 | { | 23 | { |
24 | u32 eng_intr_mask = gk20a_fifo_engine_interrupt_mask(g); | ||
25 | |||
24 | gk20a_writel(g, mc_intr_en_clear_r(0), 0xffffffff); | 26 | gk20a_writel(g, mc_intr_en_clear_r(0), 0xffffffff); |
25 | gk20a_writel(g, mc_intr_en_set_r(0), | 27 | gk20a_writel(g, mc_intr_en_set_r(0), |
26 | mc_intr_pfifo_pending_f() | 28 | mc_intr_pfifo_pending_f() |
27 | | mc_intr_pgraph_pending_f()); | 29 | | eng_intr_mask); |
28 | gk20a_writel(g, mc_intr_en_clear_r(1), 0xffffffff); | 30 | gk20a_writel(g, mc_intr_en_clear_r(1), 0xffffffff); |
29 | gk20a_writel(g, mc_intr_en_set_r(1), | 31 | gk20a_writel(g, mc_intr_en_set_r(1), |
30 | mc_intr_pfifo_pending_f() | 32 | mc_intr_pfifo_pending_f() |
31 | | mc_intr_pgraph_pending_f() | ||
32 | | mc_intr_priv_ring_pending_f() | 33 | | mc_intr_priv_ring_pending_f() |
33 | | mc_intr_ltc_pending_f() | 34 | | mc_intr_ltc_pending_f() |
34 | | mc_intr_pbus_pending_f()); | 35 | | mc_intr_pbus_pending_f() |
36 | | eng_intr_mask); | ||
35 | } | 37 | } |
36 | 38 | ||
37 | irqreturn_t mc_gp10b_isr_stall(struct gk20a *g) | 39 | irqreturn_t mc_gp10b_isr_stall(struct gk20a *g) |
@@ -71,6 +73,7 @@ irqreturn_t mc_gp10b_isr_nonstall(struct gk20a *g) | |||
71 | irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g) | 73 | irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g) |
72 | { | 74 | { |
73 | u32 mc_intr_0; | 75 | u32 mc_intr_0; |
76 | u32 eng_intr_mask = gk20a_fifo_engine_interrupt_mask(g); | ||
74 | 77 | ||
75 | gk20a_dbg(gpu_dbg_intr, "interrupt thread launched"); | 78 | gk20a_dbg(gpu_dbg_intr, "interrupt thread launched"); |
76 | 79 | ||
@@ -78,7 +81,7 @@ irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g) | |||
78 | 81 | ||
79 | gk20a_dbg(gpu_dbg_intr, "stall intr %08x\n", mc_intr_0); | 82 | gk20a_dbg(gpu_dbg_intr, "stall intr %08x\n", mc_intr_0); |
80 | 83 | ||
81 | if (mc_intr_0 & mc_intr_pgraph_pending_f()) | 84 | if (mc_intr_0 & BIT(g->fifo.engine_info[ENGINE_GR_GK20A].intr_id)) |
82 | gr_gk20a_elpg_protected_call(g, gk20a_gr_isr(g)); | 85 | gr_gk20a_elpg_protected_call(g, gk20a_gr_isr(g)); |
83 | if (mc_intr_0 & mc_intr_pfifo_pending_f()) | 86 | if (mc_intr_0 & mc_intr_pfifo_pending_f()) |
84 | gk20a_fifo_isr(g); | 87 | gk20a_fifo_isr(g); |
@@ -93,7 +96,7 @@ irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g) | |||
93 | 96 | ||
94 | gk20a_writel(g, mc_intr_en_set_r(0), | 97 | gk20a_writel(g, mc_intr_en_set_r(0), |
95 | mc_intr_pfifo_pending_f() | 98 | mc_intr_pfifo_pending_f() |
96 | | mc_intr_pgraph_pending_f()); | 99 | | eng_intr_mask); |
97 | 100 | ||
98 | return IRQ_HANDLED; | 101 | return IRQ_HANDLED; |
99 | } | 102 | } |
@@ -101,6 +104,7 @@ irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g) | |||
101 | irqreturn_t mc_gp10b_intr_thread_nonstall(struct gk20a *g) | 104 | irqreturn_t mc_gp10b_intr_thread_nonstall(struct gk20a *g) |
102 | { | 105 | { |
103 | u32 mc_intr_1; | 106 | u32 mc_intr_1; |
107 | u32 eng_intr_mask = gk20a_fifo_engine_interrupt_mask(g); | ||
104 | 108 | ||
105 | gk20a_dbg(gpu_dbg_intr, "interrupt thread launched"); | 109 | gk20a_dbg(gpu_dbg_intr, "interrupt thread launched"); |
106 | 110 | ||
@@ -110,15 +114,15 @@ irqreturn_t mc_gp10b_intr_thread_nonstall(struct gk20a *g) | |||
110 | 114 | ||
111 | if (mc_intr_1 & mc_intr_pfifo_pending_f()) | 115 | if (mc_intr_1 & mc_intr_pfifo_pending_f()) |
112 | gk20a_fifo_nonstall_isr(g); | 116 | gk20a_fifo_nonstall_isr(g); |
113 | if (mc_intr_1 & mc_intr_pgraph_pending_f()) | 117 | if (mc_intr_1 & BIT(g->fifo.engine_info[ENGINE_GR_GK20A].intr_id)) |
114 | gk20a_gr_nonstall_isr(g); | 118 | gk20a_gr_nonstall_isr(g); |
115 | 119 | ||
116 | gk20a_writel(g, mc_intr_en_set_r(1), | 120 | gk20a_writel(g, mc_intr_en_set_r(1), |
117 | mc_intr_pfifo_pending_f() | 121 | mc_intr_pfifo_pending_f() |
118 | | mc_intr_pgraph_pending_f() | ||
119 | | mc_intr_priv_ring_pending_f() | 122 | | mc_intr_priv_ring_pending_f() |
120 | | mc_intr_ltc_pending_f() | 123 | | mc_intr_ltc_pending_f() |
121 | | mc_intr_pbus_pending_f()); | 124 | | mc_intr_pbus_pending_f() |
125 | | eng_intr_mask); | ||
122 | 126 | ||
123 | return IRQ_HANDLED; | 127 | return IRQ_HANDLED; |
124 | } | 128 | } |