diff options
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/hw_ctxsw_prog_gk20a.h | 8 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h | 72 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hw_ctxsw_prog_gm20b.h | 8 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h | 72 |
4 files changed, 152 insertions, 8 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/hw_ctxsw_prog_gk20a.h b/drivers/gpu/nvgpu/gk20a/hw_ctxsw_prog_gk20a.h index 08834557..81293403 100644 --- a/drivers/gpu/nvgpu/gk20a/hw_ctxsw_prog_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/hw_ctxsw_prog_gk20a.h | |||
@@ -62,6 +62,10 @@ static inline u32 ctxsw_prog_main_image_patch_count_o(void) | |||
62 | { | 62 | { |
63 | return 0x00000010; | 63 | return 0x00000010; |
64 | } | 64 | } |
65 | static inline u32 ctxsw_prog_main_image_context_id_o(void) | ||
66 | { | ||
67 | return 0x000000f0; | ||
68 | } | ||
65 | static inline u32 ctxsw_prog_main_image_patch_adr_lo_o(void) | 69 | static inline u32 ctxsw_prog_main_image_patch_adr_lo_o(void) |
66 | { | 70 | { |
67 | return 0x00000014; | 71 | return 0x00000014; |
@@ -246,10 +250,6 @@ static inline u32 ctxsw_prog_main_image_misc_options_verif_features_disabled_f(v | |||
246 | { | 250 | { |
247 | return 0x0; | 251 | return 0x0; |
248 | } | 252 | } |
249 | static inline u32 ctxsw_prog_main_image_context_id_o(void) | ||
250 | { | ||
251 | return 0x000000f0; | ||
252 | } | ||
253 | static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_control_o(void) | 253 | static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_control_o(void) |
254 | { | 254 | { |
255 | return 0x000000ac; | 255 | return 0x000000ac; |
diff --git a/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h index ab2a975b..11cbe10c 100644 --- a/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h | |||
@@ -938,10 +938,22 @@ static inline u32 gr_fecs_host_int_status_umimp_illegal_method_f(u32 v) | |||
938 | { | 938 | { |
939 | return (v & 0x1) << 18; | 939 | return (v & 0x1) << 18; |
940 | } | 940 | } |
941 | static inline u32 gr_fecs_host_int_status_ctxsw_intr_f(u32 v) | ||
942 | { | ||
943 | return (v & 0xffff) << 0; | ||
944 | } | ||
941 | static inline u32 gr_fecs_host_int_clear_r(void) | 945 | static inline u32 gr_fecs_host_int_clear_r(void) |
942 | { | 946 | { |
943 | return 0x00409c20; | 947 | return 0x00409c20; |
944 | } | 948 | } |
949 | static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_f(u32 v) | ||
950 | { | ||
951 | return (v & 0x1) << 1; | ||
952 | } | ||
953 | static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_clear_f(void) | ||
954 | { | ||
955 | return 0x2; | ||
956 | } | ||
945 | static inline u32 gr_fecs_host_int_enable_r(void) | 957 | static inline u32 gr_fecs_host_int_enable_r(void) |
946 | { | 958 | { |
947 | return 0x00409c24; | 959 | return 0x00409c24; |
@@ -3102,6 +3114,14 @@ static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_disable_f(void) | |||
3102 | { | 3114 | { |
3103 | return 0x0; | 3115 | return 0x0; |
3104 | } | 3116 | } |
3117 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_single_step_mode_enable_f(void) | ||
3118 | { | ||
3119 | return 0x8; | ||
3120 | } | ||
3121 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_single_step_mode_disable_f(void) | ||
3122 | { | ||
3123 | return 0x0; | ||
3124 | } | ||
3105 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_run_trigger_task_f(void) | 3125 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_run_trigger_task_f(void) |
3106 | { | 3126 | { |
3107 | return 0x40000000; | 3127 | return 0x40000000; |
@@ -3186,6 +3206,26 @@ static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_single_step_complete_pending_f( | |||
3186 | { | 3206 | { |
3187 | return 0x40; | 3207 | return 0x40; |
3188 | } | 3208 | } |
3209 | static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_sm_to_sm_fault_pending_f(void) | ||
3210 | { | ||
3211 | return 0x1; | ||
3212 | } | ||
3213 | static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_l1_error_pending_f(void) | ||
3214 | { | ||
3215 | return 0x2; | ||
3216 | } | ||
3217 | static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_multiple_warp_errors_pending_f(void) | ||
3218 | { | ||
3219 | return 0x4; | ||
3220 | } | ||
3221 | static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_physical_stack_overflow_error_pending_f(void) | ||
3222 | { | ||
3223 | return 0x8; | ||
3224 | } | ||
3225 | static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_timeout_error_pending_f(void) | ||
3226 | { | ||
3227 | return 0x80000000; | ||
3228 | } | ||
3189 | static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_r(void) | 3229 | static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_r(void) |
3190 | { | 3230 | { |
3191 | return 0x00504650; | 3231 | return 0x00504650; |
@@ -3202,6 +3242,26 @@ static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f( | |||
3202 | { | 3242 | { |
3203 | return 0x40; | 3243 | return 0x40; |
3204 | } | 3244 | } |
3245 | static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_sm_to_sm_fault_pending_f(void) | ||
3246 | { | ||
3247 | return 0x1; | ||
3248 | } | ||
3249 | static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_l1_error_pending_f(void) | ||
3250 | { | ||
3251 | return 0x2; | ||
3252 | } | ||
3253 | static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_multiple_warp_errors_pending_f(void) | ||
3254 | { | ||
3255 | return 0x4; | ||
3256 | } | ||
3257 | static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_physical_stack_overflow_error_pending_f(void) | ||
3258 | { | ||
3259 | return 0x8; | ||
3260 | } | ||
3261 | static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_timeout_error_pending_f(void) | ||
3262 | { | ||
3263 | return 0x80000000; | ||
3264 | } | ||
3205 | static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_r(void) | 3265 | static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_r(void) |
3206 | { | 3266 | { |
3207 | return 0x00504224; | 3267 | return 0x00504224; |
@@ -3618,6 +3678,18 @@ static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_disable_f(void) | |||
3618 | { | 3678 | { |
3619 | return 0x0; | 3679 | return 0x0; |
3620 | } | 3680 | } |
3681 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_m(void) | ||
3682 | { | ||
3683 | return 0x1 << 3; | ||
3684 | } | ||
3685 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_enable_f(void) | ||
3686 | { | ||
3687 | return 0x8; | ||
3688 | } | ||
3689 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_disable_f(void) | ||
3690 | { | ||
3691 | return 0x0; | ||
3692 | } | ||
3621 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_m(void) | 3693 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_m(void) |
3622 | { | 3694 | { |
3623 | return 0x1 << 30; | 3695 | return 0x1 << 30; |
diff --git a/drivers/gpu/nvgpu/gm20b/hw_ctxsw_prog_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_ctxsw_prog_gm20b.h index c9bf4b4f..535b6c6e 100644 --- a/drivers/gpu/nvgpu/gm20b/hw_ctxsw_prog_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/hw_ctxsw_prog_gm20b.h | |||
@@ -74,6 +74,10 @@ static inline u32 ctxsw_prog_main_image_patch_count_o(void) | |||
74 | { | 74 | { |
75 | return 0x00000010; | 75 | return 0x00000010; |
76 | } | 76 | } |
77 | static inline u32 ctxsw_prog_main_image_context_id_o(void) | ||
78 | { | ||
79 | return 0x000000f0; | ||
80 | } | ||
77 | static inline u32 ctxsw_prog_main_image_patch_adr_lo_o(void) | 81 | static inline u32 ctxsw_prog_main_image_patch_adr_lo_o(void) |
78 | { | 82 | { |
79 | return 0x00000014; | 83 | return 0x00000014; |
@@ -458,8 +462,4 @@ static inline u32 ctxsw_prog_main_image_preemption_options_control_cta_enabled_f | |||
458 | { | 462 | { |
459 | return 0x1; | 463 | return 0x1; |
460 | } | 464 | } |
461 | static inline u32 ctxsw_prog_main_image_context_id_o(void) | ||
462 | { | ||
463 | return 0x000000f0; | ||
464 | } | ||
465 | #endif | 465 | #endif |
diff --git a/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h index b796e2d3..73861c07 100644 --- a/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h | |||
@@ -954,10 +954,22 @@ static inline u32 gr_fecs_host_int_status_umimp_illegal_method_f(u32 v) | |||
954 | { | 954 | { |
955 | return (v & 0x1) << 18; | 955 | return (v & 0x1) << 18; |
956 | } | 956 | } |
957 | static inline u32 gr_fecs_host_int_status_ctxsw_intr_f(u32 v) | ||
958 | { | ||
959 | return (v & 0xffff) << 0; | ||
960 | } | ||
957 | static inline u32 gr_fecs_host_int_clear_r(void) | 961 | static inline u32 gr_fecs_host_int_clear_r(void) |
958 | { | 962 | { |
959 | return 0x00409c20; | 963 | return 0x00409c20; |
960 | } | 964 | } |
965 | static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_f(u32 v) | ||
966 | { | ||
967 | return (v & 0x1) << 1; | ||
968 | } | ||
969 | static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_clear_f(void) | ||
970 | { | ||
971 | return 0x2; | ||
972 | } | ||
961 | static inline u32 gr_fecs_host_int_enable_r(void) | 973 | static inline u32 gr_fecs_host_int_enable_r(void) |
962 | { | 974 | { |
963 | return 0x00409c24; | 975 | return 0x00409c24; |
@@ -3138,6 +3150,14 @@ static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_disable_f(void) | |||
3138 | { | 3150 | { |
3139 | return 0x0; | 3151 | return 0x0; |
3140 | } | 3152 | } |
3153 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_single_step_mode_enable_f(void) | ||
3154 | { | ||
3155 | return 0x8; | ||
3156 | } | ||
3157 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_single_step_mode_disable_f(void) | ||
3158 | { | ||
3159 | return 0x0; | ||
3160 | } | ||
3141 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_run_trigger_task_f(void) | 3161 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_run_trigger_task_f(void) |
3142 | { | 3162 | { |
3143 | return 0x40000000; | 3163 | return 0x40000000; |
@@ -3234,6 +3254,26 @@ static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_single_step_complete_pending_f( | |||
3234 | { | 3254 | { |
3235 | return 0x40; | 3255 | return 0x40; |
3236 | } | 3256 | } |
3257 | static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_sm_to_sm_fault_pending_f(void) | ||
3258 | { | ||
3259 | return 0x1; | ||
3260 | } | ||
3261 | static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_l1_error_pending_f(void) | ||
3262 | { | ||
3263 | return 0x2; | ||
3264 | } | ||
3265 | static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_multiple_warp_errors_pending_f(void) | ||
3266 | { | ||
3267 | return 0x4; | ||
3268 | } | ||
3269 | static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_physical_stack_overflow_error_pending_f(void) | ||
3270 | { | ||
3271 | return 0x8; | ||
3272 | } | ||
3273 | static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_timeout_error_pending_f(void) | ||
3274 | { | ||
3275 | return 0x80000000; | ||
3276 | } | ||
3237 | static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_r(void) | 3277 | static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_r(void) |
3238 | { | 3278 | { |
3239 | return 0x00504650; | 3279 | return 0x00504650; |
@@ -3250,6 +3290,26 @@ static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f( | |||
3250 | { | 3290 | { |
3251 | return 0x40; | 3291 | return 0x40; |
3252 | } | 3292 | } |
3293 | static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_sm_to_sm_fault_pending_f(void) | ||
3294 | { | ||
3295 | return 0x1; | ||
3296 | } | ||
3297 | static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_l1_error_pending_f(void) | ||
3298 | { | ||
3299 | return 0x2; | ||
3300 | } | ||
3301 | static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_multiple_warp_errors_pending_f(void) | ||
3302 | { | ||
3303 | return 0x4; | ||
3304 | } | ||
3305 | static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_physical_stack_overflow_error_pending_f(void) | ||
3306 | { | ||
3307 | return 0x8; | ||
3308 | } | ||
3309 | static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_timeout_error_pending_f(void) | ||
3310 | { | ||
3311 | return 0x80000000; | ||
3312 | } | ||
3253 | static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_r(void) | 3313 | static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_r(void) |
3254 | { | 3314 | { |
3255 | return 0x00504224; | 3315 | return 0x00504224; |
@@ -3694,6 +3754,18 @@ static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_disable_f(void) | |||
3694 | { | 3754 | { |
3695 | return 0x0; | 3755 | return 0x0; |
3696 | } | 3756 | } |
3757 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_m(void) | ||
3758 | { | ||
3759 | return 0x1 << 3; | ||
3760 | } | ||
3761 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_enable_f(void) | ||
3762 | { | ||
3763 | return 0x8; | ||
3764 | } | ||
3765 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_disable_f(void) | ||
3766 | { | ||
3767 | return 0x0; | ||
3768 | } | ||
3697 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_m(void) | 3769 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_m(void) |
3698 | { | 3770 | { |
3699 | return 0x1 << 30; | 3771 | return 0x1 << 30; |