diff options
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/gp106/acr_gp106.c | 118 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/hal_gp106.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/hal_gv100.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/acr/acr_lsfm.h | 89 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/acr/acr_objlsfm.h | 14 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/enabled.h | 5 |
7 files changed, 223 insertions, 7 deletions
diff --git a/drivers/gpu/nvgpu/gp106/acr_gp106.c b/drivers/gpu/nvgpu/gp106/acr_gp106.c index 61b443e0..70296757 100644 --- a/drivers/gpu/nvgpu/gp106/acr_gp106.c +++ b/drivers/gpu/nvgpu/gp106/acr_gp106.c | |||
@@ -368,6 +368,50 @@ rel_sig: | |||
368 | return err; | 368 | return err; |
369 | } | 369 | } |
370 | 370 | ||
371 | /* | ||
372 | * Discover all supported shared data falcon SUB WPRs | ||
373 | */ | ||
374 | static u32 lsfm_discover_and_add_sub_wprs(struct gk20a *g, | ||
375 | struct ls_flcn_mgr_v1 *plsfm) | ||
376 | { | ||
377 | struct lsfm_sub_wpr *pnode; | ||
378 | u32 size_4K = 0; | ||
379 | u32 sub_wpr_index; | ||
380 | |||
381 | for (sub_wpr_index = 1; | ||
382 | sub_wpr_index <= LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_MAX; | ||
383 | sub_wpr_index++) { | ||
384 | |||
385 | switch (sub_wpr_index) { | ||
386 | case LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_FRTS_VBIOS_TABLES: | ||
387 | size_4K = LSF_SHARED_DATA_SUB_WPR_FRTS_VBIOS_TABLES_SIZE_IN_4K; | ||
388 | break; | ||
389 | case LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_PLAYREADY_SHARED_DATA: | ||
390 | size_4K = LSF_SHARED_DATA_SUB_WPR_PLAYREADY_SHARED_DATA_SIZE_IN_4K; | ||
391 | break; | ||
392 | default: | ||
393 | size_4K = 0; /* subWpr not supported */ | ||
394 | break; | ||
395 | } | ||
396 | |||
397 | if (size_4K) { | ||
398 | pnode = nvgpu_kzalloc(g, sizeof(struct lsfm_sub_wpr)); | ||
399 | if (pnode == NULL) | ||
400 | return -ENOMEM; | ||
401 | |||
402 | pnode->sub_wpr_header.use_case_id = sub_wpr_index; | ||
403 | pnode->sub_wpr_header.size_4K = size_4K; | ||
404 | |||
405 | pnode->pnext = plsfm->psub_wpr_list; | ||
406 | plsfm->psub_wpr_list = pnode; | ||
407 | |||
408 | plsfm->managed_sub_wpr_count++; | ||
409 | } | ||
410 | } | ||
411 | |||
412 | return 0; | ||
413 | } | ||
414 | |||
371 | int gp106_prepare_ucode_blob(struct gk20a *g) | 415 | int gp106_prepare_ucode_blob(struct gk20a *g) |
372 | { | 416 | { |
373 | 417 | ||
@@ -400,6 +444,9 @@ int gp106_prepare_ucode_blob(struct gk20a *g) | |||
400 | if (err) | 444 | if (err) |
401 | goto exit_err; | 445 | goto exit_err; |
402 | 446 | ||
447 | if (nvgpu_is_enabled(g, NVGPU_SUPPORT_MULTIPLE_WPR)) | ||
448 | lsfm_discover_and_add_sub_wprs(g, plsfm); | ||
449 | |||
403 | if (plsfm->managed_flcn_cnt && !g->acr.ucode_blob.cpu_va) { | 450 | if (plsfm->managed_flcn_cnt && !g->acr.ucode_blob.cpu_va) { |
404 | /* Generate WPR requirements*/ | 451 | /* Generate WPR requirements*/ |
405 | err = lsf_gen_wpr_requirements(g, plsfm); | 452 | err = lsf_gen_wpr_requirements(g, plsfm); |
@@ -671,6 +718,40 @@ int lsfm_fill_flcn_bl_gen_desc(struct gk20a *g, | |||
671 | return -ENOENT; | 718 | return -ENOENT; |
672 | } | 719 | } |
673 | 720 | ||
721 | static u32 lsfm_init_sub_wpr_contents(struct gk20a *g, | ||
722 | struct ls_flcn_mgr_v1 *plsfm, struct nvgpu_mem *ucode) | ||
723 | { | ||
724 | struct lsfm_sub_wpr *psub_wpr_node; | ||
725 | struct lsf_shared_sub_wpr_header last_sub_wpr_header; | ||
726 | u32 temp_size = sizeof(struct lsf_shared_sub_wpr_header); | ||
727 | u32 sub_wpr_header_offset = 0; | ||
728 | u32 i = 0; | ||
729 | |||
730 | /* SubWpr headers are placed after WPR headers */ | ||
731 | sub_wpr_header_offset = LSF_WPR_HEADERS_TOTAL_SIZE_MAX; | ||
732 | |||
733 | /* Walk through the managed shared subWPRs headers | ||
734 | * and flush them to FB | ||
735 | */ | ||
736 | psub_wpr_node = plsfm->psub_wpr_list; | ||
737 | i = 0; | ||
738 | while (psub_wpr_node) { | ||
739 | nvgpu_mem_wr_n(g, ucode, | ||
740 | sub_wpr_header_offset + (i * temp_size), | ||
741 | &psub_wpr_node->sub_wpr_header, temp_size); | ||
742 | |||
743 | psub_wpr_node = psub_wpr_node->pnext; | ||
744 | i++; | ||
745 | } | ||
746 | last_sub_wpr_header.use_case_id = | ||
747 | LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_INVALID; | ||
748 | nvgpu_mem_wr_n(g, ucode, sub_wpr_header_offset + | ||
749 | (plsfm->managed_sub_wpr_count * temp_size), | ||
750 | &last_sub_wpr_header, temp_size); | ||
751 | |||
752 | return 0; | ||
753 | } | ||
754 | |||
674 | /* Initialize WPR contents */ | 755 | /* Initialize WPR contents */ |
675 | void lsfm_init_wpr_contents(struct gk20a *g, | 756 | void lsfm_init_wpr_contents(struct gk20a *g, |
676 | struct ls_flcn_mgr_v1 *plsfm, struct nvgpu_mem *ucode) | 757 | struct ls_flcn_mgr_v1 *plsfm, struct nvgpu_mem *ucode) |
@@ -684,6 +765,9 @@ void lsfm_init_wpr_contents(struct gk20a *g, | |||
684 | memset(&last_wpr_hdr, 0, sizeof(struct lsf_wpr_header_v1)); | 765 | memset(&last_wpr_hdr, 0, sizeof(struct lsf_wpr_header_v1)); |
685 | i = 0; | 766 | i = 0; |
686 | 767 | ||
768 | if (nvgpu_is_enabled(g, NVGPU_SUPPORT_MULTIPLE_WPR)) | ||
769 | lsfm_init_sub_wpr_contents(g, plsfm, ucode); | ||
770 | |||
687 | /* | 771 | /* |
688 | * Walk the managed falcons, flush WPR and LSB headers to FB. | 772 | * Walk the managed falcons, flush WPR and LSB headers to FB. |
689 | * flush any bl args to the storage area relative to the | 773 | * flush any bl args to the storage area relative to the |
@@ -956,6 +1040,7 @@ int lsf_gen_wpr_requirements(struct gk20a *g, | |||
956 | struct ls_flcn_mgr_v1 *plsfm) | 1040 | struct ls_flcn_mgr_v1 *plsfm) |
957 | { | 1041 | { |
958 | struct lsfm_managed_ucode_img_v2 *pnode = plsfm->ucode_img_list; | 1042 | struct lsfm_managed_ucode_img_v2 *pnode = plsfm->ucode_img_list; |
1043 | struct lsfm_sub_wpr *pnode_sub_wpr = plsfm->psub_wpr_list; | ||
959 | u32 wpr_offset; | 1044 | u32 wpr_offset; |
960 | 1045 | ||
961 | /* Calculate WPR size required */ | 1046 | /* Calculate WPR size required */ |
@@ -967,6 +1052,22 @@ int lsf_gen_wpr_requirements(struct gk20a *g, | |||
967 | wpr_offset = sizeof(struct lsf_wpr_header_v1) * | 1052 | wpr_offset = sizeof(struct lsf_wpr_header_v1) * |
968 | (plsfm->managed_flcn_cnt+1); | 1053 | (plsfm->managed_flcn_cnt+1); |
969 | 1054 | ||
1055 | if (nvgpu_is_enabled(g, NVGPU_SUPPORT_MULTIPLE_WPR)) { | ||
1056 | wpr_offset = ALIGN_UP(wpr_offset, | ||
1057 | LSF_WPR_HEADERS_TOTAL_SIZE_MAX); | ||
1058 | /* | ||
1059 | * SUB WPR header is appended after | ||
1060 | * LSF_WPR_HEADER in WPR blob. | ||
1061 | * The size is allocated as per the managed | ||
1062 | * SUB WPR count. | ||
1063 | */ | ||
1064 | wpr_offset = ALIGN_UP(wpr_offset, | ||
1065 | LSF_SUB_WPR_HEADER_ALIGNMENT); | ||
1066 | wpr_offset = wpr_offset + | ||
1067 | (sizeof(struct lsf_shared_sub_wpr_header) * | ||
1068 | (plsfm->managed_sub_wpr_count + 1)); | ||
1069 | } | ||
1070 | |||
970 | /* Walk the managed falcons, accounting for the LSB structs | 1071 | /* Walk the managed falcons, accounting for the LSB structs |
971 | as well as the ucode images. */ | 1072 | as well as the ucode images. */ |
972 | while (pnode) { | 1073 | while (pnode) { |
@@ -1028,6 +1129,23 @@ int lsf_gen_wpr_requirements(struct gk20a *g, | |||
1028 | } | 1129 | } |
1029 | pnode = pnode->next; | 1130 | pnode = pnode->next; |
1030 | } | 1131 | } |
1132 | |||
1133 | if (nvgpu_is_enabled(g, NVGPU_SUPPORT_MULTIPLE_WPR)) { | ||
1134 | /* Walk through the sub wpr headers to accommodate | ||
1135 | * sub wprs in WPR request | ||
1136 | */ | ||
1137 | while (pnode_sub_wpr) { | ||
1138 | wpr_offset = ALIGN_UP(wpr_offset, | ||
1139 | SUB_WPR_SIZE_ALIGNMENT); | ||
1140 | pnode_sub_wpr->sub_wpr_header.start_addr = wpr_offset; | ||
1141 | wpr_offset = wpr_offset + | ||
1142 | (pnode_sub_wpr->sub_wpr_header.size_4K | ||
1143 | << SHIFT_4KB); | ||
1144 | pnode_sub_wpr = pnode_sub_wpr->pnext; | ||
1145 | } | ||
1146 | wpr_offset = ALIGN_UP(wpr_offset, SUB_WPR_SIZE_ALIGNMENT); | ||
1147 | } | ||
1148 | |||
1031 | plsfm->wpr_size = wpr_offset; | 1149 | plsfm->wpr_size = wpr_offset; |
1032 | return 0; | 1150 | return 0; |
1033 | } | 1151 | } |
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c index 67a7968a..a525d117 100644 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c | |||
@@ -830,6 +830,7 @@ int gp106_init_hal(struct gk20a *g) | |||
830 | __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true); | 830 | __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true); |
831 | __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, true); | 831 | __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, true); |
832 | __nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false); | 832 | __nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false); |
833 | __nvgpu_set_enabled(g, NVGPU_SUPPORT_MULTIPLE_WPR, false); | ||
833 | 834 | ||
834 | /* Read fuses to check if gpu needs to boot in secure/non-secure mode */ | 835 | /* Read fuses to check if gpu needs to boot in secure/non-secure mode */ |
835 | if (gops->fuse.check_priv_security(g)) | 836 | if (gops->fuse.check_priv_security(g)) |
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 56429975..2f5cf7f3 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c | |||
@@ -911,6 +911,7 @@ int gv100_init_hal(struct gk20a *g) | |||
911 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); | 911 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); |
912 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true); | 912 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true); |
913 | __nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false); | 913 | __nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false); |
914 | __nvgpu_set_enabled(g, NVGPU_SUPPORT_MULTIPLE_WPR, false); | ||
914 | /* for now */ | 915 | /* for now */ |
915 | __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false); | 916 | __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false); |
916 | 917 | ||
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 58912a30..cae55609 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c | |||
@@ -841,6 +841,8 @@ int gv11b_init_hal(struct gk20a *g) | |||
841 | __nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false); | 841 | __nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false); |
842 | g->bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT; | 842 | g->bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT; |
843 | 843 | ||
844 | __nvgpu_set_enabled(g, NVGPU_SUPPORT_MULTIPLE_WPR, false); | ||
845 | |||
844 | g->name = "gv11b"; | 846 | g->name = "gv11b"; |
845 | 847 | ||
846 | return 0; | 848 | return 0; |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/acr/acr_lsfm.h b/drivers/gpu/nvgpu/include/nvgpu/acr/acr_lsfm.h index 70184934..90d2d20d 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/acr/acr_lsfm.h +++ b/drivers/gpu/nvgpu/include/nvgpu/acr/acr_lsfm.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -28,6 +28,22 @@ | |||
28 | #endif | 28 | #endif |
29 | 29 | ||
30 | /* | 30 | /* |
31 | * READ/WRITE masks for WPR region | ||
32 | */ | ||
33 | /* Readable only from level 2 and 3 client */ | ||
34 | #define LSF_WPR_REGION_RMASK (0xC) | ||
35 | /* Writable only from level 2 and 3 client */ | ||
36 | #define LSF_WPR_REGION_WMASK (0xC) | ||
37 | /* Readable only from level 3 client */ | ||
38 | #define LSF_WPR_REGION_RMASK_SUB_WPR_ENABLED (0x8) | ||
39 | /* Writable only from level 3 client */ | ||
40 | #define LSF_WPR_REGION_WMASK_SUB_WPR_ENABLED (0x8) | ||
41 | /* Disallow read mis-match for all clients */ | ||
42 | #define LSF_WPR_REGION_ALLOW_READ_MISMATCH_NO (0x0) | ||
43 | /* Disallow write mis-match for all clients */ | ||
44 | #define LSF_WPR_REGION_ALLOW_WRITE_MISMATCH_NO (0x0) | ||
45 | |||
46 | /* | ||
31 | * Falcon Id Defines | 47 | * Falcon Id Defines |
32 | * Defines a common Light Secure Falcon identifier. | 48 | * Defines a common Light Secure Falcon identifier. |
33 | */ | 49 | */ |
@@ -84,6 +100,42 @@ struct lsf_wpr_header_v1 { | |||
84 | u32 bin_version; | 100 | u32 bin_version; |
85 | u32 status; | 101 | u32 status; |
86 | }; | 102 | }; |
103 | |||
104 | |||
105 | /* | ||
106 | * LSF shared SubWpr Header | ||
107 | * | ||
108 | * use_case_id - Shared SubWpr use case ID (updated by nvgpu) | ||
109 | * start_addr - start address of subWpr (updated by nvgpu) | ||
110 | * size_4K - size of subWpr in 4K (updated by nvgpu) | ||
111 | */ | ||
112 | struct lsf_shared_sub_wpr_header { | ||
113 | u32 use_case_id; | ||
114 | u32 start_addr; | ||
115 | u32 size_4K; | ||
116 | }; | ||
117 | |||
118 | /* shared sub_wpr use case IDs */ | ||
119 | enum { | ||
120 | LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_FRTS_VBIOS_TABLES = 1, | ||
121 | LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_PLAYREADY_SHARED_DATA = 2 | ||
122 | }; | ||
123 | |||
124 | #define LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_MAX \ | ||
125 | LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_PLAYREADY_SHARED_DATA | ||
126 | |||
127 | #define LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_INVALID (0xFFFFFFFF) | ||
128 | |||
129 | #define MAX_SUPPORTED_SHARED_SUB_WPR_USE_CASES \ | ||
130 | LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_MAX | ||
131 | |||
132 | /* Static sizes of shared subWPRs */ | ||
133 | /* Minimum granularity supported is 4K */ | ||
134 | /* 1MB in 4K */ | ||
135 | #define LSF_SHARED_DATA_SUB_WPR_FRTS_VBIOS_TABLES_SIZE_IN_4K (0x100) | ||
136 | /* 4K */ | ||
137 | #define LSF_SHARED_DATA_SUB_WPR_PLAYREADY_SHARED_DATA_SIZE_IN_4K (0x1) | ||
138 | |||
87 | /* | 139 | /* |
88 | * Bootstrap Owner Defines | 140 | * Bootstrap Owner Defines |
89 | */ | 141 | */ |
@@ -147,13 +199,40 @@ struct lsf_lsb_header_v1 { | |||
147 | /* | 199 | /* |
148 | * Light Secure WPR Content Alignments | 200 | * Light Secure WPR Content Alignments |
149 | */ | 201 | */ |
150 | #define LSF_LSB_HEADER_ALIGNMENT 256 | 202 | #define LSF_WPR_HEADER_ALIGNMENT (256U) |
151 | #define LSF_BL_DATA_ALIGNMENT 256 | 203 | #define LSF_SUB_WPR_HEADER_ALIGNMENT (256U) |
152 | #define LSF_BL_DATA_SIZE_ALIGNMENT 256 | 204 | #define LSF_LSB_HEADER_ALIGNMENT (256U) |
153 | #define LSF_BL_CODE_SIZE_ALIGNMENT 256 | 205 | #define LSF_BL_DATA_ALIGNMENT (256U) |
206 | #define LSF_BL_DATA_SIZE_ALIGNMENT (256U) | ||
207 | #define LSF_BL_CODE_SIZE_ALIGNMENT (256U) | ||
208 | #define LSF_DATA_SIZE_ALIGNMENT (256U) | ||
209 | #define LSF_CODE_SIZE_ALIGNMENT (256U) | ||
210 | |||
211 | /* MMU excepts sub_wpr sizes in units of 4K */ | ||
212 | #define SUB_WPR_SIZE_ALIGNMENT (4096U) | ||
213 | |||
214 | /* | ||
215 | * Maximum WPR Header size | ||
216 | */ | ||
217 | #define LSF_WPR_HEADERS_TOTAL_SIZE_MAX \ | ||
218 | (ALIGN_UP((sizeof(struct lsf_wpr_header_v1) * LSF_FALCON_ID_END), \ | ||
219 | LSF_WPR_HEADER_ALIGNMENT)) | ||
220 | #define LSF_LSB_HEADER_TOTAL_SIZE_MAX (\ | ||
221 | ALIGN_UP(sizeof(struct lsf_lsb_header_v1), LSF_LSB_HEADER_ALIGNMENT)) | ||
222 | |||
223 | /* Maximum SUB WPR header size */ | ||
224 | #define LSF_SUB_WPR_HEADERS_TOTAL_SIZE_MAX (ALIGN_UP( \ | ||
225 | (sizeof(struct lsf_shared_sub_wpr_header) * \ | ||
226 | LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_MAX), \ | ||
227 | LSF_SUB_WPR_HEADER_ALIGNMENT)) | ||
228 | |||
154 | 229 | ||
155 | #define LSF_UCODE_DATA_ALIGNMENT 4096 | 230 | #define LSF_UCODE_DATA_ALIGNMENT 4096 |
156 | 231 | ||
232 | /* Defined for 1MB alignment */ | ||
233 | #define SHIFT_1MB (20) | ||
234 | #define SHIFT_4KB (12) | ||
235 | |||
157 | /* | 236 | /* |
158 | * Supporting maximum of 2 regions. | 237 | * Supporting maximum of 2 regions. |
159 | * This is needed to pre-allocate space in DMEM | 238 | * This is needed to pre-allocate space in DMEM |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/acr/acr_objlsfm.h b/drivers/gpu/nvgpu/include/nvgpu/acr/acr_objlsfm.h index cde8707a..96fb9f19 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/acr/acr_objlsfm.h +++ b/drivers/gpu/nvgpu/include/nvgpu/acr/acr_objlsfm.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -73,12 +73,24 @@ struct ls_flcn_mgr { | |||
73 | void *wpr_client_req_state;/*PACR_CLIENT_REQUEST_STATE originally*/ | 73 | void *wpr_client_req_state;/*PACR_CLIENT_REQUEST_STATE originally*/ |
74 | }; | 74 | }; |
75 | 75 | ||
76 | /* | ||
77 | * LSFM SUB WPRs struct | ||
78 | * pnext : Next entry in the list, NULL if last | ||
79 | * sub_wpr_header : SubWpr Header struct | ||
80 | */ | ||
81 | struct lsfm_sub_wpr { | ||
82 | struct lsfm_sub_wpr *pnext; | ||
83 | struct lsf_shared_sub_wpr_header sub_wpr_header; | ||
84 | }; | ||
85 | |||
76 | struct ls_flcn_mgr_v1 { | 86 | struct ls_flcn_mgr_v1 { |
77 | u16 managed_flcn_cnt; | 87 | u16 managed_flcn_cnt; |
78 | u32 wpr_size; | 88 | u32 wpr_size; |
79 | u32 disable_mask; | 89 | u32 disable_mask; |
80 | struct lsfm_managed_ucode_img_v2 *ucode_img_list; | 90 | struct lsfm_managed_ucode_img_v2 *ucode_img_list; |
81 | void *wpr_client_req_state;/*PACR_CLIENT_REQUEST_STATE originally*/ | 91 | void *wpr_client_req_state;/*PACR_CLIENT_REQUEST_STATE originally*/ |
92 | u16 managed_sub_wpr_count; | ||
93 | struct lsfm_sub_wpr *psub_wpr_list; | ||
82 | }; | 94 | }; |
83 | 95 | ||
84 | 96 | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/enabled.h b/drivers/gpu/nvgpu/include/nvgpu/enabled.h index a76db09e..0ffb0488 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/enabled.h +++ b/drivers/gpu/nvgpu/include/nvgpu/enabled.h | |||
@@ -163,10 +163,13 @@ struct gk20a; | |||
163 | /* USERMODE enable bit */ | 163 | /* USERMODE enable bit */ |
164 | #define NVGPU_SUPPORT_USERMODE_SUBMIT 67 | 164 | #define NVGPU_SUPPORT_USERMODE_SUBMIT 67 |
165 | 165 | ||
166 | /* Multiple WPR support */ | ||
167 | #define NVGPU_SUPPORT_MULTIPLE_WPR 68 | ||
168 | |||
166 | /* | 169 | /* |
167 | * Must be greater than the largest bit offset in the above list. | 170 | * Must be greater than the largest bit offset in the above list. |
168 | */ | 171 | */ |
169 | #define NVGPU_MAX_ENABLED_BITS 68 | 172 | #define NVGPU_MAX_ENABLED_BITS 69 |
170 | 173 | ||
171 | /** | 174 | /** |
172 | * nvgpu_is_enabled - Check if the passed flag is enabled. | 175 | * nvgpu_is_enabled - Check if the passed flag is enabled. |