diff options
Diffstat (limited to 'drivers/gpu/nvgpu')
24 files changed, 409 insertions, 287 deletions
diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index 9da20802..c7ccefb5 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile | |||
@@ -42,7 +42,10 @@ nvgpu-y += common/bus/bus_gk20a.o \ | |||
42 | common/therm/therm_gm20b.o \ | 42 | common/therm/therm_gm20b.o \ |
43 | common/therm/therm_gp10b.o \ | 43 | common/therm/therm_gp10b.o \ |
44 | common/therm/therm_gp106.o \ | 44 | common/therm/therm_gp106.o \ |
45 | common/therm/therm_gv11b.o | 45 | common/therm/therm_gv11b.o \ |
46 | common/fuse/fuse_gm20b.o \ | ||
47 | common/fuse/fuse_gp10b.o \ | ||
48 | common/fuse/fuse_gp106.o | ||
46 | 49 | ||
47 | # Linux specific parts of nvgpu. | 50 | # Linux specific parts of nvgpu. |
48 | nvgpu-y += \ | 51 | nvgpu-y += \ |
@@ -227,7 +230,6 @@ nvgpu-y += \ | |||
227 | gm20b/pmu_gm20b.o \ | 230 | gm20b/pmu_gm20b.o \ |
228 | gm20b/mm_gm20b.o \ | 231 | gm20b/mm_gm20b.o \ |
229 | gm20b/regops_gm20b.o \ | 232 | gm20b/regops_gm20b.o \ |
230 | gm20b/fuse_gm20b.o \ | ||
231 | boardobj/boardobj.o \ | 233 | boardobj/boardobj.o \ |
232 | boardobj/boardobjgrp.o \ | 234 | boardobj/boardobjgrp.o \ |
233 | boardobj/boardobjgrpmask.o \ | 235 | boardobj/boardobjgrpmask.o \ |
@@ -275,7 +277,6 @@ nvgpu-y += \ | |||
275 | gp10b/regops_gp10b.o \ | 277 | gp10b/regops_gp10b.o \ |
276 | gp10b/fecs_trace_gp10b.o \ | 278 | gp10b/fecs_trace_gp10b.o \ |
277 | gp10b/gp10b.o \ | 279 | gp10b/gp10b.o \ |
278 | gp10b/fuse_gp10b.o \ | ||
279 | gp10b/ecc_gp10b.o \ | 280 | gp10b/ecc_gp10b.o \ |
280 | gp106/hal_gp106.o \ | 281 | gp106/hal_gp106.o \ |
281 | gp106/mm_gp106.o \ | 282 | gp106/mm_gp106.o \ |
@@ -289,7 +290,6 @@ nvgpu-y += \ | |||
289 | gp106/fifo_gp106.o \ | 290 | gp106/fifo_gp106.o \ |
290 | gp106/regops_gp106.o \ | 291 | gp106/regops_gp106.o \ |
291 | gp106/bios_gp106.o \ | 292 | gp106/bios_gp106.o \ |
292 | gp106/fuse_gp106.o \ | ||
293 | gv11b/gv11b.o \ | 293 | gv11b/gv11b.o \ |
294 | gv11b/css_gr_gv11b.o \ | 294 | gv11b/css_gr_gv11b.o \ |
295 | gv11b/dbg_gpu_gv11b.o \ | 295 | gv11b/dbg_gpu_gv11b.o \ |
diff --git a/drivers/gpu/nvgpu/Makefile.sources b/drivers/gpu/nvgpu/Makefile.sources index 7c6e7f7f..503e0f3a 100644 --- a/drivers/gpu/nvgpu/Makefile.sources +++ b/drivers/gpu/nvgpu/Makefile.sources | |||
@@ -74,6 +74,9 @@ srcs := os/posix/nvgpu.c \ | |||
74 | common/therm/therm_gp10b.c \ | 74 | common/therm/therm_gp10b.c \ |
75 | common/therm/therm_gv11b.c \ | 75 | common/therm/therm_gv11b.c \ |
76 | common/therm/therm_gp106.c \ | 76 | common/therm/therm_gp106.c \ |
77 | common/fuse/fuse_gm20b.c \ | ||
78 | common/fuse/fuse_gp10b.c \ | ||
79 | common/fuse/fuse_gp106.c \ | ||
77 | common/enabled.c \ | 80 | common/enabled.c \ |
78 | common/pramin.c \ | 81 | common/pramin.c \ |
79 | common/semaphore.c \ | 82 | common/semaphore.c \ |
@@ -160,7 +163,6 @@ srcs := os/posix/nvgpu.c \ | |||
160 | gm20b/pmu_gm20b.c \ | 163 | gm20b/pmu_gm20b.c \ |
161 | gm20b/mm_gm20b.c \ | 164 | gm20b/mm_gm20b.c \ |
162 | gm20b/regops_gm20b.c \ | 165 | gm20b/regops_gm20b.c \ |
163 | gm20b/fuse_gm20b.c \ | ||
164 | gp10b/gr_gp10b.c \ | 166 | gp10b/gr_gp10b.c \ |
165 | gp10b/gr_ctx_gp10b.c \ | 167 | gp10b/gr_ctx_gp10b.c \ |
166 | gp10b/ce_gp10b.c \ | 168 | gp10b/ce_gp10b.c \ |
@@ -172,7 +174,6 @@ srcs := os/posix/nvgpu.c \ | |||
172 | gp10b/regops_gp10b.c \ | 174 | gp10b/regops_gp10b.c \ |
173 | gp10b/fecs_trace_gp10b.c \ | 175 | gp10b/fecs_trace_gp10b.c \ |
174 | gp10b/gp10b.c \ | 176 | gp10b/gp10b.c \ |
175 | gp10b/fuse_gp10b.c \ | ||
176 | gp10b/ecc_gp10b.c \ | 177 | gp10b/ecc_gp10b.c \ |
177 | gv11b/gv11b.c \ | 178 | gv11b/gv11b.c \ |
178 | gv11b/dbg_gpu_gv11b.c \ | 179 | gv11b/dbg_gpu_gv11b.c \ |
@@ -200,7 +201,6 @@ srcs := os/posix/nvgpu.c \ | |||
200 | gp106/fifo_gp106.c \ | 201 | gp106/fifo_gp106.c \ |
201 | gp106/regops_gp106.c \ | 202 | gp106/regops_gp106.c \ |
202 | gp106/bios_gp106.c \ | 203 | gp106/bios_gp106.c \ |
203 | gp106/fuse_gp106.c \ | ||
204 | gp106/clk_gp106.c \ | 204 | gp106/clk_gp106.c \ |
205 | gp106/clk_arb_gp106.c \ | 205 | gp106/clk_arb_gp106.c \ |
206 | gv100/mm_gv100.c \ | 206 | gv100/mm_gv100.c \ |
diff --git a/drivers/gpu/nvgpu/clk/clk_vin.c b/drivers/gpu/nvgpu/clk/clk_vin.c index 4e6fbe50..67eeffd5 100644 --- a/drivers/gpu/nvgpu/clk/clk_vin.c +++ b/drivers/gpu/nvgpu/clk/clk_vin.c | |||
@@ -36,8 +36,6 @@ | |||
36 | #include "clk.h" | 36 | #include "clk.h" |
37 | #include "clk_vin.h" | 37 | #include "clk_vin.h" |
38 | 38 | ||
39 | #include <nvgpu/hw/gp106/hw_fuse_gp106.h> | ||
40 | |||
41 | static u32 devinit_get_vin_device_table(struct gk20a *g, | 39 | static u32 devinit_get_vin_device_table(struct gk20a *g, |
42 | struct avfsvinobjs *pvinobjs); | 40 | struct avfsvinobjs *pvinobjs); |
43 | 41 | ||
@@ -62,196 +60,6 @@ static u32 vin_device_init_pmudata_super(struct gk20a *g, | |||
62 | struct boardobj *board_obj_ptr, | 60 | struct boardobj *board_obj_ptr, |
63 | struct nv_pmu_boardobj *ppmudata); | 61 | struct nv_pmu_boardobj *ppmudata); |
64 | 62 | ||
65 | static u32 read_vin_cal_fuse_rev(struct gk20a *g) | ||
66 | { | ||
67 | return fuse_vin_cal_fuse_rev_data_v( | ||
68 | gk20a_readl(g, fuse_vin_cal_fuse_rev_r())); | ||
69 | } | ||
70 | |||
71 | static u32 read_vin_cal_slope_intercept_fuse(struct gk20a *g, | ||
72 | u32 vin_id, u32 *slope, | ||
73 | u32 *intercept) | ||
74 | { | ||
75 | u32 data = 0; | ||
76 | u32 interceptdata = 0; | ||
77 | u32 slopedata = 0; | ||
78 | u32 gpc0data; | ||
79 | u32 gpc0slopedata; | ||
80 | u32 gpc0interceptdata; | ||
81 | |||
82 | /* read gpc0 irrespective of vin id */ | ||
83 | gpc0data = gk20a_readl(g, fuse_vin_cal_gpc0_r()); | ||
84 | if (gpc0data == 0xFFFFFFFF) | ||
85 | return -EINVAL; | ||
86 | |||
87 | switch (vin_id) { | ||
88 | case CTRL_CLK_VIN_ID_GPC0: | ||
89 | break; | ||
90 | |||
91 | case CTRL_CLK_VIN_ID_GPC1: | ||
92 | data = gk20a_readl(g, fuse_vin_cal_gpc1_delta_r()); | ||
93 | break; | ||
94 | |||
95 | case CTRL_CLK_VIN_ID_GPC2: | ||
96 | data = gk20a_readl(g, fuse_vin_cal_gpc2_delta_r()); | ||
97 | break; | ||
98 | |||
99 | case CTRL_CLK_VIN_ID_GPC3: | ||
100 | data = gk20a_readl(g, fuse_vin_cal_gpc3_delta_r()); | ||
101 | break; | ||
102 | |||
103 | case CTRL_CLK_VIN_ID_GPC4: | ||
104 | data = gk20a_readl(g, fuse_vin_cal_gpc4_delta_r()); | ||
105 | break; | ||
106 | |||
107 | case CTRL_CLK_VIN_ID_GPC5: | ||
108 | data = gk20a_readl(g, fuse_vin_cal_gpc5_delta_r()); | ||
109 | break; | ||
110 | |||
111 | case CTRL_CLK_VIN_ID_SYS: | ||
112 | case CTRL_CLK_VIN_ID_XBAR: | ||
113 | case CTRL_CLK_VIN_ID_LTC: | ||
114 | data = gk20a_readl(g, fuse_vin_cal_shared_delta_r()); | ||
115 | break; | ||
116 | |||
117 | case CTRL_CLK_VIN_ID_SRAM: | ||
118 | data = gk20a_readl(g, fuse_vin_cal_sram_delta_r()); | ||
119 | break; | ||
120 | |||
121 | default: | ||
122 | return -EINVAL; | ||
123 | } | ||
124 | if (data == 0xFFFFFFFF) | ||
125 | return -EINVAL; | ||
126 | |||
127 | gpc0interceptdata = (fuse_vin_cal_gpc0_icpt_int_data_v(gpc0data) << | ||
128 | fuse_vin_cal_gpc0_icpt_frac_data_s()) + | ||
129 | fuse_vin_cal_gpc0_icpt_frac_data_v(gpc0data); | ||
130 | gpc0interceptdata = (gpc0interceptdata * 1000U) >> | ||
131 | fuse_vin_cal_gpc0_icpt_frac_data_s(); | ||
132 | |||
133 | switch (vin_id) { | ||
134 | case CTRL_CLK_VIN_ID_GPC0: | ||
135 | break; | ||
136 | |||
137 | case CTRL_CLK_VIN_ID_GPC1: | ||
138 | case CTRL_CLK_VIN_ID_GPC2: | ||
139 | case CTRL_CLK_VIN_ID_GPC3: | ||
140 | case CTRL_CLK_VIN_ID_GPC4: | ||
141 | case CTRL_CLK_VIN_ID_GPC5: | ||
142 | case CTRL_CLK_VIN_ID_SYS: | ||
143 | case CTRL_CLK_VIN_ID_XBAR: | ||
144 | case CTRL_CLK_VIN_ID_LTC: | ||
145 | interceptdata = (fuse_vin_cal_gpc1_delta_icpt_int_data_v(data) << | ||
146 | fuse_vin_cal_gpc1_delta_icpt_frac_data_s()) + | ||
147 | fuse_vin_cal_gpc1_delta_icpt_frac_data_v(data); | ||
148 | interceptdata = (interceptdata * 1000U) >> | ||
149 | fuse_vin_cal_gpc1_delta_icpt_frac_data_s(); | ||
150 | break; | ||
151 | |||
152 | case CTRL_CLK_VIN_ID_SRAM: | ||
153 | interceptdata = (fuse_vin_cal_sram_delta_icpt_int_data_v(data) << | ||
154 | fuse_vin_cal_sram_delta_icpt_frac_data_s()) + | ||
155 | fuse_vin_cal_sram_delta_icpt_frac_data_v(data); | ||
156 | interceptdata = (interceptdata * 1000U) >> | ||
157 | fuse_vin_cal_sram_delta_icpt_frac_data_s(); | ||
158 | break; | ||
159 | |||
160 | default: | ||
161 | return -EINVAL; | ||
162 | } | ||
163 | |||
164 | if (fuse_vin_cal_gpc1_delta_icpt_sign_data_v(data)) | ||
165 | *intercept = gpc0interceptdata - interceptdata; | ||
166 | else | ||
167 | *intercept = gpc0interceptdata + interceptdata; | ||
168 | |||
169 | /* slope */ | ||
170 | gpc0slopedata = (fuse_vin_cal_gpc0_slope_int_data_v(gpc0data) << | ||
171 | fuse_vin_cal_gpc0_slope_frac_data_s()) + | ||
172 | fuse_vin_cal_gpc0_slope_frac_data_v(gpc0data); | ||
173 | gpc0slopedata = (gpc0slopedata * 1000U) >> | ||
174 | fuse_vin_cal_gpc0_slope_frac_data_s(); | ||
175 | switch (vin_id) { | ||
176 | case CTRL_CLK_VIN_ID_GPC0: | ||
177 | break; | ||
178 | |||
179 | case CTRL_CLK_VIN_ID_GPC1: | ||
180 | case CTRL_CLK_VIN_ID_GPC2: | ||
181 | case CTRL_CLK_VIN_ID_GPC3: | ||
182 | case CTRL_CLK_VIN_ID_GPC4: | ||
183 | case CTRL_CLK_VIN_ID_GPC5: | ||
184 | case CTRL_CLK_VIN_ID_SYS: | ||
185 | case CTRL_CLK_VIN_ID_XBAR: | ||
186 | case CTRL_CLK_VIN_ID_LTC: | ||
187 | case CTRL_CLK_VIN_ID_SRAM: | ||
188 | slopedata = | ||
189 | (fuse_vin_cal_gpc1_delta_slope_int_data_v(data)) * 1000; | ||
190 | break; | ||
191 | |||
192 | default: | ||
193 | return -EINVAL; | ||
194 | } | ||
195 | |||
196 | if (fuse_vin_cal_gpc1_delta_slope_sign_data_v(data)) | ||
197 | *slope = gpc0slopedata - slopedata; | ||
198 | else | ||
199 | *slope = gpc0slopedata + slopedata; | ||
200 | return 0; | ||
201 | } | ||
202 | |||
203 | static u32 read_vin_cal_gain_offset_fuse(struct gk20a *g, | ||
204 | u32 vin_id, s8 *gain, | ||
205 | s8 *offset) | ||
206 | { | ||
207 | u32 data = 0; | ||
208 | |||
209 | switch (vin_id) { | ||
210 | case CTRL_CLK_VIN_ID_GPC0: | ||
211 | data = gk20a_readl(g, fuse_vin_cal_gpc0_r()); | ||
212 | break; | ||
213 | |||
214 | case CTRL_CLK_VIN_ID_GPC1: | ||
215 | data = gk20a_readl(g, fuse_vin_cal_gpc1_delta_r()); | ||
216 | break; | ||
217 | |||
218 | case CTRL_CLK_VIN_ID_GPC2: | ||
219 | data = gk20a_readl(g, fuse_vin_cal_gpc2_delta_r()); | ||
220 | break; | ||
221 | |||
222 | case CTRL_CLK_VIN_ID_GPC3: | ||
223 | data = gk20a_readl(g, fuse_vin_cal_gpc3_delta_r()); | ||
224 | break; | ||
225 | |||
226 | case CTRL_CLK_VIN_ID_GPC4: | ||
227 | data = gk20a_readl(g, fuse_vin_cal_gpc4_delta_r()); | ||
228 | break; | ||
229 | |||
230 | case CTRL_CLK_VIN_ID_GPC5: | ||
231 | data = gk20a_readl(g, fuse_vin_cal_gpc5_delta_r()); | ||
232 | break; | ||
233 | |||
234 | case CTRL_CLK_VIN_ID_SYS: | ||
235 | case CTRL_CLK_VIN_ID_XBAR: | ||
236 | case CTRL_CLK_VIN_ID_LTC: | ||
237 | data = gk20a_readl(g, fuse_vin_cal_shared_delta_r()); | ||
238 | break; | ||
239 | |||
240 | case CTRL_CLK_VIN_ID_SRAM: | ||
241 | data = gk20a_readl(g, fuse_vin_cal_sram_delta_r()); | ||
242 | break; | ||
243 | |||
244 | default: | ||
245 | return -EINVAL; | ||
246 | } | ||
247 | if (data == 0xFFFFFFFF) | ||
248 | return -EINVAL; | ||
249 | *gain = (s8) (data >> 16) & 0x1f; | ||
250 | *offset = (s8) data & 0x7f; | ||
251 | |||
252 | return 0; | ||
253 | } | ||
254 | |||
255 | u32 clk_avfs_get_vin_cal_fuse_v10(struct gk20a *g, | 63 | u32 clk_avfs_get_vin_cal_fuse_v10(struct gk20a *g, |
256 | struct avfsvinobjs *pvinobjs, | 64 | struct avfsvinobjs *pvinobjs, |
257 | struct vin_device_v20 *pvindev) | 65 | struct vin_device_v20 *pvindev) |
@@ -260,13 +68,13 @@ u32 clk_avfs_get_vin_cal_fuse_v10(struct gk20a *g, | |||
260 | u32 slope, intercept; | 68 | u32 slope, intercept; |
261 | u8 i; | 69 | u8 i; |
262 | 70 | ||
263 | if (pvinobjs->calibration_rev_vbios == read_vin_cal_fuse_rev(g)) { | 71 | if (pvinobjs->calibration_rev_vbios == g->ops.fuse.read_vin_cal_fuse_rev(g)) { |
264 | BOARDOBJGRP_FOR_EACH(&(pvinobjs->super.super), | 72 | BOARDOBJGRP_FOR_EACH(&(pvinobjs->super.super), |
265 | struct vin_device_v20 *, pvindev, i) { | 73 | struct vin_device_v20 *, pvindev, i) { |
266 | slope = 0; | 74 | slope = 0; |
267 | intercept = 0; | 75 | intercept = 0; |
268 | pvindev = (struct vin_device_v20 *)CLK_GET_VIN_DEVICE(pvinobjs, i); | 76 | pvindev = (struct vin_device_v20 *)CLK_GET_VIN_DEVICE(pvinobjs, i); |
269 | status = read_vin_cal_slope_intercept_fuse(g, | 77 | status = g->ops.fuse.read_vin_cal_slope_intercept_fuse(g, |
270 | pvindev->super.id, &slope, &intercept); | 78 | pvindev->super.id, &slope, &intercept); |
271 | if (status) { | 79 | if (status) { |
272 | nvgpu_err(g, | 80 | nvgpu_err(g, |
@@ -291,13 +99,13 @@ u32 clk_avfs_get_vin_cal_fuse_v20(struct gk20a *g, | |||
291 | s8 gain, offset; | 99 | s8 gain, offset; |
292 | u8 i; | 100 | u8 i; |
293 | 101 | ||
294 | if (pvinobjs->calibration_rev_vbios == read_vin_cal_fuse_rev(g)) { | 102 | if (pvinobjs->calibration_rev_vbios == g->ops.fuse.read_vin_cal_fuse_rev(g)) { |
295 | BOARDOBJGRP_FOR_EACH(&(pvinobjs->super.super), | 103 | BOARDOBJGRP_FOR_EACH(&(pvinobjs->super.super), |
296 | struct vin_device_v20 *, pvindev, i) { | 104 | struct vin_device_v20 *, pvindev, i) { |
297 | gain = 0; | 105 | gain = 0; |
298 | offset = 0; | 106 | offset = 0; |
299 | pvindev = (struct vin_device_v20 *)CLK_GET_VIN_DEVICE(pvinobjs, i); | 107 | pvindev = (struct vin_device_v20 *)CLK_GET_VIN_DEVICE(pvinobjs, i); |
300 | status = read_vin_cal_gain_offset_fuse(g, | 108 | status = g->ops.fuse.read_vin_cal_gain_offset_fuse(g, |
301 | pvindev->super.id, &gain, &offset); | 109 | pvindev->super.id, &gain, &offset); |
302 | if (status) { | 110 | if (status) { |
303 | nvgpu_err(g, | 111 | nvgpu_err(g, |
diff --git a/drivers/gpu/nvgpu/gm20b/fuse_gm20b.c b/drivers/gpu/nvgpu/common/fuse/fuse_gm20b.c index 95ac8ee3..c790e297 100644 --- a/drivers/gpu/nvgpu/gm20b/fuse_gm20b.c +++ b/drivers/gpu/nvgpu/common/fuse/fuse_gm20b.c | |||
@@ -89,3 +89,38 @@ int gm20b_fuse_check_priv_security(struct gk20a *g) | |||
89 | 89 | ||
90 | return 0; | 90 | return 0; |
91 | } | 91 | } |
92 | |||
93 | u32 gm20b_fuse_status_opt_fbio(struct gk20a *g) | ||
94 | { | ||
95 | return nvgpu_readl(g, fuse_status_opt_fbio_r()); | ||
96 | } | ||
97 | |||
98 | u32 gm20b_fuse_status_opt_fbp(struct gk20a *g) | ||
99 | { | ||
100 | return nvgpu_readl(g, fuse_status_opt_fbp_r()); | ||
101 | } | ||
102 | |||
103 | u32 gm20b_fuse_status_opt_rop_l2_fbp(struct gk20a *g, u32 fbp) | ||
104 | { | ||
105 | return nvgpu_readl(g, fuse_status_opt_rop_l2_fbp_r(fbp)); | ||
106 | } | ||
107 | |||
108 | u32 gm20b_fuse_status_opt_tpc_gpc(struct gk20a *g, u32 gpc) | ||
109 | { | ||
110 | return nvgpu_readl(g, fuse_status_opt_tpc_gpc_r(gpc)); | ||
111 | } | ||
112 | |||
113 | void gm20b_fuse_ctrl_opt_tpc_gpc(struct gk20a *g, u32 gpc, u32 val) | ||
114 | { | ||
115 | nvgpu_writel(g, fuse_ctrl_opt_tpc_gpc_r(gpc), val); | ||
116 | } | ||
117 | |||
118 | u32 gm20b_fuse_opt_sec_debug_en(struct gk20a *g) | ||
119 | { | ||
120 | return nvgpu_readl(g, fuse_opt_sec_debug_en_r()); | ||
121 | } | ||
122 | |||
123 | u32 gm20b_fuse_opt_priv_sec_en(struct gk20a *g) | ||
124 | { | ||
125 | return gk20a_readl(g, fuse_opt_priv_sec_en_r()); | ||
126 | } | ||
diff --git a/drivers/gpu/nvgpu/gm20b/fuse_gm20b.h b/drivers/gpu/nvgpu/common/fuse/fuse_gm20b.h index 51734b2f..5e2d194b 100644 --- a/drivers/gpu/nvgpu/gm20b/fuse_gm20b.h +++ b/drivers/gpu/nvgpu/common/fuse/fuse_gm20b.h | |||
@@ -33,5 +33,12 @@ | |||
33 | struct gk20a; | 33 | struct gk20a; |
34 | 34 | ||
35 | int gm20b_fuse_check_priv_security(struct gk20a *g); | 35 | int gm20b_fuse_check_priv_security(struct gk20a *g); |
36 | u32 gm20b_fuse_status_opt_fbio(struct gk20a *g); | ||
37 | u32 gm20b_fuse_status_opt_fbp(struct gk20a *g); | ||
38 | u32 gm20b_fuse_status_opt_rop_l2_fbp(struct gk20a *g, u32 fbp); | ||
39 | u32 gm20b_fuse_status_opt_tpc_gpc(struct gk20a *g, u32 gpc); | ||
40 | void gm20b_fuse_ctrl_opt_tpc_gpc(struct gk20a *g, u32 gpc, u32 val); | ||
41 | u32 gm20b_fuse_opt_sec_debug_en(struct gk20a *g); | ||
42 | u32 gm20b_fuse_opt_priv_sec_en(struct gk20a *g); | ||
36 | 43 | ||
37 | #endif | 44 | #endif |
diff --git a/drivers/gpu/nvgpu/common/fuse/fuse_gp106.c b/drivers/gpu/nvgpu/common/fuse/fuse_gp106.c new file mode 100644 index 00000000..17951e27 --- /dev/null +++ b/drivers/gpu/nvgpu/common/fuse/fuse_gp106.c | |||
@@ -0,0 +1,230 @@ | |||
1 | /* | ||
2 | * GP106 FUSE | ||
3 | * | ||
4 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice shall be included in | ||
14 | * all copies or substantial portions of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
22 | * DEALINGS IN THE SOFTWARE. | ||
23 | */ | ||
24 | |||
25 | #include <nvgpu/enabled.h> | ||
26 | #include <nvgpu/io.h> | ||
27 | |||
28 | #include "gk20a/gk20a.h" | ||
29 | |||
30 | #include "fuse_gp106.h" | ||
31 | |||
32 | #include <nvgpu/hw/gp106/hw_fuse_gp106.h> | ||
33 | |||
34 | int gp106_fuse_check_priv_security(struct gk20a *g) | ||
35 | { | ||
36 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); | ||
37 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true); | ||
38 | |||
39 | return 0; | ||
40 | } | ||
41 | |||
42 | u32 gp106_fuse_read_vin_cal_fuse_rev(struct gk20a *g) | ||
43 | { | ||
44 | return fuse_vin_cal_fuse_rev_data_v( | ||
45 | gk20a_readl(g, fuse_vin_cal_fuse_rev_r())); | ||
46 | } | ||
47 | |||
48 | u32 gp106_fuse_read_vin_cal_slope_intercept_fuse(struct gk20a *g, | ||
49 | u32 vin_id, u32 *slope, | ||
50 | u32 *intercept) | ||
51 | { | ||
52 | u32 data = 0; | ||
53 | u32 interceptdata = 0; | ||
54 | u32 slopedata = 0; | ||
55 | u32 gpc0data; | ||
56 | u32 gpc0slopedata; | ||
57 | u32 gpc0interceptdata; | ||
58 | |||
59 | /* read gpc0 irrespective of vin id */ | ||
60 | gpc0data = gk20a_readl(g, fuse_vin_cal_gpc0_r()); | ||
61 | if (gpc0data == 0xFFFFFFFF) | ||
62 | return -EINVAL; | ||
63 | |||
64 | switch (vin_id) { | ||
65 | case CTRL_CLK_VIN_ID_GPC0: | ||
66 | break; | ||
67 | |||
68 | case CTRL_CLK_VIN_ID_GPC1: | ||
69 | data = gk20a_readl(g, fuse_vin_cal_gpc1_delta_r()); | ||
70 | break; | ||
71 | |||
72 | case CTRL_CLK_VIN_ID_GPC2: | ||
73 | data = gk20a_readl(g, fuse_vin_cal_gpc2_delta_r()); | ||
74 | break; | ||
75 | |||
76 | case CTRL_CLK_VIN_ID_GPC3: | ||
77 | data = gk20a_readl(g, fuse_vin_cal_gpc3_delta_r()); | ||
78 | break; | ||
79 | |||
80 | case CTRL_CLK_VIN_ID_GPC4: | ||
81 | data = gk20a_readl(g, fuse_vin_cal_gpc4_delta_r()); | ||
82 | break; | ||
83 | |||
84 | case CTRL_CLK_VIN_ID_GPC5: | ||
85 | data = gk20a_readl(g, fuse_vin_cal_gpc5_delta_r()); | ||
86 | break; | ||
87 | |||
88 | case CTRL_CLK_VIN_ID_SYS: | ||
89 | case CTRL_CLK_VIN_ID_XBAR: | ||
90 | case CTRL_CLK_VIN_ID_LTC: | ||
91 | data = gk20a_readl(g, fuse_vin_cal_shared_delta_r()); | ||
92 | break; | ||
93 | |||
94 | case CTRL_CLK_VIN_ID_SRAM: | ||
95 | data = gk20a_readl(g, fuse_vin_cal_sram_delta_r()); | ||
96 | break; | ||
97 | |||
98 | default: | ||
99 | return -EINVAL; | ||
100 | } | ||
101 | if (data == 0xFFFFFFFF) | ||
102 | return -EINVAL; | ||
103 | |||
104 | gpc0interceptdata = (fuse_vin_cal_gpc0_icpt_int_data_v(gpc0data) << | ||
105 | fuse_vin_cal_gpc0_icpt_frac_data_s()) + | ||
106 | fuse_vin_cal_gpc0_icpt_frac_data_v(gpc0data); | ||
107 | gpc0interceptdata = (gpc0interceptdata * 1000U) >> | ||
108 | fuse_vin_cal_gpc0_icpt_frac_data_s(); | ||
109 | |||
110 | switch (vin_id) { | ||
111 | case CTRL_CLK_VIN_ID_GPC0: | ||
112 | break; | ||
113 | |||
114 | case CTRL_CLK_VIN_ID_GPC1: | ||
115 | case CTRL_CLK_VIN_ID_GPC2: | ||
116 | case CTRL_CLK_VIN_ID_GPC3: | ||
117 | case CTRL_CLK_VIN_ID_GPC4: | ||
118 | case CTRL_CLK_VIN_ID_GPC5: | ||
119 | case CTRL_CLK_VIN_ID_SYS: | ||
120 | case CTRL_CLK_VIN_ID_XBAR: | ||
121 | case CTRL_CLK_VIN_ID_LTC: | ||
122 | interceptdata = (fuse_vin_cal_gpc1_delta_icpt_int_data_v(data) << | ||
123 | fuse_vin_cal_gpc1_delta_icpt_frac_data_s()) + | ||
124 | fuse_vin_cal_gpc1_delta_icpt_frac_data_v(data); | ||
125 | interceptdata = (interceptdata * 1000U) >> | ||
126 | fuse_vin_cal_gpc1_delta_icpt_frac_data_s(); | ||
127 | break; | ||
128 | |||
129 | case CTRL_CLK_VIN_ID_SRAM: | ||
130 | interceptdata = (fuse_vin_cal_sram_delta_icpt_int_data_v(data) << | ||
131 | fuse_vin_cal_sram_delta_icpt_frac_data_s()) + | ||
132 | fuse_vin_cal_sram_delta_icpt_frac_data_v(data); | ||
133 | interceptdata = (interceptdata * 1000U) >> | ||
134 | fuse_vin_cal_sram_delta_icpt_frac_data_s(); | ||
135 | break; | ||
136 | |||
137 | default: | ||
138 | return -EINVAL; | ||
139 | } | ||
140 | |||
141 | if (fuse_vin_cal_gpc1_delta_icpt_sign_data_v(data)) | ||
142 | *intercept = gpc0interceptdata - interceptdata; | ||
143 | else | ||
144 | *intercept = gpc0interceptdata + interceptdata; | ||
145 | |||
146 | /* slope */ | ||
147 | gpc0slopedata = (fuse_vin_cal_gpc0_slope_int_data_v(gpc0data) << | ||
148 | fuse_vin_cal_gpc0_slope_frac_data_s()) + | ||
149 | fuse_vin_cal_gpc0_slope_frac_data_v(gpc0data); | ||
150 | gpc0slopedata = (gpc0slopedata * 1000U) >> | ||
151 | fuse_vin_cal_gpc0_slope_frac_data_s(); | ||
152 | switch (vin_id) { | ||
153 | case CTRL_CLK_VIN_ID_GPC0: | ||
154 | break; | ||
155 | |||
156 | case CTRL_CLK_VIN_ID_GPC1: | ||
157 | case CTRL_CLK_VIN_ID_GPC2: | ||
158 | case CTRL_CLK_VIN_ID_GPC3: | ||
159 | case CTRL_CLK_VIN_ID_GPC4: | ||
160 | case CTRL_CLK_VIN_ID_GPC5: | ||
161 | case CTRL_CLK_VIN_ID_SYS: | ||
162 | case CTRL_CLK_VIN_ID_XBAR: | ||
163 | case CTRL_CLK_VIN_ID_LTC: | ||
164 | case CTRL_CLK_VIN_ID_SRAM: | ||
165 | slopedata = | ||
166 | (fuse_vin_cal_gpc1_delta_slope_int_data_v(data)) * 1000; | ||
167 | break; | ||
168 | |||
169 | default: | ||
170 | return -EINVAL; | ||
171 | } | ||
172 | |||
173 | if (fuse_vin_cal_gpc1_delta_slope_sign_data_v(data)) | ||
174 | *slope = gpc0slopedata - slopedata; | ||
175 | else | ||
176 | *slope = gpc0slopedata + slopedata; | ||
177 | return 0; | ||
178 | } | ||
179 | |||
180 | u32 gp106_fuse_read_vin_cal_gain_offset_fuse(struct gk20a *g, | ||
181 | u32 vin_id, s8 *gain, | ||
182 | s8 *offset) | ||
183 | { | ||
184 | u32 data = 0; | ||
185 | |||
186 | switch (vin_id) { | ||
187 | case CTRL_CLK_VIN_ID_GPC0: | ||
188 | data = gk20a_readl(g, fuse_vin_cal_gpc0_r()); | ||
189 | break; | ||
190 | |||
191 | case CTRL_CLK_VIN_ID_GPC1: | ||
192 | data = gk20a_readl(g, fuse_vin_cal_gpc1_delta_r()); | ||
193 | break; | ||
194 | |||
195 | case CTRL_CLK_VIN_ID_GPC2: | ||
196 | data = gk20a_readl(g, fuse_vin_cal_gpc2_delta_r()); | ||
197 | break; | ||
198 | |||
199 | case CTRL_CLK_VIN_ID_GPC3: | ||
200 | data = gk20a_readl(g, fuse_vin_cal_gpc3_delta_r()); | ||
201 | break; | ||
202 | |||
203 | case CTRL_CLK_VIN_ID_GPC4: | ||
204 | data = gk20a_readl(g, fuse_vin_cal_gpc4_delta_r()); | ||
205 | break; | ||
206 | |||
207 | case CTRL_CLK_VIN_ID_GPC5: | ||
208 | data = gk20a_readl(g, fuse_vin_cal_gpc5_delta_r()); | ||
209 | break; | ||
210 | |||
211 | case CTRL_CLK_VIN_ID_SYS: | ||
212 | case CTRL_CLK_VIN_ID_XBAR: | ||
213 | case CTRL_CLK_VIN_ID_LTC: | ||
214 | data = gk20a_readl(g, fuse_vin_cal_shared_delta_r()); | ||
215 | break; | ||
216 | |||
217 | case CTRL_CLK_VIN_ID_SRAM: | ||
218 | data = gk20a_readl(g, fuse_vin_cal_sram_delta_r()); | ||
219 | break; | ||
220 | |||
221 | default: | ||
222 | return -EINVAL; | ||
223 | } | ||
224 | if (data == 0xFFFFFFFF) | ||
225 | return -EINVAL; | ||
226 | *gain = (s8) (data >> 16) & 0x1f; | ||
227 | *offset = (s8) data & 0x7f; | ||
228 | |||
229 | return 0; | ||
230 | } | ||
diff --git a/drivers/gpu/nvgpu/gp106/fuse_gp106.h b/drivers/gpu/nvgpu/common/fuse/fuse_gp106.h index dfb776b8..f014ee8c 100644 --- a/drivers/gpu/nvgpu/gp106/fuse_gp106.h +++ b/drivers/gpu/nvgpu/common/fuse/fuse_gp106.h | |||
@@ -28,5 +28,12 @@ | |||
28 | struct gk20a; | 28 | struct gk20a; |
29 | 29 | ||
30 | int gp106_fuse_check_priv_security(struct gk20a *g); | 30 | int gp106_fuse_check_priv_security(struct gk20a *g); |
31 | u32 gp106_fuse_read_vin_cal_fuse_rev(struct gk20a *g); | ||
32 | u32 gp106_fuse_read_vin_cal_slope_intercept_fuse(struct gk20a *g, | ||
33 | u32 vin_id, u32 *slope, | ||
34 | u32 *intercept); | ||
35 | u32 gp106_fuse_read_vin_cal_gain_offset_fuse(struct gk20a *g, | ||
36 | u32 vin_id, s8 *gain, | ||
37 | s8 *offset); | ||
31 | 38 | ||
32 | #endif | 39 | #endif |
diff --git a/drivers/gpu/nvgpu/gp10b/fuse_gp10b.c b/drivers/gpu/nvgpu/common/fuse/fuse_gp10b.c index a79d5e1c..3a26e1b9 100644 --- a/drivers/gpu/nvgpu/gp10b/fuse_gp10b.c +++ b/drivers/gpu/nvgpu/common/fuse/fuse_gp10b.c | |||
@@ -29,8 +29,7 @@ | |||
29 | 29 | ||
30 | #include "gk20a/gk20a.h" | 30 | #include "gk20a/gk20a.h" |
31 | 31 | ||
32 | #include "gm20b/fuse_gm20b.h" | 32 | #include "fuse_gm20b.h" |
33 | |||
34 | #include "fuse_gp10b.h" | 33 | #include "fuse_gp10b.h" |
35 | 34 | ||
36 | #include <nvgpu/hw/gp10b/hw_fuse_gp10b.h> | 35 | #include <nvgpu/hw/gp10b/hw_fuse_gp10b.h> |
diff --git a/drivers/gpu/nvgpu/gp10b/fuse_gp10b.h b/drivers/gpu/nvgpu/common/fuse/fuse_gp10b.h index d9037e22..d9037e22 100644 --- a/drivers/gpu/nvgpu/gp10b/fuse_gp10b.h +++ b/drivers/gpu/nvgpu/common/fuse/fuse_gp10b.h | |||
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 1fe0cb5d..febd7e0c 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -1256,6 +1256,20 @@ struct gpu_ops { | |||
1256 | int (*check_priv_security)(struct gk20a *g); | 1256 | int (*check_priv_security)(struct gk20a *g); |
1257 | bool (*is_opt_ecc_enable)(struct gk20a *g); | 1257 | bool (*is_opt_ecc_enable)(struct gk20a *g); |
1258 | bool (*is_opt_feature_override_disable)(struct gk20a *g); | 1258 | bool (*is_opt_feature_override_disable)(struct gk20a *g); |
1259 | u32 (*fuse_status_opt_fbio)(struct gk20a *g); | ||
1260 | u32 (*fuse_status_opt_fbp)(struct gk20a *g); | ||
1261 | u32 (*fuse_status_opt_rop_l2_fbp)(struct gk20a *g, u32 fbp); | ||
1262 | u32 (*fuse_status_opt_tpc_gpc)(struct gk20a *g, u32 gpc); | ||
1263 | void (*fuse_ctrl_opt_tpc_gpc)(struct gk20a *g, u32 gpc, u32 val); | ||
1264 | u32 (*fuse_opt_sec_debug_en)(struct gk20a *g); | ||
1265 | u32 (*fuse_opt_priv_sec_en)(struct gk20a *g); | ||
1266 | u32 (*read_vin_cal_fuse_rev)(struct gk20a *g); | ||
1267 | u32 (*read_vin_cal_slope_intercept_fuse)(struct gk20a *g, | ||
1268 | u32 vin_id, u32 *slope, | ||
1269 | u32 *intercept); | ||
1270 | u32 (*read_vin_cal_gain_offset_fuse)(struct gk20a *g, | ||
1271 | u32 vin_id, s8 *gain, | ||
1272 | s8 *offset); | ||
1259 | } fuse; | 1273 | } fuse; |
1260 | struct { | 1274 | struct { |
1261 | int (*init)(struct gk20a *g); | 1275 | int (*init)(struct gk20a *g); |
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index abc39362..68ae91e8 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c | |||
@@ -40,7 +40,6 @@ | |||
40 | #include <nvgpu/hw/gm20b/hw_fifo_gm20b.h> | 40 | #include <nvgpu/hw/gm20b/hw_fifo_gm20b.h> |
41 | #include <nvgpu/hw/gm20b/hw_top_gm20b.h> | 41 | #include <nvgpu/hw/gm20b/hw_top_gm20b.h> |
42 | #include <nvgpu/hw/gm20b/hw_ctxsw_prog_gm20b.h> | 42 | #include <nvgpu/hw/gm20b/hw_ctxsw_prog_gm20b.h> |
43 | #include <nvgpu/hw/gm20b/hw_fuse_gm20b.h> | ||
44 | #include <nvgpu/hw/gm20b/hw_perf_gm20b.h> | 43 | #include <nvgpu/hw/gm20b/hw_perf_gm20b.h> |
45 | 44 | ||
46 | void gr_gm20b_init_gpc_mmu(struct gk20a *g) | 45 | void gr_gm20b_init_gpc_mmu(struct gk20a *g) |
@@ -549,7 +548,7 @@ u32 gr_gm20b_get_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) | |||
549 | struct gr_gk20a *gr = &g->gr; | 548 | struct gr_gk20a *gr = &g->gr; |
550 | 549 | ||
551 | /* Toggle the bits of NV_FUSE_STATUS_OPT_TPC_GPC */ | 550 | /* Toggle the bits of NV_FUSE_STATUS_OPT_TPC_GPC */ |
552 | val = gk20a_readl(g, fuse_status_opt_tpc_gpc_r(gpc_index)); | 551 | val = g->ops.fuse.fuse_status_opt_tpc_gpc(g, gpc_index); |
553 | 552 | ||
554 | return (~val) & ((0x1 << gr->max_tpc_per_gpc_count) - 1); | 553 | return (~val) & ((0x1 << gr->max_tpc_per_gpc_count) - 1); |
555 | } | 554 | } |
@@ -1076,7 +1075,7 @@ u32 gr_gm20b_get_fbp_en_mask(struct gk20a *g) | |||
1076 | * flip the bits. | 1075 | * flip the bits. |
1077 | * Also set unused bits to zero | 1076 | * Also set unused bits to zero |
1078 | */ | 1077 | */ |
1079 | fbp_en_mask = gk20a_readl(g, fuse_status_opt_fbp_r()); | 1078 | fbp_en_mask = g->ops.fuse.fuse_status_opt_fbp(g); |
1080 | fbp_en_mask = ~fbp_en_mask; | 1079 | fbp_en_mask = ~fbp_en_mask; |
1081 | fbp_en_mask = fbp_en_mask & ((1 << max_fbps_count) - 1); | 1080 | fbp_en_mask = fbp_en_mask & ((1 << max_fbps_count) - 1); |
1082 | 1081 | ||
@@ -1114,7 +1113,7 @@ u32 *gr_gm20b_rop_l2_en_mask(struct gk20a *g) | |||
1114 | 1113 | ||
1115 | /* mask of Rop_L2 for each FBP */ | 1114 | /* mask of Rop_L2 for each FBP */ |
1116 | for_each_set_bit(i, &fbp_en_mask, max_fbps_count) { | 1115 | for_each_set_bit(i, &fbp_en_mask, max_fbps_count) { |
1117 | tmp = gk20a_readl(g, fuse_status_opt_rop_l2_fbp_r(i)); | 1116 | tmp = g->ops.fuse.fuse_status_opt_rop_l2_fbp(g, i); |
1118 | gr->fbp_rop_l2_en_mask[i] = rop_l2_all_en ^ tmp; | 1117 | gr->fbp_rop_l2_en_mask[i] = rop_l2_all_en ^ tmp; |
1119 | } | 1118 | } |
1120 | 1119 | ||
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index 431cfc9b..acdf4591 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c | |||
@@ -32,6 +32,7 @@ | |||
32 | #include "common/therm/therm_gm20b.h" | 32 | #include "common/therm/therm_gm20b.h" |
33 | #include "common/therm/therm_gm20b.h" | 33 | #include "common/therm/therm_gm20b.h" |
34 | #include "common/ltc/ltc_gm20b.h" | 34 | #include "common/ltc/ltc_gm20b.h" |
35 | #include "common/fuse/fuse_gm20b.h" | ||
35 | 36 | ||
36 | #include "gk20a/gk20a.h" | 37 | #include "gk20a/gk20a.h" |
37 | #include "gk20a/ce2_gk20a.h" | 38 | #include "gk20a/ce2_gk20a.h" |
@@ -55,7 +56,6 @@ | |||
55 | #include "regops_gm20b.h" | 56 | #include "regops_gm20b.h" |
56 | #include "hal_gm20b.h" | 57 | #include "hal_gm20b.h" |
57 | #include "acr_gm20b.h" | 58 | #include "acr_gm20b.h" |
58 | #include "fuse_gm20b.h" | ||
59 | 59 | ||
60 | #include <nvgpu/debug.h> | 60 | #include <nvgpu/debug.h> |
61 | #include <nvgpu/bug.h> | 61 | #include <nvgpu/bug.h> |
@@ -64,7 +64,6 @@ | |||
64 | #include <nvgpu/error_notifier.h> | 64 | #include <nvgpu/error_notifier.h> |
65 | 65 | ||
66 | #include <nvgpu/hw/gm20b/hw_proj_gm20b.h> | 66 | #include <nvgpu/hw/gm20b/hw_proj_gm20b.h> |
67 | #include <nvgpu/hw/gm20b/hw_fuse_gm20b.h> | ||
68 | #include <nvgpu/hw/gm20b/hw_fifo_gm20b.h> | 67 | #include <nvgpu/hw/gm20b/hw_fifo_gm20b.h> |
69 | #include <nvgpu/hw/gm20b/hw_ram_gm20b.h> | 68 | #include <nvgpu/hw/gm20b/hw_ram_gm20b.h> |
70 | #include <nvgpu/hw/gm20b/hw_top_gm20b.h> | 69 | #include <nvgpu/hw/gm20b/hw_top_gm20b.h> |
@@ -649,6 +648,16 @@ static const struct gpu_ops gm20b_ops = { | |||
649 | }, | 648 | }, |
650 | .fuse = { | 649 | .fuse = { |
651 | .check_priv_security = gm20b_fuse_check_priv_security, | 650 | .check_priv_security = gm20b_fuse_check_priv_security, |
651 | .fuse_status_opt_fbio = gm20b_fuse_status_opt_fbio, | ||
652 | .fuse_status_opt_fbp = gm20b_fuse_status_opt_fbp, | ||
653 | .fuse_status_opt_rop_l2_fbp = gm20b_fuse_status_opt_rop_l2_fbp, | ||
654 | .fuse_status_opt_tpc_gpc = gm20b_fuse_status_opt_tpc_gpc, | ||
655 | .fuse_ctrl_opt_tpc_gpc = gm20b_fuse_ctrl_opt_tpc_gpc, | ||
656 | .fuse_opt_sec_debug_en = gm20b_fuse_opt_sec_debug_en, | ||
657 | .fuse_opt_priv_sec_en = gm20b_fuse_opt_priv_sec_en, | ||
658 | .read_vin_cal_fuse_rev = NULL, | ||
659 | .read_vin_cal_slope_intercept_fuse = NULL, | ||
660 | .read_vin_cal_gain_offset_fuse = NULL, | ||
652 | }, | 661 | }, |
653 | .chip_init_gpu_characteristics = gk20a_init_gpu_characteristics, | 662 | .chip_init_gpu_characteristics = gk20a_init_gpu_characteristics, |
654 | .get_litter_value = gm20b_get_litter_value, | 663 | .get_litter_value = gm20b_get_litter_value, |
diff --git a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c index 731078f7..53bec96f 100644 --- a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c | |||
@@ -36,7 +36,6 @@ | |||
36 | 36 | ||
37 | #include <nvgpu/hw/gm20b/hw_gr_gm20b.h> | 37 | #include <nvgpu/hw/gm20b/hw_gr_gm20b.h> |
38 | #include <nvgpu/hw/gm20b/hw_pwr_gm20b.h> | 38 | #include <nvgpu/hw/gm20b/hw_pwr_gm20b.h> |
39 | #include <nvgpu/hw/gm20b/hw_fuse_gm20b.h> | ||
40 | 39 | ||
41 | #define gm20b_dbg_pmu(g, fmt, arg...) \ | 40 | #define gm20b_dbg_pmu(g, fmt, arg...) \ |
42 | nvgpu_log(g, gpu_dbg_pmu, fmt, ##arg) | 41 | nvgpu_log(g, gpu_dbg_pmu, fmt, ##arg) |
@@ -267,9 +266,9 @@ void pmu_dump_security_fuses_gm20b(struct gk20a *g) | |||
267 | u32 val; | 266 | u32 val; |
268 | 267 | ||
269 | nvgpu_err(g, "FUSE_OPT_SEC_DEBUG_EN_0: 0x%x", | 268 | nvgpu_err(g, "FUSE_OPT_SEC_DEBUG_EN_0: 0x%x", |
270 | gk20a_readl(g, fuse_opt_sec_debug_en_r())); | 269 | g->ops.fuse.fuse_opt_sec_debug_en(g)); |
271 | nvgpu_err(g, "FUSE_OPT_PRIV_SEC_EN_0: 0x%x", | 270 | nvgpu_err(g, "FUSE_OPT_PRIV_SEC_EN_0: 0x%x", |
272 | gk20a_readl(g, fuse_opt_priv_sec_en_r())); | 271 | g->ops.fuse.fuse_opt_priv_sec_en(g)); |
273 | nvgpu_tegra_fuse_read_gcplex_config_fuse(g, &val); | 272 | nvgpu_tegra_fuse_read_gcplex_config_fuse(g, &val); |
274 | nvgpu_err(g, "FUSE_GCPLEX_CONFIG_FUSE_0: 0x%x", val); | 273 | nvgpu_err(g, "FUSE_GCPLEX_CONFIG_FUSE_0: 0x%x", val); |
275 | } | 274 | } |
diff --git a/drivers/gpu/nvgpu/gp106/fuse_gp106.c b/drivers/gpu/nvgpu/gp106/fuse_gp106.c deleted file mode 100644 index 82e3217f..00000000 --- a/drivers/gpu/nvgpu/gp106/fuse_gp106.c +++ /dev/null | |||
@@ -1,37 +0,0 @@ | |||
1 | /* | ||
2 | * GP106 FUSE | ||
3 | * | ||
4 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice shall be included in | ||
14 | * all copies or substantial portions of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
22 | * DEALINGS IN THE SOFTWARE. | ||
23 | */ | ||
24 | |||
25 | #include <nvgpu/enabled.h> | ||
26 | #include <nvgpu/io.h> | ||
27 | |||
28 | #include "gk20a/gk20a.h" | ||
29 | #include "gp106/fuse_gp106.h" | ||
30 | |||
31 | int gp106_fuse_check_priv_security(struct gk20a *g) | ||
32 | { | ||
33 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); | ||
34 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true); | ||
35 | |||
36 | return 0; | ||
37 | } | ||
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c index 52fcc9d3..f3b5dd87 100644 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c | |||
@@ -38,6 +38,9 @@ | |||
38 | #include "common/therm/therm_gp106.h" | 38 | #include "common/therm/therm_gp106.h" |
39 | #include "common/ltc/ltc_gm20b.h" | 39 | #include "common/ltc/ltc_gm20b.h" |
40 | #include "common/ltc/ltc_gp10b.h" | 40 | #include "common/ltc/ltc_gp10b.h" |
41 | #include "common/fuse/fuse_gm20b.h" | ||
42 | #include "common/fuse/fuse_gp10b.h" | ||
43 | #include "common/fuse/fuse_gp106.h" | ||
41 | 44 | ||
42 | #include "gk20a/gk20a.h" | 45 | #include "gk20a/gk20a.h" |
43 | #include "gk20a/fifo_gk20a.h" | 46 | #include "gk20a/fifo_gk20a.h" |
@@ -60,7 +63,6 @@ | |||
60 | #include "gp10b/fifo_gp10b.h" | 63 | #include "gp10b/fifo_gp10b.h" |
61 | #include "gp10b/pmu_gp10b.h" | 64 | #include "gp10b/pmu_gp10b.h" |
62 | #include "gp10b/gr_gp10b.h" | 65 | #include "gp10b/gr_gp10b.h" |
63 | #include "gp10b/fuse_gp10b.h" | ||
64 | 66 | ||
65 | #include "gp106/fifo_gp106.h" | 67 | #include "gp106/fifo_gp106.h" |
66 | #include "gp106/regops_gp106.h" | 68 | #include "gp106/regops_gp106.h" |
@@ -85,7 +87,6 @@ | |||
85 | #include "gp106/gr_ctx_gp106.h" | 87 | #include "gp106/gr_ctx_gp106.h" |
86 | #include "gp106/gr_gp106.h" | 88 | #include "gp106/gr_gp106.h" |
87 | #include "gp106/flcn_gp106.h" | 89 | #include "gp106/flcn_gp106.h" |
88 | #include "gp106/fuse_gp106.h" | ||
89 | 90 | ||
90 | #include "hal_gp106.h" | 91 | #include "hal_gp106.h" |
91 | 92 | ||
@@ -788,6 +789,18 @@ static const struct gpu_ops gp106_ops = { | |||
788 | .is_opt_ecc_enable = gp10b_fuse_is_opt_ecc_enable, | 789 | .is_opt_ecc_enable = gp10b_fuse_is_opt_ecc_enable, |
789 | .is_opt_feature_override_disable = | 790 | .is_opt_feature_override_disable = |
790 | gp10b_fuse_is_opt_feature_override_disable, | 791 | gp10b_fuse_is_opt_feature_override_disable, |
792 | .fuse_status_opt_fbio = gm20b_fuse_status_opt_fbio, | ||
793 | .fuse_status_opt_fbp = gm20b_fuse_status_opt_fbp, | ||
794 | .fuse_status_opt_rop_l2_fbp = gm20b_fuse_status_opt_rop_l2_fbp, | ||
795 | .fuse_status_opt_tpc_gpc = gm20b_fuse_status_opt_tpc_gpc, | ||
796 | .fuse_ctrl_opt_tpc_gpc = gm20b_fuse_ctrl_opt_tpc_gpc, | ||
797 | .fuse_opt_sec_debug_en = gm20b_fuse_opt_sec_debug_en, | ||
798 | .fuse_opt_priv_sec_en = gm20b_fuse_opt_priv_sec_en, | ||
799 | .read_vin_cal_fuse_rev = gp106_fuse_read_vin_cal_fuse_rev, | ||
800 | .read_vin_cal_slope_intercept_fuse = | ||
801 | gp106_fuse_read_vin_cal_slope_intercept_fuse, | ||
802 | .read_vin_cal_gain_offset_fuse = | ||
803 | gp106_fuse_read_vin_cal_gain_offset_fuse, | ||
791 | }, | 804 | }, |
792 | .get_litter_value = gp106_get_litter_value, | 805 | .get_litter_value = gp106_get_litter_value, |
793 | .chip_init_gpu_characteristics = gp106_init_gpu_characteristics, | 806 | .chip_init_gpu_characteristics = gp106_init_gpu_characteristics, |
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 7df17ed7..efd66b5d 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c | |||
@@ -36,6 +36,8 @@ | |||
36 | #include "common/therm/therm_gp10b.h" | 36 | #include "common/therm/therm_gp10b.h" |
37 | #include "common/ltc/ltc_gm20b.h" | 37 | #include "common/ltc/ltc_gm20b.h" |
38 | #include "common/ltc/ltc_gp10b.h" | 38 | #include "common/ltc/ltc_gp10b.h" |
39 | #include "common/fuse/fuse_gm20b.h" | ||
40 | #include "common/fuse/fuse_gp10b.h" | ||
39 | 41 | ||
40 | #include "gk20a/gk20a.h" | 42 | #include "gk20a/gk20a.h" |
41 | #include "gk20a/fifo_gk20a.h" | 43 | #include "gk20a/fifo_gk20a.h" |
@@ -70,7 +72,6 @@ | |||
70 | 72 | ||
71 | #include "gp10b.h" | 73 | #include "gp10b.h" |
72 | #include "hal_gp10b.h" | 74 | #include "hal_gp10b.h" |
73 | #include "fuse_gp10b.h" | ||
74 | 75 | ||
75 | #include <nvgpu/debug.h> | 76 | #include <nvgpu/debug.h> |
76 | #include <nvgpu/bug.h> | 77 | #include <nvgpu/bug.h> |
@@ -80,7 +81,6 @@ | |||
80 | #include <nvgpu/error_notifier.h> | 81 | #include <nvgpu/error_notifier.h> |
81 | 82 | ||
82 | #include <nvgpu/hw/gp10b/hw_proj_gp10b.h> | 83 | #include <nvgpu/hw/gp10b/hw_proj_gp10b.h> |
83 | #include <nvgpu/hw/gp10b/hw_fuse_gp10b.h> | ||
84 | #include <nvgpu/hw/gp10b/hw_fifo_gp10b.h> | 84 | #include <nvgpu/hw/gp10b/hw_fifo_gp10b.h> |
85 | #include <nvgpu/hw/gp10b/hw_ram_gp10b.h> | 85 | #include <nvgpu/hw/gp10b/hw_ram_gp10b.h> |
86 | #include <nvgpu/hw/gp10b/hw_top_gp10b.h> | 86 | #include <nvgpu/hw/gp10b/hw_top_gp10b.h> |
@@ -597,7 +597,7 @@ static const struct gpu_ops gp10b_ops = { | |||
597 | .pmu_pg_init_param = gp10b_pg_gr_init, | 597 | .pmu_pg_init_param = gp10b_pg_gr_init, |
598 | .pmu_pg_supported_engines_list = gk20a_pmu_pg_engines_list, | 598 | .pmu_pg_supported_engines_list = gk20a_pmu_pg_engines_list, |
599 | .pmu_pg_engines_feature_list = gk20a_pmu_pg_feature_list, | 599 | .pmu_pg_engines_feature_list = gk20a_pmu_pg_feature_list, |
600 | .dump_secure_fuses = pmu_dump_security_fuses_gp10b, | 600 | .dump_secure_fuses = pmu_dump_security_fuses_gm20b, |
601 | .reset_engine = gk20a_pmu_engine_reset, | 601 | .reset_engine = gk20a_pmu_engine_reset, |
602 | .is_engine_in_reset = gk20a_pmu_is_engine_in_reset, | 602 | .is_engine_in_reset = gk20a_pmu_is_engine_in_reset, |
603 | .get_irqdest = gk20a_pmu_get_irqdest, | 603 | .get_irqdest = gk20a_pmu_get_irqdest, |
@@ -702,6 +702,16 @@ static const struct gpu_ops gp10b_ops = { | |||
702 | .is_opt_ecc_enable = gp10b_fuse_is_opt_ecc_enable, | 702 | .is_opt_ecc_enable = gp10b_fuse_is_opt_ecc_enable, |
703 | .is_opt_feature_override_disable = | 703 | .is_opt_feature_override_disable = |
704 | gp10b_fuse_is_opt_feature_override_disable, | 704 | gp10b_fuse_is_opt_feature_override_disable, |
705 | .fuse_status_opt_fbio = gm20b_fuse_status_opt_fbio, | ||
706 | .fuse_status_opt_fbp = gm20b_fuse_status_opt_fbp, | ||
707 | .fuse_status_opt_rop_l2_fbp = gm20b_fuse_status_opt_rop_l2_fbp, | ||
708 | .fuse_status_opt_tpc_gpc = gm20b_fuse_status_opt_tpc_gpc, | ||
709 | .fuse_ctrl_opt_tpc_gpc = gm20b_fuse_ctrl_opt_tpc_gpc, | ||
710 | .fuse_opt_sec_debug_en = gm20b_fuse_opt_sec_debug_en, | ||
711 | .fuse_opt_priv_sec_en = gm20b_fuse_opt_priv_sec_en, | ||
712 | .read_vin_cal_fuse_rev = NULL, | ||
713 | .read_vin_cal_slope_intercept_fuse = NULL, | ||
714 | .read_vin_cal_gain_offset_fuse = NULL, | ||
705 | }, | 715 | }, |
706 | .chip_init_gpu_characteristics = gp10b_init_gpu_characteristics, | 716 | .chip_init_gpu_characteristics = gp10b_init_gpu_characteristics, |
707 | .get_litter_value = gp10b_get_litter_value, | 717 | .get_litter_value = gp10b_get_litter_value, |
diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c index 6ecb7957..d6497173 100644 --- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | |||
@@ -36,7 +36,6 @@ | |||
36 | #include "pmu_gp10b.h" | 36 | #include "pmu_gp10b.h" |
37 | 37 | ||
38 | #include <nvgpu/hw/gp10b/hw_pwr_gp10b.h> | 38 | #include <nvgpu/hw/gp10b/hw_pwr_gp10b.h> |
39 | #include <nvgpu/hw/gp10b/hw_fuse_gp10b.h> | ||
40 | 39 | ||
41 | #define gp10b_dbg_pmu(g, fmt, arg...) \ | 40 | #define gp10b_dbg_pmu(g, fmt, arg...) \ |
42 | nvgpu_log(g, gpu_dbg_pmu, fmt, ##arg) | 41 | nvgpu_log(g, gpu_dbg_pmu, fmt, ##arg) |
@@ -375,19 +374,6 @@ bool gp10b_is_priv_load(u32 falcon_id) | |||
375 | return enable_status; | 374 | return enable_status; |
376 | } | 375 | } |
377 | 376 | ||
378 | /*Dump Security related fuses*/ | ||
379 | void pmu_dump_security_fuses_gp10b(struct gk20a *g) | ||
380 | { | ||
381 | u32 val; | ||
382 | |||
383 | nvgpu_err(g, "FUSE_OPT_SEC_DEBUG_EN_0: 0x%x", | ||
384 | gk20a_readl(g, fuse_opt_sec_debug_en_r())); | ||
385 | nvgpu_err(g, "FUSE_OPT_PRIV_SEC_EN_0: 0x%x", | ||
386 | gk20a_readl(g, fuse_opt_priv_sec_en_r())); | ||
387 | nvgpu_tegra_fuse_read_gcplex_config_fuse(g, &val); | ||
388 | nvgpu_err(g, "FUSE_GCPLEX_CONFIG_FUSE_0: 0x%x", val); | ||
389 | } | ||
390 | |||
391 | bool gp10b_is_pmu_supported(struct gk20a *g) | 377 | bool gp10b_is_pmu_supported(struct gk20a *g) |
392 | { | 378 | { |
393 | return true; | 379 | return true; |
diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.h b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.h index 44e0ec98..87c3ba79 100644 --- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.h | |||
@@ -35,7 +35,6 @@ int gp10b_init_pmu_setup_hw1(struct gk20a *g); | |||
35 | void gp10b_pmu_elpg_statistics(struct gk20a *g, u32 pg_engine_id, | 35 | void gp10b_pmu_elpg_statistics(struct gk20a *g, u32 pg_engine_id, |
36 | struct pmu_pg_stats_data *pg_stat_data); | 36 | struct pmu_pg_stats_data *pg_stat_data); |
37 | int gp10b_pmu_setup_elpg(struct gk20a *g); | 37 | int gp10b_pmu_setup_elpg(struct gk20a *g); |
38 | void pmu_dump_security_fuses_gp10b(struct gk20a *g); | ||
39 | int gp10b_load_falcon_ucode(struct gk20a *g, u32 falconidmask); | 38 | int gp10b_load_falcon_ucode(struct gk20a *g, u32 falconidmask); |
40 | int gp10b_pg_gr_init(struct gk20a *g, u32 pg_engine_id); | 39 | int gp10b_pg_gr_init(struct gk20a *g, u32 pg_engine_id); |
41 | void gp10b_write_dmatrfbase(struct gk20a *g, u32 addr); | 40 | void gp10b_write_dmatrfbase(struct gk20a *g, u32 addr); |
diff --git a/drivers/gpu/nvgpu/gv100/gr_gv100.c b/drivers/gpu/nvgpu/gv100/gr_gv100.c index 13092f2a..79526947 100644 --- a/drivers/gpu/nvgpu/gv100/gr_gv100.c +++ b/drivers/gpu/nvgpu/gv100/gr_gv100.c | |||
@@ -37,7 +37,6 @@ | |||
37 | #include <nvgpu/hw/gv100/hw_gr_gv100.h> | 37 | #include <nvgpu/hw/gv100/hw_gr_gv100.h> |
38 | #include <nvgpu/hw/gv100/hw_fb_gv100.h> | 38 | #include <nvgpu/hw/gv100/hw_fb_gv100.h> |
39 | #include <nvgpu/hw/gv100/hw_proj_gv100.h> | 39 | #include <nvgpu/hw/gv100/hw_proj_gv100.h> |
40 | #include <nvgpu/hw/gv100/hw_fuse_gv100.h> | ||
41 | #include <nvgpu/hw/gv100/hw_top_gv100.h> | 40 | #include <nvgpu/hw/gv100/hw_top_gv100.h> |
42 | #include <nvgpu/hw/gv100/hw_ctxsw_prog_gv100.h> | 41 | #include <nvgpu/hw/gv100/hw_ctxsw_prog_gv100.h> |
43 | #include <nvgpu/hw/gv100/hw_perf_gv100.h> | 42 | #include <nvgpu/hw/gv100/hw_perf_gv100.h> |
@@ -391,7 +390,7 @@ static u32 gr_gv100_get_active_fpba_mask(struct gk20a *g) | |||
391 | * flip the bits. | 390 | * flip the bits. |
392 | * Also set unused bits to zero | 391 | * Also set unused bits to zero |
393 | */ | 392 | */ |
394 | active_fbpa_mask = nvgpu_readl(g, fuse_status_opt_fbio_r()); | 393 | active_fbpa_mask = g->ops.fuse.fuse_status_opt_fbio(g); |
395 | active_fbpa_mask = ~active_fbpa_mask; | 394 | active_fbpa_mask = ~active_fbpa_mask; |
396 | active_fbpa_mask = active_fbpa_mask & ((1 << num_fbpas) - 1); | 395 | active_fbpa_mask = active_fbpa_mask & ((1 << num_fbpas) - 1); |
397 | 396 | ||
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 8565d5fc..69ad018a 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c | |||
@@ -42,6 +42,9 @@ | |||
42 | #include "common/ltc/ltc_gm20b.h" | 42 | #include "common/ltc/ltc_gm20b.h" |
43 | #include "common/ltc/ltc_gp10b.h" | 43 | #include "common/ltc/ltc_gp10b.h" |
44 | #include "common/ltc/ltc_gv11b.h" | 44 | #include "common/ltc/ltc_gv11b.h" |
45 | #include "common/fuse/fuse_gm20b.h" | ||
46 | #include "common/fuse/fuse_gp10b.h" | ||
47 | #include "common/fuse/fuse_gp106.h" | ||
45 | 48 | ||
46 | #include "gk20a/gk20a.h" | 49 | #include "gk20a/gk20a.h" |
47 | #include "gk20a/fifo_gk20a.h" | 50 | #include "gk20a/fifo_gk20a.h" |
@@ -77,7 +80,6 @@ | |||
77 | #include "gp10b/fecs_trace_gp10b.h" | 80 | #include "gp10b/fecs_trace_gp10b.h" |
78 | #include "gp10b/mm_gp10b.h" | 81 | #include "gp10b/mm_gp10b.h" |
79 | #include "gp10b/pmu_gp10b.h" | 82 | #include "gp10b/pmu_gp10b.h" |
80 | #include "gp10b/fuse_gp10b.h" | ||
81 | 83 | ||
82 | #include "gv11b/css_gr_gv11b.h" | 84 | #include "gv11b/css_gr_gv11b.h" |
83 | #include "gv11b/dbg_gpu_gv11b.h" | 85 | #include "gv11b/dbg_gpu_gv11b.h" |
@@ -883,6 +885,18 @@ static const struct gpu_ops gv100_ops = { | |||
883 | .is_opt_ecc_enable = gp10b_fuse_is_opt_ecc_enable, | 885 | .is_opt_ecc_enable = gp10b_fuse_is_opt_ecc_enable, |
884 | .is_opt_feature_override_disable = | 886 | .is_opt_feature_override_disable = |
885 | gp10b_fuse_is_opt_feature_override_disable, | 887 | gp10b_fuse_is_opt_feature_override_disable, |
888 | .fuse_status_opt_fbio = gm20b_fuse_status_opt_fbio, | ||
889 | .fuse_status_opt_fbp = gm20b_fuse_status_opt_fbp, | ||
890 | .fuse_status_opt_rop_l2_fbp = gm20b_fuse_status_opt_rop_l2_fbp, | ||
891 | .fuse_status_opt_tpc_gpc = gm20b_fuse_status_opt_tpc_gpc, | ||
892 | .fuse_ctrl_opt_tpc_gpc = gm20b_fuse_ctrl_opt_tpc_gpc, | ||
893 | .fuse_opt_sec_debug_en = gm20b_fuse_opt_sec_debug_en, | ||
894 | .fuse_opt_priv_sec_en = gm20b_fuse_opt_priv_sec_en, | ||
895 | .read_vin_cal_fuse_rev = gp106_fuse_read_vin_cal_fuse_rev, | ||
896 | .read_vin_cal_slope_intercept_fuse = | ||
897 | gp106_fuse_read_vin_cal_slope_intercept_fuse, | ||
898 | .read_vin_cal_gain_offset_fuse = | ||
899 | gp106_fuse_read_vin_cal_gain_offset_fuse, | ||
886 | }, | 900 | }, |
887 | #if defined(CONFIG_TEGRA_NVLINK) | 901 | #if defined(CONFIG_TEGRA_NVLINK) |
888 | .nvlink = { | 902 | .nvlink = { |
@@ -947,6 +961,7 @@ int gv100_init_hal(struct gk20a *g) | |||
947 | gops->xve = gv100_ops.xve; | 961 | gops->xve = gv100_ops.xve; |
948 | gops->falcon = gv100_ops.falcon; | 962 | gops->falcon = gv100_ops.falcon; |
949 | gops->priv_ring = gv100_ops.priv_ring; | 963 | gops->priv_ring = gv100_ops.priv_ring; |
964 | gops->fuse = gv100_ops.fuse; | ||
950 | gops->nvlink = gv100_ops.nvlink; | 965 | gops->nvlink = gv100_ops.nvlink; |
951 | 966 | ||
952 | /* clocks */ | 967 | /* clocks */ |
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 41d2f695..5d237839 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c | |||
@@ -59,7 +59,6 @@ | |||
59 | #include <nvgpu/hw/gv11b/hw_ram_gv11b.h> | 59 | #include <nvgpu/hw/gv11b/hw_ram_gv11b.h> |
60 | #include <nvgpu/hw/gv11b/hw_pbdma_gv11b.h> | 60 | #include <nvgpu/hw/gv11b/hw_pbdma_gv11b.h> |
61 | #include <nvgpu/hw/gv11b/hw_perf_gv11b.h> | 61 | #include <nvgpu/hw/gv11b/hw_perf_gv11b.h> |
62 | #include <nvgpu/hw/gv11b/hw_fuse_gv11b.h> | ||
63 | 62 | ||
64 | #define GFXP_WFI_TIMEOUT_COUNT_IN_USEC_DEFAULT 100 | 63 | #define GFXP_WFI_TIMEOUT_COUNT_IN_USEC_DEFAULT 100 |
65 | 64 | ||
@@ -131,16 +130,16 @@ bool gr_gv11b_is_valid_gfx_class(struct gk20a *g, u32 class_num) | |||
131 | 130 | ||
132 | void gr_gv11b_powergate_tpc(struct gk20a *g) | 131 | void gr_gv11b_powergate_tpc(struct gk20a *g) |
133 | { | 132 | { |
134 | u32 tpc_pg_status = gk20a_readl(g, fuse_status_opt_tpc_gpc_r(0)); | 133 | u32 tpc_pg_status = g->ops.fuse.fuse_status_opt_tpc_gpc(g, 0); |
135 | 134 | ||
136 | if (tpc_pg_status == g->tpc_pg_mask) { | 135 | if (tpc_pg_status == g->tpc_pg_mask) { |
137 | return; | 136 | return; |
138 | } | 137 | } |
139 | 138 | ||
140 | gk20a_writel(g, fuse_ctrl_opt_tpc_gpc_r(0), (g->tpc_pg_mask)); | 139 | g->ops.fuse.fuse_ctrl_opt_tpc_gpc(g, 0, g->tpc_pg_mask); |
141 | 140 | ||
142 | do { | 141 | do { |
143 | tpc_pg_status = gk20a_readl(g, fuse_status_opt_tpc_gpc_r(0)); | 142 | tpc_pg_status = g->ops.fuse.fuse_status_opt_tpc_gpc(g, 0); |
144 | } while (tpc_pg_status != g->tpc_pg_mask); | 143 | } while (tpc_pg_status != g->tpc_pg_mask); |
145 | 144 | ||
146 | gk20a_writel(g, gr_fe_tpc_pesmask_r(), gr_fe_tpc_pesmask_req_send_f() | | 145 | gk20a_writel(g, gr_fe_tpc_pesmask_r(), gr_fe_tpc_pesmask_req_send_f() | |
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index baafa801..0989e00a 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c | |||
@@ -39,6 +39,8 @@ | |||
39 | #include "common/ltc/ltc_gm20b.h" | 39 | #include "common/ltc/ltc_gm20b.h" |
40 | #include "common/ltc/ltc_gp10b.h" | 40 | #include "common/ltc/ltc_gp10b.h" |
41 | #include "common/ltc/ltc_gv11b.h" | 41 | #include "common/ltc/ltc_gv11b.h" |
42 | #include "common/fuse/fuse_gm20b.h" | ||
43 | #include "common/fuse/fuse_gp10b.h" | ||
42 | 44 | ||
43 | #include "gk20a/gk20a.h" | 45 | #include "gk20a/gk20a.h" |
44 | #include "gk20a/fifo_gk20a.h" | 46 | #include "gk20a/fifo_gk20a.h" |
@@ -65,7 +67,6 @@ | |||
65 | #include "gp10b/mm_gp10b.h" | 67 | #include "gp10b/mm_gp10b.h" |
66 | #include "gp10b/pmu_gp10b.h" | 68 | #include "gp10b/pmu_gp10b.h" |
67 | #include "gp10b/gr_gp10b.h" | 69 | #include "gp10b/gr_gp10b.h" |
68 | #include "gp10b/fuse_gp10b.h" | ||
69 | 70 | ||
70 | #include "gp106/pmu_gp106.h" | 71 | #include "gp106/pmu_gp106.h" |
71 | #include "gp106/acr_gp106.h" | 72 | #include "gp106/acr_gp106.h" |
@@ -100,7 +101,6 @@ | |||
100 | #include <nvgpu/hw/gv11b/hw_ram_gv11b.h> | 101 | #include <nvgpu/hw/gv11b/hw_ram_gv11b.h> |
101 | #include <nvgpu/hw/gv11b/hw_top_gv11b.h> | 102 | #include <nvgpu/hw/gv11b/hw_top_gv11b.h> |
102 | #include <nvgpu/hw/gv11b/hw_pwr_gv11b.h> | 103 | #include <nvgpu/hw/gv11b/hw_pwr_gv11b.h> |
103 | #include <nvgpu/hw/gv11b/hw_fuse_gv11b.h> | ||
104 | #include <nvgpu/hw/gv11b/hw_gr_gv11b.h> | 104 | #include <nvgpu/hw/gv11b/hw_gr_gv11b.h> |
105 | 105 | ||
106 | int gv11b_get_litter_value(struct gk20a *g, int value) | 106 | int gv11b_get_litter_value(struct gk20a *g, int value) |
@@ -689,7 +689,7 @@ static const struct gpu_ops gv11b_ops = { | |||
689 | .pmu_pg_init_param = gv11b_pg_gr_init, | 689 | .pmu_pg_init_param = gv11b_pg_gr_init, |
690 | .pmu_pg_supported_engines_list = gk20a_pmu_pg_engines_list, | 690 | .pmu_pg_supported_engines_list = gk20a_pmu_pg_engines_list, |
691 | .pmu_pg_engines_feature_list = gk20a_pmu_pg_feature_list, | 691 | .pmu_pg_engines_feature_list = gk20a_pmu_pg_feature_list, |
692 | .dump_secure_fuses = pmu_dump_security_fuses_gp10b, | 692 | .dump_secure_fuses = pmu_dump_security_fuses_gm20b, |
693 | .reset_engine = gp106_pmu_engine_reset, | 693 | .reset_engine = gp106_pmu_engine_reset, |
694 | .is_engine_in_reset = gp106_pmu_is_engine_in_reset, | 694 | .is_engine_in_reset = gp106_pmu_is_engine_in_reset, |
695 | .pmu_nsbootstrap = gv11b_pmu_bootstrap, | 695 | .pmu_nsbootstrap = gv11b_pmu_bootstrap, |
@@ -801,6 +801,16 @@ static const struct gpu_ops gv11b_ops = { | |||
801 | .is_opt_ecc_enable = gp10b_fuse_is_opt_ecc_enable, | 801 | .is_opt_ecc_enable = gp10b_fuse_is_opt_ecc_enable, |
802 | .is_opt_feature_override_disable = | 802 | .is_opt_feature_override_disable = |
803 | gp10b_fuse_is_opt_feature_override_disable, | 803 | gp10b_fuse_is_opt_feature_override_disable, |
804 | .fuse_status_opt_fbio = gm20b_fuse_status_opt_fbio, | ||
805 | .fuse_status_opt_fbp = gm20b_fuse_status_opt_fbp, | ||
806 | .fuse_status_opt_rop_l2_fbp = gm20b_fuse_status_opt_rop_l2_fbp, | ||
807 | .fuse_status_opt_tpc_gpc = gm20b_fuse_status_opt_tpc_gpc, | ||
808 | .fuse_ctrl_opt_tpc_gpc = gm20b_fuse_ctrl_opt_tpc_gpc, | ||
809 | .fuse_opt_sec_debug_en = gm20b_fuse_opt_sec_debug_en, | ||
810 | .fuse_opt_priv_sec_en = gm20b_fuse_opt_priv_sec_en, | ||
811 | .read_vin_cal_fuse_rev = NULL, | ||
812 | .read_vin_cal_slope_intercept_fuse = NULL, | ||
813 | .read_vin_cal_gain_offset_fuse = NULL, | ||
804 | }, | 814 | }, |
805 | .chip_init_gpu_characteristics = gv11b_init_gpu_characteristics, | 815 | .chip_init_gpu_characteristics = gv11b_init_gpu_characteristics, |
806 | .get_litter_value = gv11b_get_litter_value, | 816 | .get_litter_value = gv11b_get_litter_value, |
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c index b046ba6c..00efe316 100644 --- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c | |||
@@ -32,6 +32,8 @@ | |||
32 | #include "common/therm/therm_gp10b.h" | 32 | #include "common/therm/therm_gp10b.h" |
33 | #include "common/ltc/ltc_gm20b.h" | 33 | #include "common/ltc/ltc_gm20b.h" |
34 | #include "common/ltc/ltc_gp10b.h" | 34 | #include "common/ltc/ltc_gp10b.h" |
35 | #include "common/fuse/fuse_gm20b.h" | ||
36 | #include "common/fuse/fuse_gp10b.h" | ||
35 | 37 | ||
36 | #include "vgpu/fifo_vgpu.h" | 38 | #include "vgpu/fifo_vgpu.h" |
37 | #include "vgpu/gr_vgpu.h" | 39 | #include "vgpu/gr_vgpu.h" |
@@ -59,7 +61,6 @@ | |||
59 | #include "gp10b/gr_ctx_gp10b.h" | 61 | #include "gp10b/gr_ctx_gp10b.h" |
60 | #include "gp10b/fifo_gp10b.h" | 62 | #include "gp10b/fifo_gp10b.h" |
61 | #include "gp10b/regops_gp10b.h" | 63 | #include "gp10b/regops_gp10b.h" |
62 | #include "gp10b/fuse_gp10b.h" | ||
63 | 64 | ||
64 | #include "gm20b/gr_gm20b.h" | 65 | #include "gm20b/gr_gm20b.h" |
65 | #include "gm20b/fifo_gm20b.h" | 66 | #include "gm20b/fifo_gm20b.h" |
@@ -71,7 +72,6 @@ | |||
71 | #include <nvgpu/vgpu/vgpu.h> | 72 | #include <nvgpu/vgpu/vgpu.h> |
72 | #include <nvgpu/error_notifier.h> | 73 | #include <nvgpu/error_notifier.h> |
73 | 74 | ||
74 | #include <nvgpu/hw/gp10b/hw_fuse_gp10b.h> | ||
75 | #include <nvgpu/hw/gp10b/hw_fifo_gp10b.h> | 75 | #include <nvgpu/hw/gp10b/hw_fifo_gp10b.h> |
76 | #include <nvgpu/hw/gp10b/hw_ram_gp10b.h> | 76 | #include <nvgpu/hw/gp10b/hw_ram_gp10b.h> |
77 | #include <nvgpu/hw/gp10b/hw_top_gp10b.h> | 77 | #include <nvgpu/hw/gp10b/hw_top_gp10b.h> |
@@ -464,7 +464,7 @@ static const struct gpu_ops vgpu_gp10b_ops = { | |||
464 | .pmu_pg_init_param = gp10b_pg_gr_init, | 464 | .pmu_pg_init_param = gp10b_pg_gr_init, |
465 | .pmu_pg_supported_engines_list = gk20a_pmu_pg_engines_list, | 465 | .pmu_pg_supported_engines_list = gk20a_pmu_pg_engines_list, |
466 | .pmu_pg_engines_feature_list = gk20a_pmu_pg_feature_list, | 466 | .pmu_pg_engines_feature_list = gk20a_pmu_pg_feature_list, |
467 | .dump_secure_fuses = pmu_dump_security_fuses_gp10b, | 467 | .dump_secure_fuses = pmu_dump_security_fuses_gm20b, |
468 | .reset_engine = gk20a_pmu_engine_reset, | 468 | .reset_engine = gk20a_pmu_engine_reset, |
469 | .is_engine_in_reset = gk20a_pmu_is_engine_in_reset, | 469 | .is_engine_in_reset = gk20a_pmu_is_engine_in_reset, |
470 | }, | 470 | }, |
@@ -566,6 +566,16 @@ static const struct gpu_ops vgpu_gp10b_ops = { | |||
566 | .is_opt_ecc_enable = gp10b_fuse_is_opt_ecc_enable, | 566 | .is_opt_ecc_enable = gp10b_fuse_is_opt_ecc_enable, |
567 | .is_opt_feature_override_disable = | 567 | .is_opt_feature_override_disable = |
568 | gp10b_fuse_is_opt_feature_override_disable, | 568 | gp10b_fuse_is_opt_feature_override_disable, |
569 | .fuse_status_opt_fbio = gm20b_fuse_status_opt_fbio, | ||
570 | .fuse_status_opt_fbp = gm20b_fuse_status_opt_fbp, | ||
571 | .fuse_status_opt_rop_l2_fbp = gm20b_fuse_status_opt_rop_l2_fbp, | ||
572 | .fuse_status_opt_tpc_gpc = gm20b_fuse_status_opt_tpc_gpc, | ||
573 | .fuse_ctrl_opt_tpc_gpc = gm20b_fuse_ctrl_opt_tpc_gpc, | ||
574 | .fuse_opt_sec_debug_en = gm20b_fuse_opt_sec_debug_en, | ||
575 | .fuse_opt_priv_sec_en = gm20b_fuse_opt_priv_sec_en, | ||
576 | .read_vin_cal_fuse_rev = NULL, | ||
577 | .read_vin_cal_slope_intercept_fuse = NULL, | ||
578 | .read_vin_cal_gain_offset_fuse = NULL, | ||
569 | }, | 579 | }, |
570 | .chip_init_gpu_characteristics = vgpu_init_gpu_characteristics, | 580 | .chip_init_gpu_characteristics = vgpu_init_gpu_characteristics, |
571 | .get_litter_value = gp10b_get_litter_value, | 581 | .get_litter_value = gp10b_get_litter_value, |
diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c index f9d09ebd..204c0105 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | |||
@@ -35,6 +35,8 @@ | |||
35 | #include "common/ltc/ltc_gm20b.h" | 35 | #include "common/ltc/ltc_gm20b.h" |
36 | #include "common/ltc/ltc_gp10b.h" | 36 | #include "common/ltc/ltc_gp10b.h" |
37 | #include "common/ltc/ltc_gv11b.h" | 37 | #include "common/ltc/ltc_gv11b.h" |
38 | #include "common/fuse/fuse_gm20b.h" | ||
39 | #include "common/fuse/fuse_gp10b.h" | ||
38 | 40 | ||
39 | #include <gk20a/gk20a.h> | 41 | #include <gk20a/gk20a.h> |
40 | #include <gv11b/hal_gv11b.h> | 42 | #include <gv11b/hal_gv11b.h> |
@@ -68,7 +70,6 @@ | |||
68 | #include <gp10b/ce_gp10b.h> | 70 | #include <gp10b/ce_gp10b.h> |
69 | #include "gp10b/gr_gp10b.h" | 71 | #include "gp10b/gr_gp10b.h" |
70 | #include <gp10b/fifo_gp10b.h> | 72 | #include <gp10b/fifo_gp10b.h> |
71 | #include <gp10b/fuse_gp10b.h> | ||
72 | 73 | ||
73 | #include <gp106/pmu_gp106.h> | 74 | #include <gp106/pmu_gp106.h> |
74 | #include <gp106/acr_gp106.h> | 75 | #include <gp106/acr_gp106.h> |
@@ -91,7 +92,6 @@ | |||
91 | #include "vgpu_subctx_gv11b.h" | 92 | #include "vgpu_subctx_gv11b.h" |
92 | #include "vgpu_tsg_gv11b.h" | 93 | #include "vgpu_tsg_gv11b.h" |
93 | 94 | ||
94 | #include <nvgpu/hw/gv11b/hw_fuse_gv11b.h> | ||
95 | #include <nvgpu/hw/gv11b/hw_fifo_gv11b.h> | 95 | #include <nvgpu/hw/gv11b/hw_fifo_gv11b.h> |
96 | #include <nvgpu/hw/gv11b/hw_ram_gv11b.h> | 96 | #include <nvgpu/hw/gv11b/hw_ram_gv11b.h> |
97 | #include <nvgpu/hw/gv11b/hw_top_gv11b.h> | 97 | #include <nvgpu/hw/gv11b/hw_top_gv11b.h> |
@@ -530,7 +530,7 @@ static const struct gpu_ops vgpu_gv11b_ops = { | |||
530 | .pmu_pg_init_param = gv11b_pg_gr_init, | 530 | .pmu_pg_init_param = gv11b_pg_gr_init, |
531 | .pmu_pg_supported_engines_list = gk20a_pmu_pg_engines_list, | 531 | .pmu_pg_supported_engines_list = gk20a_pmu_pg_engines_list, |
532 | .pmu_pg_engines_feature_list = gk20a_pmu_pg_feature_list, | 532 | .pmu_pg_engines_feature_list = gk20a_pmu_pg_feature_list, |
533 | .dump_secure_fuses = pmu_dump_security_fuses_gp10b, | 533 | .dump_secure_fuses = pmu_dump_security_fuses_gm20b, |
534 | .reset_engine = gp106_pmu_engine_reset, | 534 | .reset_engine = gp106_pmu_engine_reset, |
535 | .is_engine_in_reset = gp106_pmu_is_engine_in_reset, | 535 | .is_engine_in_reset = gp106_pmu_is_engine_in_reset, |
536 | .pmu_nsbootstrap = gv11b_pmu_bootstrap, | 536 | .pmu_nsbootstrap = gv11b_pmu_bootstrap, |
@@ -635,6 +635,16 @@ static const struct gpu_ops vgpu_gv11b_ops = { | |||
635 | .is_opt_ecc_enable = gp10b_fuse_is_opt_ecc_enable, | 635 | .is_opt_ecc_enable = gp10b_fuse_is_opt_ecc_enable, |
636 | .is_opt_feature_override_disable = | 636 | .is_opt_feature_override_disable = |
637 | gp10b_fuse_is_opt_feature_override_disable, | 637 | gp10b_fuse_is_opt_feature_override_disable, |
638 | .fuse_status_opt_fbio = gm20b_fuse_status_opt_fbio, | ||
639 | .fuse_status_opt_fbp = gm20b_fuse_status_opt_fbp, | ||
640 | .fuse_status_opt_rop_l2_fbp = gm20b_fuse_status_opt_rop_l2_fbp, | ||
641 | .fuse_status_opt_tpc_gpc = gm20b_fuse_status_opt_tpc_gpc, | ||
642 | .fuse_ctrl_opt_tpc_gpc = gm20b_fuse_ctrl_opt_tpc_gpc, | ||
643 | .fuse_opt_sec_debug_en = gm20b_fuse_opt_sec_debug_en, | ||
644 | .fuse_opt_priv_sec_en = gm20b_fuse_opt_priv_sec_en, | ||
645 | .read_vin_cal_fuse_rev = NULL, | ||
646 | .read_vin_cal_slope_intercept_fuse = NULL, | ||
647 | .read_vin_cal_gain_offset_fuse = NULL, | ||
638 | }, | 648 | }, |
639 | .chip_init_gpu_characteristics = vgpu_gv11b_init_gpu_characteristics, | 649 | .chip_init_gpu_characteristics = vgpu_gv11b_init_gpu_characteristics, |
640 | .get_litter_value = gv11b_get_litter_value, | 650 | .get_litter_value = gv11b_get_litter_value, |
@@ -669,6 +679,7 @@ int vgpu_gv11b_init_hal(struct gk20a *g) | |||
669 | #endif | 679 | #endif |
670 | gops->falcon = vgpu_gv11b_ops.falcon; | 680 | gops->falcon = vgpu_gv11b_ops.falcon; |
671 | gops->priv_ring = vgpu_gv11b_ops.priv_ring; | 681 | gops->priv_ring = vgpu_gv11b_ops.priv_ring; |
682 | gops->fuse = vgpu_gv11b_ops.fuse; | ||
672 | 683 | ||
673 | /* Lone functions */ | 684 | /* Lone functions */ |
674 | gops->chip_init_gpu_characteristics = | 685 | gops->chip_init_gpu_characteristics = |