diff options
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c | 33 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/regops_gk20a.c | 39 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/regops_gm20b.c | 9 |
4 files changed, 50 insertions, 32 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c b/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c index 6af54e68..94486064 100644 --- a/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c | |||
@@ -686,39 +686,8 @@ static int nvgpu_dbg_gpu_ioctl_smpc_ctxsw_mode(struct dbg_session_gk20a *dbg_s, | |||
686 | "error (%d) during smpc ctxsw mode update\n", err); | 686 | "error (%d) during smpc ctxsw mode update\n", err); |
687 | goto clean_up; | 687 | goto clean_up; |
688 | } | 688 | } |
689 | /* The following regops are a hack/war to make up for the fact that we | ||
690 | * just scribbled into the ctxsw image w/o really knowing whether | ||
691 | * it was already swapped out in/out once or not, etc. | ||
692 | */ | ||
693 | { | ||
694 | struct nvgpu_dbg_gpu_reg_op ops[4]; | ||
695 | int i; | ||
696 | for (i = 0; i < ARRAY_SIZE(ops); i++) { | ||
697 | ops[i].op = NVGPU_DBG_GPU_REG_OP_WRITE_32; | ||
698 | ops[i].type = NVGPU_DBG_GPU_REG_OP_TYPE_GR_CTX; | ||
699 | ops[i].status = NVGPU_DBG_GPU_REG_OP_STATUS_SUCCESS; | ||
700 | ops[i].value_hi = 0; | ||
701 | ops[i].and_n_mask_lo = 0; | ||
702 | ops[i].and_n_mask_hi = 0; | ||
703 | } | ||
704 | /* gr_pri_gpcs_tpcs_sm_dsm_perf_counter_control_sel1_r();*/ | ||
705 | ops[0].offset = 0x00419e08; | ||
706 | ops[0].value_lo = 0x1d; | ||
707 | |||
708 | /* gr_pri_gpcs_tpcs_sm_dsm_perf_counter_control5_r(); */ | ||
709 | ops[1].offset = 0x00419e58; | ||
710 | ops[1].value_lo = 0x1; | ||
711 | 689 | ||
712 | /* gr_pri_gpcs_tpcs_sm_dsm_perf_counter_control3_r(); */ | 690 | err = g->ops.regops.apply_smpc_war(dbg_s); |
713 | ops[2].offset = 0x00419e68; | ||
714 | ops[2].value_lo = 0xaaaa; | ||
715 | |||
716 | /* gr_pri_gpcs_tpcs_sm_dsm_perf_counter4_control_r(); */ | ||
717 | ops[3].offset = 0x00419f40; | ||
718 | ops[3].value_lo = 0x18; | ||
719 | |||
720 | err = dbg_s->ops->exec_reg_ops(dbg_s, ops, ARRAY_SIZE(ops)); | ||
721 | } | ||
722 | 691 | ||
723 | clean_up: | 692 | clean_up: |
724 | mutex_unlock(&g->dbg_sessions_lock); | 693 | mutex_unlock(&g->dbg_sessions_lock); |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index a111a040..28d43081 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -335,6 +335,7 @@ struct gpu_ops { | |||
335 | const struct regop_offset_range* ( | 335 | const struct regop_offset_range* ( |
336 | *get_qctl_whitelist_ranges)(void); | 336 | *get_qctl_whitelist_ranges)(void); |
337 | int (*get_qctl_whitelist_ranges_count)(void); | 337 | int (*get_qctl_whitelist_ranges_count)(void); |
338 | int (*apply_smpc_war)(struct dbg_session_gk20a *dbg_s); | ||
338 | } regops; | 339 | } regops; |
339 | struct { | 340 | struct { |
340 | void (*intr_enable)(struct gk20a *g); | 341 | void (*intr_enable)(struct gk20a *g); |
diff --git a/drivers/gpu/nvgpu/gk20a/regops_gk20a.c b/drivers/gpu/nvgpu/gk20a/regops_gk20a.c index 7adb458b..d9984e03 100644 --- a/drivers/gpu/nvgpu/gk20a/regops_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/regops_gk20a.c | |||
@@ -757,6 +757,42 @@ int gk20a_get_qctl_whitelist_ranges_count(void) | |||
757 | return gk20a_qctl_whitelist_ranges_count; | 757 | return gk20a_qctl_whitelist_ranges_count; |
758 | } | 758 | } |
759 | 759 | ||
760 | int gk20a_apply_smpc_war(struct dbg_session_gk20a *dbg_s) | ||
761 | { | ||
762 | /* The following regops are a hack/war to make up for the fact that we | ||
763 | * just scribbled into the ctxsw image w/o really knowing whether | ||
764 | * it was already swapped out in/out once or not, etc. | ||
765 | */ | ||
766 | struct nvgpu_dbg_gpu_reg_op ops[4]; | ||
767 | int i; | ||
768 | for (i = 0; i < ARRAY_SIZE(ops); i++) { | ||
769 | ops[i].op = REGOP(WRITE_32); | ||
770 | ops[i].type = REGOP(TYPE_GR_CTX); | ||
771 | ops[i].status = REGOP(STATUS_SUCCESS); | ||
772 | ops[i].value_hi = 0; | ||
773 | ops[i].and_n_mask_lo = 0; | ||
774 | ops[i].and_n_mask_hi = 0; | ||
775 | } | ||
776 | |||
777 | /* gr_pri_gpcs_tpcs_sm_dsm_perf_counter_control_sel1_r();*/ | ||
778 | ops[0].offset = 0x00419e08; | ||
779 | ops[0].value_lo = 0x1d; | ||
780 | |||
781 | /* gr_pri_gpcs_tpcs_sm_dsm_perf_counter_control5_r(); */ | ||
782 | ops[1].offset = 0x00419e58; | ||
783 | ops[1].value_lo = 0x1; | ||
784 | |||
785 | /* gr_pri_gpcs_tpcs_sm_dsm_perf_counter_control3_r(); */ | ||
786 | ops[2].offset = 0x00419e68; | ||
787 | ops[2].value_lo = 0xaaaa; | ||
788 | |||
789 | /* gr_pri_gpcs_tpcs_sm_dsm_perf_counter4_control_r(); */ | ||
790 | ops[3].offset = 0x00419f40; | ||
791 | ops[3].value_lo = 0x18; | ||
792 | |||
793 | return dbg_s->ops->exec_reg_ops(dbg_s, ops, ARRAY_SIZE(ops)); | ||
794 | } | ||
795 | |||
760 | void gk20a_init_regops(struct gpu_ops *gops) | 796 | void gk20a_init_regops(struct gpu_ops *gops) |
761 | { | 797 | { |
762 | gops->regops.get_global_whitelist_ranges = | 798 | gops->regops.get_global_whitelist_ranges = |
@@ -788,4 +824,7 @@ void gk20a_init_regops(struct gpu_ops *gops) | |||
788 | gk20a_get_qctl_whitelist_ranges; | 824 | gk20a_get_qctl_whitelist_ranges; |
789 | gops->regops.get_qctl_whitelist_ranges_count = | 825 | gops->regops.get_qctl_whitelist_ranges_count = |
790 | gk20a_get_qctl_whitelist_ranges_count; | 826 | gk20a_get_qctl_whitelist_ranges_count; |
827 | |||
828 | gops->regops.apply_smpc_war = | ||
829 | gk20a_apply_smpc_war; | ||
791 | } | 830 | } |
diff --git a/drivers/gpu/nvgpu/gm20b/regops_gm20b.c b/drivers/gpu/nvgpu/gm20b/regops_gm20b.c index b7cc0aaa..71ccda37 100644 --- a/drivers/gpu/nvgpu/gm20b/regops_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/regops_gm20b.c | |||
@@ -494,6 +494,12 @@ int gm20b_get_qctl_whitelist_ranges_count(void) | |||
494 | return gm20b_qctl_whitelist_ranges_count; | 494 | return gm20b_qctl_whitelist_ranges_count; |
495 | } | 495 | } |
496 | 496 | ||
497 | int gm20b_apply_smpc_war(struct dbg_session_gk20a *dbg_s) | ||
498 | { | ||
499 | /* Not needed on gm20b */ | ||
500 | return 0; | ||
501 | } | ||
502 | |||
497 | void gm20b_init_regops(struct gpu_ops *gops) | 503 | void gm20b_init_regops(struct gpu_ops *gops) |
498 | { | 504 | { |
499 | gops->regops.get_global_whitelist_ranges = | 505 | gops->regops.get_global_whitelist_ranges = |
@@ -525,4 +531,7 @@ void gm20b_init_regops(struct gpu_ops *gops) | |||
525 | gm20b_get_qctl_whitelist_ranges; | 531 | gm20b_get_qctl_whitelist_ranges; |
526 | gops->regops.get_qctl_whitelist_ranges_count = | 532 | gops->regops.get_qctl_whitelist_ranges_count = |
527 | gm20b_get_qctl_whitelist_ranges_count; | 533 | gm20b_get_qctl_whitelist_ranges_count; |
534 | |||
535 | gops->regops.apply_smpc_war = | ||
536 | gm20b_apply_smpc_war; | ||
528 | } | 537 | } |