diff options
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/common/falcon/falcon.c | 26 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/flcn_gk20a.c | 32 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/falcon.h | 36 |
3 files changed, 94 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/common/falcon/falcon.c b/drivers/gpu/nvgpu/common/falcon/falcon.c index 99b2c249..d8420ece 100644 --- a/drivers/gpu/nvgpu/common/falcon/falcon.c +++ b/drivers/gpu/nvgpu/common/falcon/falcon.c | |||
@@ -286,6 +286,32 @@ int nvgpu_flcn_bootstrap(struct nvgpu_falcon *flcn, u32 boot_vector) | |||
286 | return status; | 286 | return status; |
287 | } | 287 | } |
288 | 288 | ||
289 | u32 nvgpu_flcn_mailbox_read(struct nvgpu_falcon *flcn, u32 mailbox_index) | ||
290 | { | ||
291 | struct nvgpu_falcon_ops *flcn_ops = &flcn->flcn_ops; | ||
292 | u32 data = 0; | ||
293 | |||
294 | if (flcn_ops->mailbox_read) | ||
295 | data = flcn_ops->mailbox_read(flcn, mailbox_index); | ||
296 | else | ||
297 | nvgpu_warn(flcn->g, "Invalid op on falcon 0x%x ", | ||
298 | flcn->flcn_id); | ||
299 | |||
300 | return data; | ||
301 | } | ||
302 | |||
303 | void nvgpu_flcn_mailbox_write(struct nvgpu_falcon *flcn, u32 mailbox_index, | ||
304 | u32 data) | ||
305 | { | ||
306 | struct nvgpu_falcon_ops *flcn_ops = &flcn->flcn_ops; | ||
307 | |||
308 | if (flcn_ops->mailbox_write) | ||
309 | flcn_ops->mailbox_write(flcn, mailbox_index, data); | ||
310 | else | ||
311 | nvgpu_warn(flcn->g, "Invalid op on falcon 0x%x ", | ||
312 | flcn->flcn_id); | ||
313 | } | ||
314 | |||
289 | void nvgpu_flcn_dump_stats(struct nvgpu_falcon *flcn) | 315 | void nvgpu_flcn_dump_stats(struct nvgpu_falcon *flcn) |
290 | { | 316 | { |
291 | struct nvgpu_falcon_ops *flcn_ops = &flcn->flcn_ops; | 317 | struct nvgpu_falcon_ops *flcn_ops = &flcn->flcn_ops; |
diff --git a/drivers/gpu/nvgpu/gk20a/flcn_gk20a.c b/drivers/gpu/nvgpu/gk20a/flcn_gk20a.c index 8d459903..83850a19 100644 --- a/drivers/gpu/nvgpu/gk20a/flcn_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/flcn_gk20a.c | |||
@@ -402,6 +402,36 @@ static int gk20a_falcon_bootstrap(struct nvgpu_falcon *flcn, | |||
402 | return 0; | 402 | return 0; |
403 | } | 403 | } |
404 | 404 | ||
405 | static u32 gk20a_falcon_mailbox_read(struct nvgpu_falcon *flcn, | ||
406 | u32 mailbox_index) | ||
407 | { | ||
408 | struct gk20a *g = flcn->g; | ||
409 | u32 data = 0; | ||
410 | |||
411 | if (mailbox_index < FALCON_MAILBOX_COUNT) | ||
412 | data = gk20a_readl(g, flcn->flcn_base + (mailbox_index ? | ||
413 | falcon_falcon_mailbox1_r() : | ||
414 | falcon_falcon_mailbox0_r())); | ||
415 | else | ||
416 | nvgpu_err(g, "incorrect mailbox id %d", mailbox_index); | ||
417 | |||
418 | return data; | ||
419 | } | ||
420 | |||
421 | static void gk20a_falcon_mailbox_write(struct nvgpu_falcon *flcn, | ||
422 | u32 mailbox_index, u32 data) | ||
423 | { | ||
424 | struct gk20a *g = flcn->g; | ||
425 | |||
426 | if (mailbox_index < FALCON_MAILBOX_COUNT) | ||
427 | gk20a_writel(g, flcn->flcn_base + (mailbox_index ? | ||
428 | falcon_falcon_mailbox1_r() : | ||
429 | falcon_falcon_mailbox0_r()), | ||
430 | data); | ||
431 | else | ||
432 | nvgpu_err(g, "incorrect mailbox id %d", mailbox_index); | ||
433 | } | ||
434 | |||
405 | static void gk20a_falcon_dump_imblk(struct nvgpu_falcon *flcn) | 435 | static void gk20a_falcon_dump_imblk(struct nvgpu_falcon *flcn) |
406 | { | 436 | { |
407 | struct gk20a *g = flcn->g; | 437 | struct gk20a *g = flcn->g; |
@@ -612,6 +642,8 @@ void gk20a_falcon_ops(struct nvgpu_falcon *flcn) | |||
612 | flcn_ops->copy_from_imem = gk20a_flcn_copy_from_imem; | 642 | flcn_ops->copy_from_imem = gk20a_flcn_copy_from_imem; |
613 | flcn_ops->bootstrap = gk20a_falcon_bootstrap; | 643 | flcn_ops->bootstrap = gk20a_falcon_bootstrap; |
614 | flcn_ops->dump_falcon_stats = gk20a_falcon_dump_stats; | 644 | flcn_ops->dump_falcon_stats = gk20a_falcon_dump_stats; |
645 | flcn_ops->mailbox_read = gk20a_falcon_mailbox_read; | ||
646 | flcn_ops->mailbox_write = gk20a_falcon_mailbox_write; | ||
615 | 647 | ||
616 | gk20a_falcon_engine_dependency_ops(flcn); | 648 | gk20a_falcon_engine_dependency_ops(flcn); |
617 | } | 649 | } |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/falcon.h b/drivers/gpu/nvgpu/include/nvgpu/falcon.h index 888d8e70..4be16576 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/falcon.h +++ b/drivers/gpu/nvgpu/include/nvgpu/falcon.h | |||
@@ -79,6 +79,15 @@ | |||
79 | #define FALCON_REG_RSVD2 (31) | 79 | #define FALCON_REG_RSVD2 (31) |
80 | #define FALCON_REG_SIZE (32) | 80 | #define FALCON_REG_SIZE (32) |
81 | 81 | ||
82 | #define FALCON_MAILBOX_COUNT 0x02 | ||
83 | #define FALCON_BLOCK_SIZE 0x100 | ||
84 | |||
85 | #define GET_IMEM_TAG(IMEM_ADDR) (IMEM_ADDR >> 8) | ||
86 | |||
87 | #define GET_NEXT_BLOCK(ADDR) \ | ||
88 | ((((ADDR + (FALCON_BLOCK_SIZE - 1)) & ~(FALCON_BLOCK_SIZE-1)) \ | ||
89 | / FALCON_BLOCK_SIZE) << 8) | ||
90 | |||
82 | /* | 91 | /* |
83 | * Falcon HWCFG request read types defines | 92 | * Falcon HWCFG request read types defines |
84 | */ | 93 | */ |
@@ -113,6 +122,33 @@ enum flcn_mem_type { | |||
113 | MEM_IMEM | 122 | MEM_IMEM |
114 | }; | 123 | }; |
115 | 124 | ||
125 | /* Falcon ucode header format | ||
126 | * OS Code Offset | ||
127 | * OS Code Size | ||
128 | * OS Data Offset | ||
129 | * OS Data Size | ||
130 | * NumApps (N) | ||
131 | * App 0 Code Offset | ||
132 | * App 0 Code Size | ||
133 | * . . . . | ||
134 | * App N - 1 Code Offset | ||
135 | * App N - 1 Code Size | ||
136 | * App 0 Data Offset | ||
137 | * App 0 Data Size | ||
138 | * . . . . | ||
139 | * App N - 1 Data Offset | ||
140 | * App N - 1 Data Size | ||
141 | * OS Ovl Offset | ||
142 | * OS Ovl Size | ||
143 | */ | ||
144 | #define OS_CODE_OFFSET 0x0 | ||
145 | #define OS_CODE_SIZE 0x1 | ||
146 | #define OS_DATA_OFFSET 0x2 | ||
147 | #define OS_DATA_SIZE 0x3 | ||
148 | #define NUM_APPS 0x4 | ||
149 | #define APP_0_CODE_OFFSET 0x5 | ||
150 | #define APP_0_CODE_SIZE 0x6 | ||
151 | |||
116 | struct nvgpu_falcon_dma_info { | 152 | struct nvgpu_falcon_dma_info { |
117 | u32 fb_base; | 153 | u32 fb_base; |
118 | u32 fb_off; | 154 | u32 fb_off; |