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-rw-r--r--drivers/gpu/nvgpu/gk20a/gr_gk20a.c10
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index 263d8bac..faecb815 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -6586,12 +6586,22 @@ static int gr_gk20a_ctx_patch_smpc(struct gk20a *g,
6586 ctxsw_prog_main_image_patch_count_o(), 6586 ctxsw_prog_main_image_patch_count_o(),
6587 ch_ctx->patch_ctx.data_count); 6587 ch_ctx->patch_ctx.data_count);
6588 if (ctxheader->gpu_va) { 6588 if (ctxheader->gpu_va) {
6589 /*
6590 * Main context can be gr_ctx or pm_ctx.
6591 * CPU access for relevant ctx is taken
6592 * care of in the calling function
6593 * __gr_gk20a_exec_ctx_ops. Need to take
6594 * care of cpu access to ctxheader here.
6595 */
6596 if (nvgpu_mem_begin(g, ctxheader))
6597 return -ENOMEM;
6589 nvgpu_mem_wr(g, ctxheader, 6598 nvgpu_mem_wr(g, ctxheader,
6590 ctxsw_prog_main_image_patch_adr_lo_o(), 6599 ctxsw_prog_main_image_patch_adr_lo_o(),
6591 vaddr_lo); 6600 vaddr_lo);
6592 nvgpu_mem_wr(g, ctxheader, 6601 nvgpu_mem_wr(g, ctxheader,
6593 ctxsw_prog_main_image_patch_adr_hi_o(), 6602 ctxsw_prog_main_image_patch_adr_hi_o(),
6594 vaddr_hi); 6603 vaddr_hi);
6604 nvgpu_mem_end(g, ctxheader);
6595 } else { 6605 } else {
6596 nvgpu_mem_wr(g, mem, 6606 nvgpu_mem_wr(g, mem,
6597 ctxsw_prog_main_image_patch_adr_lo_o(), 6607 ctxsw_prog_main_image_patch_adr_lo_o(),