diff options
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 88 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h | 16 |
3 files changed, 108 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 1bbf09ec..bb9def35 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | |||
@@ -29,6 +29,7 @@ | |||
29 | #include <nvgpu/hw/gv11b/hw_usermode_gv11b.h> | 29 | #include <nvgpu/hw/gv11b/hw_usermode_gv11b.h> |
30 | #include <nvgpu/hw/gv11b/hw_top_gv11b.h> | 30 | #include <nvgpu/hw/gv11b/hw_top_gv11b.h> |
31 | #include <nvgpu/hw/gv11b/hw_gmmu_gv11b.h> | 31 | #include <nvgpu/hw/gv11b/hw_gmmu_gv11b.h> |
32 | #include <nvgpu/hw/gv11b/hw_mc_gv11b.h> | ||
32 | 33 | ||
33 | #include "fifo_gv11b.h" | 34 | #include "fifo_gv11b.h" |
34 | #include "subctx_gv11b.h" | 35 | #include "subctx_gv11b.h" |
@@ -684,6 +685,92 @@ static void gv11b_fifo_init_pbdma_intr_descs(struct fifo_gk20a *f) | |||
684 | pbdma_intr_0_device_pending_f(); | 685 | pbdma_intr_0_device_pending_f(); |
685 | } | 686 | } |
686 | 687 | ||
688 | static u32 gv11b_fifo_intr_0_en_mask(struct gk20a *g) | ||
689 | { | ||
690 | u32 intr_0_en_mask; | ||
691 | |||
692 | intr_0_en_mask = g->ops.fifo.intr_0_error_mask(g); | ||
693 | |||
694 | intr_0_en_mask |= fifo_intr_0_runlist_event_pending_f() | | ||
695 | fifo_intr_0_pbdma_intr_pending_f(); | ||
696 | |||
697 | return intr_0_en_mask; | ||
698 | } | ||
699 | |||
700 | int gv11b_init_fifo_reset_enable_hw(struct gk20a *g) | ||
701 | { | ||
702 | u32 intr_stall; | ||
703 | u32 mask; | ||
704 | u32 timeout; | ||
705 | unsigned int i; | ||
706 | u32 host_num_pbdma = nvgpu_get_litter_value(g, GPU_LIT_HOST_NUM_PBDMA); | ||
707 | |||
708 | gk20a_dbg_fn(""); | ||
709 | |||
710 | /* enable pmc pfifo */ | ||
711 | g->ops.mc.reset(g, mc_enable_pfifo_enabled_f()); | ||
712 | |||
713 | if (g->ops.clock_gating.slcg_ce2_load_gating_prod) | ||
714 | g->ops.clock_gating.slcg_ce2_load_gating_prod(g, | ||
715 | g->slcg_enabled); | ||
716 | if (g->ops.clock_gating.slcg_fifo_load_gating_prod) | ||
717 | g->ops.clock_gating.slcg_fifo_load_gating_prod(g, | ||
718 | g->slcg_enabled); | ||
719 | if (g->ops.clock_gating.blcg_fifo_load_gating_prod) | ||
720 | g->ops.clock_gating.blcg_fifo_load_gating_prod(g, | ||
721 | g->blcg_enabled); | ||
722 | |||
723 | /* enable pbdma */ | ||
724 | mask = 0; | ||
725 | for (i = 0; i < host_num_pbdma; ++i) | ||
726 | mask |= mc_enable_pb_sel_f(mc_enable_pb_0_enabled_v(), i); | ||
727 | gk20a_writel(g, mc_enable_pb_r(), mask); | ||
728 | |||
729 | |||
730 | timeout = gk20a_readl(g, fifo_fb_timeout_r()); | ||
731 | timeout = set_field(timeout, fifo_fb_timeout_period_m(), | ||
732 | fifo_fb_timeout_period_init_f()); | ||
733 | gk20a_dbg_info("fifo_fb_timeout reg val = 0x%08x", timeout); | ||
734 | gk20a_writel(g, fifo_fb_timeout_r(), timeout); | ||
735 | |||
736 | /* write pbdma timeout value */ | ||
737 | for (i = 0; i < host_num_pbdma; i++) { | ||
738 | timeout = gk20a_readl(g, pbdma_timeout_r(i)); | ||
739 | timeout = set_field(timeout, pbdma_timeout_period_m(), | ||
740 | pbdma_timeout_period_init_f()); | ||
741 | gk20a_dbg_info("pbdma_timeout reg val = 0x%08x", timeout); | ||
742 | gk20a_writel(g, pbdma_timeout_r(i), timeout); | ||
743 | } | ||
744 | /* clear and enable pbdma interrupt */ | ||
745 | for (i = 0; i < host_num_pbdma; i++) { | ||
746 | gk20a_writel(g, pbdma_intr_0_r(i), 0xFFFFFFFF); | ||
747 | gk20a_writel(g, pbdma_intr_1_r(i), 0xFFFFFFFF); | ||
748 | |||
749 | intr_stall = gk20a_readl(g, pbdma_intr_stall_r(i)); | ||
750 | gk20a_dbg_info("pbdma id:%u, intr_en_0 0x%08x", i, intr_stall); | ||
751 | gk20a_writel(g, pbdma_intr_en_0_r(i), intr_stall); | ||
752 | |||
753 | intr_stall = gk20a_readl(g, pbdma_intr_stall_1_r(i)); | ||
754 | gk20a_dbg_info("pbdma id:%u, intr_en_1 0x%08x", i, intr_stall); | ||
755 | gk20a_writel(g, pbdma_intr_en_1_r(i), intr_stall); | ||
756 | } | ||
757 | |||
758 | /* clear runlist interrupts */ | ||
759 | gk20a_writel(g, fifo_intr_runlist_r(), ~0); | ||
760 | |||
761 | /* clear and enable pfifo interrupt */ | ||
762 | gk20a_writel(g, fifo_intr_0_r(), 0xFFFFFFFF); | ||
763 | mask = gv11b_fifo_intr_0_en_mask(g); | ||
764 | gk20a_dbg_info("fifo_intr_en_0 0x%08x", mask); | ||
765 | gk20a_writel(g, fifo_intr_en_0_r(), mask); | ||
766 | gk20a_dbg_info("fifo_intr_en_1 = 0x80000000"); | ||
767 | gk20a_writel(g, fifo_intr_en_1_r(), 0x80000000); | ||
768 | |||
769 | gk20a_dbg_fn("done"); | ||
770 | |||
771 | return 0; | ||
772 | } | ||
773 | |||
687 | void gv11b_init_fifo(struct gpu_ops *gops) | 774 | void gv11b_init_fifo(struct gpu_ops *gops) |
688 | { | 775 | { |
689 | gp10b_init_fifo(gops); | 776 | gp10b_init_fifo(gops); |
@@ -712,4 +799,5 @@ void gv11b_init_fifo(struct gpu_ops *gops) | |||
712 | gops->fifo.is_preempt_pending = gv11b_fifo_is_preempt_pending; | 799 | gops->fifo.is_preempt_pending = gv11b_fifo_is_preempt_pending; |
713 | gops->fifo.preempt_ch_tsg = gv11b_fifo_preempt_ch_tsg; | 800 | gops->fifo.preempt_ch_tsg = gv11b_fifo_preempt_ch_tsg; |
714 | gops->fifo.init_pbdma_intr_descs = gv11b_fifo_init_pbdma_intr_descs; | 801 | gops->fifo.init_pbdma_intr_descs = gv11b_fifo_init_pbdma_intr_descs; |
802 | gops->fifo.reset_enable_hw = gv11b_init_fifo_reset_enable_hw; | ||
715 | } | 803 | } |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h index 911efa43..b9249128 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h | |||
@@ -298,6 +298,10 @@ static inline u32 fifo_fb_timeout_period_max_f(void) | |||
298 | { | 298 | { |
299 | return 0x3fffffff; | 299 | return 0x3fffffff; |
300 | } | 300 | } |
301 | static inline u32 fifo_fb_timeout_period_init_f(void) | ||
302 | { | ||
303 | return 0x3c00; | ||
304 | } | ||
301 | static inline u32 fifo_sched_disable_r(void) | 305 | static inline u32 fifo_sched_disable_r(void) |
302 | { | 306 | { |
303 | return 0x00002630; | 307 | return 0x00002630; |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h index 9c2ba7c6..ed63cebc 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h | |||
@@ -618,4 +618,20 @@ static inline u32 pbdma_set_channel_info_veid_f(u32 v) | |||
618 | { | 618 | { |
619 | return (v & 0x3f) << 8; | 619 | return (v & 0x3f) << 8; |
620 | } | 620 | } |
621 | static inline u32 pbdma_timeout_r(u32 i) | ||
622 | { | ||
623 | return 0x0004012c + i*8192; | ||
624 | } | ||
625 | static inline u32 pbdma_timeout_period_m(void) | ||
626 | { | ||
627 | return 0xffffffff << 0; | ||
628 | } | ||
629 | static inline u32 pbdma_timeout_period_max_f(void) | ||
630 | { | ||
631 | return 0xffffffff; | ||
632 | } | ||
633 | static inline u32 pbdma_timeout_period_init_f(void) | ||
634 | { | ||
635 | return 0x10000; | ||
636 | } | ||
621 | #endif | 637 | #endif |