diff options
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/common/fifo/channel.c | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | 50 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fifo_gk20a.h | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 11 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/fifo_gv11b.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/gk20a.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/fifo_vgpu.c | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/fifo_vgpu.h | 2 |
8 files changed, 38 insertions, 43 deletions
diff --git a/drivers/gpu/nvgpu/common/fifo/channel.c b/drivers/gpu/nvgpu/common/fifo/channel.c index 6ac8e508..29720886 100644 --- a/drivers/gpu/nvgpu/common/fifo/channel.c +++ b/drivers/gpu/nvgpu/common/fifo/channel.c | |||
@@ -227,8 +227,8 @@ void gk20a_channel_abort(struct channel_gk20a *ch, bool channel_preempt) | |||
227 | 227 | ||
228 | ch->g->ops.fifo.disable_channel(ch); | 228 | ch->g->ops.fifo.disable_channel(ch); |
229 | 229 | ||
230 | if (channel_preempt && gk20a_is_channel_marked_as_tsg(ch)) { | 230 | if (channel_preempt) { |
231 | ch->g->ops.fifo.preempt_channel(ch->g, ch->chid); | 231 | ch->g->ops.fifo.preempt_channel(ch->g, ch); |
232 | } | 232 | } |
233 | 233 | ||
234 | if (ch->g->ops.fifo.ch_abort_clean_up) { | 234 | if (ch->g->ops.fifo.ch_abort_clean_up) { |
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index 382744c7..06db0bb0 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | |||
@@ -2912,19 +2912,14 @@ void gk20a_fifo_preempt_timeout_rc_tsg(struct gk20a *g, struct tsg_gk20a *tsg) | |||
2912 | gk20a_fifo_recover_tsg(g, tsg, true, RC_TYPE_PREEMPT_TIMEOUT); | 2912 | gk20a_fifo_recover_tsg(g, tsg, true, RC_TYPE_PREEMPT_TIMEOUT); |
2913 | } | 2913 | } |
2914 | 2914 | ||
2915 | void gk20a_fifo_preempt_timeout_rc(struct gk20a *g, u32 chid) | 2915 | void gk20a_fifo_preempt_timeout_rc(struct gk20a *g, struct channel_gk20a *ch) |
2916 | { | 2916 | { |
2917 | struct channel_gk20a *ch = gk20a_channel_from_id(g, chid); | 2917 | nvgpu_err(g, "preempt channel %d timeout", ch->chid); |
2918 | 2918 | ||
2919 | nvgpu_err(g, "preempt channel %d timeout", chid); | 2919 | g->ops.fifo.set_error_notifier(ch, |
2920 | |||
2921 | if (ch != NULL) { | ||
2922 | g->ops.fifo.set_error_notifier(ch, | ||
2923 | NVGPU_ERR_NOTIFIER_FIFO_ERROR_IDLE_TIMEOUT); | 2920 | NVGPU_ERR_NOTIFIER_FIFO_ERROR_IDLE_TIMEOUT); |
2924 | gk20a_fifo_recover_ch(g, ch, true, | 2921 | gk20a_fifo_recover_ch(g, ch, true, |
2925 | RC_TYPE_PREEMPT_TIMEOUT); | 2922 | RC_TYPE_PREEMPT_TIMEOUT); |
2926 | gk20a_channel_put(ch); | ||
2927 | } | ||
2928 | } | 2923 | } |
2929 | 2924 | ||
2930 | int __locked_fifo_preempt(struct gk20a *g, u32 id, bool is_tsg) | 2925 | int __locked_fifo_preempt(struct gk20a *g, u32 id, bool is_tsg) |
@@ -2945,7 +2940,7 @@ int __locked_fifo_preempt(struct gk20a *g, u32 id, bool is_tsg) | |||
2945 | return ret; | 2940 | return ret; |
2946 | } | 2941 | } |
2947 | 2942 | ||
2948 | int gk20a_fifo_preempt_channel(struct gk20a *g, u32 chid) | 2943 | int gk20a_fifo_preempt_channel(struct gk20a *g, struct channel_gk20a *ch) |
2949 | { | 2944 | { |
2950 | struct fifo_gk20a *f = &g->fifo; | 2945 | struct fifo_gk20a *f = &g->fifo; |
2951 | u32 ret = 0; | 2946 | u32 ret = 0; |
@@ -2953,10 +2948,7 @@ int gk20a_fifo_preempt_channel(struct gk20a *g, u32 chid) | |||
2953 | u32 mutex_ret = 0; | 2948 | u32 mutex_ret = 0; |
2954 | u32 i; | 2949 | u32 i; |
2955 | 2950 | ||
2956 | nvgpu_log_fn(g, "chid: %d", chid); | 2951 | nvgpu_log_fn(g, "chid: %d", ch->chid); |
2957 | if (chid == FIFO_INVAL_CHANNEL_ID) { | ||
2958 | return 0; | ||
2959 | } | ||
2960 | 2952 | ||
2961 | /* we have no idea which runlist we are using. lock all */ | 2953 | /* we have no idea which runlist we are using. lock all */ |
2962 | for (i = 0; i < g->fifo.max_runlists; i++) { | 2954 | for (i = 0; i < g->fifo.max_runlists; i++) { |
@@ -2965,7 +2957,7 @@ int gk20a_fifo_preempt_channel(struct gk20a *g, u32 chid) | |||
2965 | 2957 | ||
2966 | mutex_ret = nvgpu_pmu_mutex_acquire(&g->pmu, PMU_MUTEX_ID_FIFO, &token); | 2958 | mutex_ret = nvgpu_pmu_mutex_acquire(&g->pmu, PMU_MUTEX_ID_FIFO, &token); |
2967 | 2959 | ||
2968 | ret = __locked_fifo_preempt(g, chid, false); | 2960 | ret = __locked_fifo_preempt(g, ch->chid, false); |
2969 | 2961 | ||
2970 | if (!mutex_ret) { | 2962 | if (!mutex_ret) { |
2971 | nvgpu_pmu_mutex_release(&g->pmu, PMU_MUTEX_ID_FIFO, &token); | 2963 | nvgpu_pmu_mutex_release(&g->pmu, PMU_MUTEX_ID_FIFO, &token); |
@@ -2978,9 +2970,10 @@ int gk20a_fifo_preempt_channel(struct gk20a *g, u32 chid) | |||
2978 | if (ret) { | 2970 | if (ret) { |
2979 | if (nvgpu_platform_is_silicon(g)) { | 2971 | if (nvgpu_platform_is_silicon(g)) { |
2980 | nvgpu_err(g, "preempt timed out for chid: %u, " | 2972 | nvgpu_err(g, "preempt timed out for chid: %u, " |
2981 | "ctxsw timeout will trigger recovery if needed", chid); | 2973 | "ctxsw timeout will trigger recovery if needed", |
2974 | ch->chid); | ||
2982 | } else { | 2975 | } else { |
2983 | gk20a_fifo_preempt_timeout_rc(g, chid); | 2976 | gk20a_fifo_preempt_timeout_rc(g, ch); |
2984 | } | 2977 | } |
2985 | } | 2978 | } |
2986 | 2979 | ||
@@ -3035,7 +3028,7 @@ int gk20a_fifo_preempt(struct gk20a *g, struct channel_gk20a *ch) | |||
3035 | if (tsg != NULL) { | 3028 | if (tsg != NULL) { |
3036 | err = g->ops.fifo.preempt_tsg(ch->g, tsg); | 3029 | err = g->ops.fifo.preempt_tsg(ch->g, tsg); |
3037 | } else { | 3030 | } else { |
3038 | err = g->ops.fifo.preempt_channel(ch->g, ch->chid); | 3031 | err = g->ops.fifo.preempt_channel(ch->g, ch); |
3039 | } | 3032 | } |
3040 | 3033 | ||
3041 | return err; | 3034 | return err; |
@@ -3126,8 +3119,9 @@ int gk20a_fifo_disable_engine_activity(struct gk20a *g, | |||
3126 | u32 pbdma_chid = FIFO_INVAL_CHANNEL_ID; | 3119 | u32 pbdma_chid = FIFO_INVAL_CHANNEL_ID; |
3127 | u32 engine_chid = FIFO_INVAL_CHANNEL_ID; | 3120 | u32 engine_chid = FIFO_INVAL_CHANNEL_ID; |
3128 | u32 token = PMU_INVALID_MUTEX_OWNER_ID; | 3121 | u32 token = PMU_INVALID_MUTEX_OWNER_ID; |
3129 | u32 mutex_ret; | 3122 | int mutex_ret; |
3130 | u32 err = 0; | 3123 | struct channel_gk20a *ch = NULL; |
3124 | int err = 0; | ||
3131 | 3125 | ||
3132 | nvgpu_log_fn(g, " "); | 3126 | nvgpu_log_fn(g, " "); |
3133 | 3127 | ||
@@ -3155,8 +3149,12 @@ int gk20a_fifo_disable_engine_activity(struct gk20a *g, | |||
3155 | } | 3149 | } |
3156 | 3150 | ||
3157 | if (pbdma_chid != FIFO_INVAL_CHANNEL_ID) { | 3151 | if (pbdma_chid != FIFO_INVAL_CHANNEL_ID) { |
3158 | err = g->ops.fifo.preempt_channel(g, pbdma_chid); | 3152 | ch = gk20a_channel_from_id(g, pbdma_chid); |
3159 | if (err) { | 3153 | if (ch != NULL) { |
3154 | err = g->ops.fifo.preempt_channel(g, ch); | ||
3155 | gk20a_channel_put(ch); | ||
3156 | } | ||
3157 | if (err != 0) { | ||
3160 | goto clean_up; | 3158 | goto clean_up; |
3161 | } | 3159 | } |
3162 | } | 3160 | } |
@@ -3173,8 +3171,12 @@ int gk20a_fifo_disable_engine_activity(struct gk20a *g, | |||
3173 | } | 3171 | } |
3174 | 3172 | ||
3175 | if (engine_chid != FIFO_INVAL_ENGINE_ID && engine_chid != pbdma_chid) { | 3173 | if (engine_chid != FIFO_INVAL_ENGINE_ID && engine_chid != pbdma_chid) { |
3176 | err = g->ops.fifo.preempt_channel(g, engine_chid); | 3174 | ch = gk20a_channel_from_id(g, engine_chid); |
3177 | if (err) { | 3175 | if (ch != NULL) { |
3176 | err = g->ops.fifo.preempt_channel(g, ch); | ||
3177 | gk20a_channel_put(ch); | ||
3178 | } | ||
3179 | if (err != 0) { | ||
3178 | goto clean_up; | 3180 | goto clean_up; |
3179 | } | 3181 | } |
3180 | } | 3182 | } |
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h index 330929f6..29c2f889 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h | |||
@@ -230,7 +230,7 @@ int gk20a_init_fifo_setup_hw(struct gk20a *g); | |||
230 | void gk20a_fifo_isr(struct gk20a *g); | 230 | void gk20a_fifo_isr(struct gk20a *g); |
231 | u32 gk20a_fifo_nonstall_isr(struct gk20a *g); | 231 | u32 gk20a_fifo_nonstall_isr(struct gk20a *g); |
232 | 232 | ||
233 | int gk20a_fifo_preempt_channel(struct gk20a *g, u32 chid); | 233 | int gk20a_fifo_preempt_channel(struct gk20a *g, struct channel_gk20a *ch); |
234 | int gk20a_fifo_preempt_tsg(struct gk20a *g, struct tsg_gk20a *tsg); | 234 | int gk20a_fifo_preempt_tsg(struct gk20a *g, struct tsg_gk20a *tsg); |
235 | int gk20a_fifo_preempt(struct gk20a *g, struct channel_gk20a *ch); | 235 | int gk20a_fifo_preempt(struct gk20a *g, struct channel_gk20a *ch); |
236 | 236 | ||
@@ -391,7 +391,7 @@ int gk20a_fifo_is_preempt_pending(struct gk20a *g, u32 id, | |||
391 | unsigned int id_type); | 391 | unsigned int id_type); |
392 | int __locked_fifo_preempt(struct gk20a *g, u32 id, bool is_tsg); | 392 | int __locked_fifo_preempt(struct gk20a *g, u32 id, bool is_tsg); |
393 | void gk20a_fifo_preempt_timeout_rc_tsg(struct gk20a *g, struct tsg_gk20a *tsg); | 393 | void gk20a_fifo_preempt_timeout_rc_tsg(struct gk20a *g, struct tsg_gk20a *tsg); |
394 | void gk20a_fifo_preempt_timeout_rc(struct gk20a *g, u32 chid); | 394 | void gk20a_fifo_preempt_timeout_rc(struct gk20a *g, struct channel_gk20a *ch); |
395 | int gk20a_fifo_setup_ramfc(struct channel_gk20a *c, | 395 | int gk20a_fifo_setup_ramfc(struct channel_gk20a *c, |
396 | u64 gpfifo_base, u32 gpfifo_entries, | 396 | u64 gpfifo_base, u32 gpfifo_entries, |
397 | unsigned long timeout, u32 flags); | 397 | unsigned long timeout, u32 flags); |
diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index fb9c7712..8b5eef82 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | |||
@@ -801,22 +801,17 @@ int gv11b_fifo_is_preempt_pending(struct gk20a *g, u32 id, | |||
801 | return ret; | 801 | return ret; |
802 | } | 802 | } |
803 | 803 | ||
804 | int gv11b_fifo_preempt_channel(struct gk20a *g, u32 chid) | 804 | int gv11b_fifo_preempt_channel(struct gk20a *g, struct channel_gk20a *ch) |
805 | { | 805 | { |
806 | struct fifo_gk20a *f = &g->fifo; | ||
807 | struct tsg_gk20a *tsg = NULL; | 806 | struct tsg_gk20a *tsg = NULL; |
808 | 807 | ||
809 | if (chid == FIFO_INVAL_CHANNEL_ID) { | 808 | tsg = tsg_gk20a_from_ch(ch); |
810 | return 0; | ||
811 | } | ||
812 | |||
813 | tsg = tsg_gk20a_from_ch(&f->channel[chid]); | ||
814 | 809 | ||
815 | if (tsg == NULL) { | 810 | if (tsg == NULL) { |
816 | return 0; | 811 | return 0; |
817 | } | 812 | } |
818 | 813 | ||
819 | nvgpu_log_info(g, "chid:%d tsgid:%d", chid, tsg->tsgid); | 814 | nvgpu_log_info(g, "chid:%d tsgid:%d", ch->chid, tsg->tsgid); |
820 | 815 | ||
821 | /* Preempt tsg. Channel preempt is NOOP */ | 816 | /* Preempt tsg. Channel preempt is NOOP */ |
822 | return g->ops.fifo.preempt_tsg(g, tsg); | 817 | return g->ops.fifo.preempt_tsg(g, tsg); |
diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h index 7ff42637..3d491bad 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h | |||
@@ -81,7 +81,7 @@ u32 gv11b_fifo_intr_0_error_mask(struct gk20a *g); | |||
81 | int gv11b_fifo_reschedule_runlist(struct channel_gk20a *ch, bool preempt_next); | 81 | int gv11b_fifo_reschedule_runlist(struct channel_gk20a *ch, bool preempt_next); |
82 | int gv11b_fifo_is_preempt_pending(struct gk20a *g, u32 id, | 82 | int gv11b_fifo_is_preempt_pending(struct gk20a *g, u32 id, |
83 | unsigned int id_type); | 83 | unsigned int id_type); |
84 | int gv11b_fifo_preempt_channel(struct gk20a *g, u32 chid); | 84 | int gv11b_fifo_preempt_channel(struct gk20a *g, struct channel_gk20a *ch); |
85 | int gv11b_fifo_preempt_tsg(struct gk20a *g, struct tsg_gk20a *tsg); | 85 | int gv11b_fifo_preempt_tsg(struct gk20a *g, struct tsg_gk20a *tsg); |
86 | int gv11b_fifo_enable_tsg(struct tsg_gk20a *tsg); | 86 | int gv11b_fifo_enable_tsg(struct tsg_gk20a *tsg); |
87 | void gv11b_fifo_teardown_ch_tsg(struct gk20a *g, u32 act_eng_bitmask, | 87 | void gv11b_fifo_teardown_ch_tsg(struct gk20a *g, u32 act_eng_bitmask, |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h index f6aabd82..dfa4aaf2 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h | |||
@@ -645,7 +645,7 @@ struct gpu_ops { | |||
645 | unsigned long acquire_timeout, | 645 | unsigned long acquire_timeout, |
646 | u32 flags); | 646 | u32 flags); |
647 | int (*resetup_ramfc)(struct channel_gk20a *c); | 647 | int (*resetup_ramfc)(struct channel_gk20a *c); |
648 | int (*preempt_channel)(struct gk20a *g, u32 chid); | 648 | int (*preempt_channel)(struct gk20a *g, struct channel_gk20a *ch); |
649 | int (*preempt_tsg)(struct gk20a *g, struct tsg_gk20a *tsg); | 649 | int (*preempt_tsg)(struct gk20a *g, struct tsg_gk20a *tsg); |
650 | int (*enable_tsg)(struct tsg_gk20a *tsg); | 650 | int (*enable_tsg)(struct tsg_gk20a *tsg); |
651 | int (*disable_tsg)(struct tsg_gk20a *tsg); | 651 | int (*disable_tsg)(struct tsg_gk20a *tsg); |
diff --git a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c index 9e3f7867..234f6fd4 100644 --- a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c | |||
@@ -443,10 +443,8 @@ int vgpu_init_fifo_support(struct gk20a *g) | |||
443 | return err; | 443 | return err; |
444 | } | 444 | } |
445 | 445 | ||
446 | int vgpu_fifo_preempt_channel(struct gk20a *g, u32 chid) | 446 | int vgpu_fifo_preempt_channel(struct gk20a *g, struct channel_gk20a *ch) |
447 | { | 447 | { |
448 | struct fifo_gk20a *f = &g->fifo; | ||
449 | struct channel_gk20a *ch = &f->channel[chid]; | ||
450 | struct tegra_vgpu_cmd_msg msg; | 448 | struct tegra_vgpu_cmd_msg msg; |
451 | struct tegra_vgpu_channel_config_params *p = | 449 | struct tegra_vgpu_channel_config_params *p = |
452 | &msg.params.channel_config; | 450 | &msg.params.channel_config; |
@@ -464,7 +462,7 @@ int vgpu_fifo_preempt_channel(struct gk20a *g, u32 chid) | |||
464 | 462 | ||
465 | if (err || msg.ret) { | 463 | if (err || msg.ret) { |
466 | nvgpu_err(g, | 464 | nvgpu_err(g, |
467 | "preempt channel %d failed", chid); | 465 | "preempt channel %d failed", ch->chid); |
468 | err = -ENOMEM; | 466 | err = -ENOMEM; |
469 | } | 467 | } |
470 | 468 | ||
diff --git a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.h b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.h index 8c042033..db199f8f 100644 --- a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.h +++ b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.h | |||
@@ -41,7 +41,7 @@ int vgpu_channel_setup_ramfc(struct channel_gk20a *ch, u64 gpfifo_base, | |||
41 | u32 gpfifo_entries, | 41 | u32 gpfifo_entries, |
42 | unsigned long acquire_timeout, u32 flags); | 42 | unsigned long acquire_timeout, u32 flags); |
43 | int vgpu_fifo_init_engine_info(struct fifo_gk20a *f); | 43 | int vgpu_fifo_init_engine_info(struct fifo_gk20a *f); |
44 | int vgpu_fifo_preempt_channel(struct gk20a *g, u32 chid); | 44 | int vgpu_fifo_preempt_channel(struct gk20a *g, struct channel_gk20a *ch); |
45 | int vgpu_fifo_preempt_tsg(struct gk20a *g, struct tsg_gk20a *tsg); | 45 | int vgpu_fifo_preempt_tsg(struct gk20a *g, struct tsg_gk20a *tsg); |
46 | int vgpu_fifo_update_runlist(struct gk20a *g, u32 runlist_id, | 46 | int vgpu_fifo_update_runlist(struct gk20a *g, u32 runlist_id, |
47 | u32 chid, bool add, bool wait_for_finish); | 47 | u32 chid, bool add, bool wait_for_finish); |