diff options
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/clk_gm20b.c | 21 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/clk_gm20b.h | 10 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 24 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/clk_arb_gp106.c | 14 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/clk_arb_gp106.h | 8 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/clk_gp106.c | 19 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/clk_gp106.h | 5 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/hal_gp106.c | 32 |
8 files changed, 83 insertions, 50 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c index 8f770e2e..22501c64 100644 --- a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c | |||
@@ -1389,7 +1389,7 @@ static int set_pll_freq(struct gk20a *g, int allow_slide) | |||
1389 | return err; | 1389 | return err; |
1390 | } | 1390 | } |
1391 | 1391 | ||
1392 | static int gm20b_init_clk_support(struct gk20a *g) | 1392 | int gm20b_init_clk_support(struct gk20a *g) |
1393 | { | 1393 | { |
1394 | struct clk_gk20a *clk = &g->clk; | 1394 | struct clk_gk20a *clk = &g->clk; |
1395 | u32 err; | 1395 | u32 err; |
@@ -1427,7 +1427,7 @@ static int gm20b_init_clk_support(struct gk20a *g) | |||
1427 | return err; | 1427 | return err; |
1428 | } | 1428 | } |
1429 | 1429 | ||
1430 | static int gm20b_suspend_clk_support(struct gk20a *g) | 1430 | int gm20b_suspend_clk_support(struct gk20a *g) |
1431 | { | 1431 | { |
1432 | int ret = 0; | 1432 | int ret = 0; |
1433 | 1433 | ||
@@ -1445,7 +1445,7 @@ static int gm20b_suspend_clk_support(struct gk20a *g) | |||
1445 | return ret; | 1445 | return ret; |
1446 | } | 1446 | } |
1447 | 1447 | ||
1448 | static int gm20b_clk_get_voltage(struct clk_gk20a *clk, u64 *val) | 1448 | int gm20b_clk_get_voltage(struct clk_gk20a *clk, u64 *val) |
1449 | { | 1449 | { |
1450 | struct gk20a *g = clk->g; | 1450 | struct gk20a *g = clk->g; |
1451 | struct pll_parms *gpc_pll_params = gm20b_get_gpc_pll_parms(); | 1451 | struct pll_parms *gpc_pll_params = gm20b_get_gpc_pll_parms(); |
@@ -1472,7 +1472,7 @@ static int gm20b_clk_get_voltage(struct clk_gk20a *clk, u64 *val) | |||
1472 | return 0; | 1472 | return 0; |
1473 | } | 1473 | } |
1474 | 1474 | ||
1475 | static int gm20b_clk_get_gpcclk_clock_counter(struct clk_gk20a *clk, u64 *val) | 1475 | int gm20b_clk_get_gpcclk_clock_counter(struct clk_gk20a *clk, u64 *val) |
1476 | { | 1476 | { |
1477 | struct gk20a *g = clk->g; | 1477 | struct gk20a *g = clk->g; |
1478 | u32 clk_slowdown, clk_slowdown_save; | 1478 | u32 clk_slowdown, clk_slowdown_save; |
@@ -1593,16 +1593,3 @@ int gm20b_clk_get_pll_debug_data(struct gk20a *g, | |||
1593 | nvgpu_mutex_release(&g->clk.clk_mutex); | 1593 | nvgpu_mutex_release(&g->clk.clk_mutex); |
1594 | return 0; | 1594 | return 0; |
1595 | } | 1595 | } |
1596 | |||
1597 | void gm20b_init_clk_ops(struct gpu_ops *gops) | ||
1598 | { | ||
1599 | gops->clk.init_clk_support = gm20b_init_clk_support; | ||
1600 | gops->clk.suspend_clk_support = gm20b_suspend_clk_support; | ||
1601 | #ifdef CONFIG_DEBUG_FS | ||
1602 | gops->clk.init_debugfs = gm20b_clk_init_debugfs; | ||
1603 | #endif | ||
1604 | gops->clk.get_voltage = gm20b_clk_get_voltage; | ||
1605 | gops->clk.get_gpcclk_clock_counter = gm20b_clk_get_gpcclk_clock_counter; | ||
1606 | gops->clk.pll_reg_write = gm20b_clk_pll_reg_write; | ||
1607 | gops->clk.get_pll_debug_data = gm20b_clk_get_pll_debug_data; | ||
1608 | } | ||
diff --git a/drivers/gpu/nvgpu/gm20b/clk_gm20b.h b/drivers/gpu/nvgpu/gm20b/clk_gm20b.h index 1e06d651..07e0d04d 100644 --- a/drivers/gpu/nvgpu/gm20b/clk_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/clk_gm20b.h | |||
@@ -50,8 +50,6 @@ struct nvgpu_clk_pll_debug_data { | |||
50 | u32 trim_sys_gpcpll_dvfs0_dfs_dc_offset; | 50 | u32 trim_sys_gpcpll_dvfs0_dfs_dc_offset; |
51 | }; | 51 | }; |
52 | 52 | ||
53 | void gm20b_init_clk_ops(struct gpu_ops *gops); | ||
54 | |||
55 | int gm20b_init_clk_setup_sw(struct gk20a *g); | 53 | int gm20b_init_clk_setup_sw(struct gk20a *g); |
56 | 54 | ||
57 | int gm20b_clk_prepare(struct clk_gk20a *clk); | 55 | int gm20b_clk_prepare(struct clk_gk20a *clk); |
@@ -67,6 +65,14 @@ struct pll_parms *gm20b_get_gpc_pll_parms(void); | |||
67 | int gm20b_clk_init_debugfs(struct gk20a *g); | 65 | int gm20b_clk_init_debugfs(struct gk20a *g); |
68 | #endif | 66 | #endif |
69 | 67 | ||
68 | int gm20b_clk_pll_reg_write(struct gk20a *g, u32 reg, u32 val); | ||
69 | int gm20b_init_clk_support(struct gk20a *g); | ||
70 | int gm20b_suspend_clk_support(struct gk20a *g); | ||
71 | int gm20b_clk_get_voltage(struct clk_gk20a *clk, u64 *val); | ||
72 | int gm20b_clk_get_gpcclk_clock_counter(struct clk_gk20a *clk, u64 *val); | ||
73 | int gm20b_clk_get_pll_debug_data(struct gk20a *g, | ||
74 | struct nvgpu_clk_pll_debug_data *d); | ||
75 | |||
70 | /* 1:1 match between post divider settings and divisor value */ | 76 | /* 1:1 match between post divider settings and divisor value */ |
71 | static inline u32 nvgpu_pl_to_div(u32 pl) | 77 | static inline u32 nvgpu_pl_to_div(u32 pl) |
72 | { | 78 | { |
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index c2bccbee..c16cd3e5 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c | |||
@@ -277,6 +277,17 @@ static const struct gpu_ops gm20b_ops = { | |||
277 | .init_therm_setup_hw = gm20b_init_therm_setup_hw, | 277 | .init_therm_setup_hw = gm20b_init_therm_setup_hw, |
278 | .elcg_init_idle_filters = gk20a_elcg_init_idle_filters, | 278 | .elcg_init_idle_filters = gk20a_elcg_init_idle_filters, |
279 | }, | 279 | }, |
280 | .clk = { | ||
281 | .init_clk_support = gm20b_init_clk_support, | ||
282 | .suspend_clk_support = gm20b_suspend_clk_support, | ||
283 | #ifdef CONFIG_DEBUG_FS | ||
284 | .init_debugfs = gm20b_clk_init_debugfs, | ||
285 | #endif | ||
286 | .get_voltage = gm20b_clk_get_voltage, | ||
287 | .get_gpcclk_clock_counter = gm20b_clk_get_gpcclk_clock_counter, | ||
288 | .pll_reg_write = gm20b_clk_pll_reg_write, | ||
289 | .get_pll_debug_data = gm20b_clk_get_pll_debug_data, | ||
290 | }, | ||
280 | .regops = { | 291 | .regops = { |
281 | .get_global_whitelist_ranges = | 292 | .get_global_whitelist_ranges = |
282 | gm20b_get_global_whitelist_ranges, | 293 | gm20b_get_global_whitelist_ranges, |
@@ -373,6 +384,18 @@ int gm20b_init_hal(struct gk20a *g) | |||
373 | gops->fifo = gm20b_ops.fifo; | 384 | gops->fifo = gm20b_ops.fifo; |
374 | gops->gr_ctx = gm20b_ops.gr_ctx; | 385 | gops->gr_ctx = gm20b_ops.gr_ctx; |
375 | gops->therm = gm20b_ops.therm; | 386 | gops->therm = gm20b_ops.therm; |
387 | /* | ||
388 | * clk must be assigned member by member | ||
389 | * since some clk ops are assigned during probe prior to HAL init | ||
390 | */ | ||
391 | gops->clk.init_clk_support = gm20b_ops.clk.init_clk_support; | ||
392 | gops->clk.suspend_clk_support = gm20b_ops.clk.suspend_clk_support; | ||
393 | gops->clk.get_voltage = gm20b_ops.clk.get_voltage; | ||
394 | gops->clk.get_gpcclk_clock_counter = | ||
395 | gm20b_ops.clk.get_gpcclk_clock_counter; | ||
396 | gops->clk.pll_reg_write = gm20b_ops.clk.pll_reg_write; | ||
397 | gops->clk.get_pll_debug_data = gm20b_ops.clk.get_pll_debug_data; | ||
398 | |||
376 | gops->regops = gm20b_ops.regops; | 399 | gops->regops = gm20b_ops.regops; |
377 | gops->mc = gm20b_ops.mc; | 400 | gops->mc = gm20b_ops.mc; |
378 | gops->dbg_session_ops = gm20b_ops.dbg_session_ops; | 401 | gops->dbg_session_ops = gm20b_ops.dbg_session_ops; |
@@ -427,7 +450,6 @@ int gm20b_init_hal(struct gk20a *g) | |||
427 | gm20b_init_fb(gops); | 450 | gm20b_init_fb(gops); |
428 | gm20b_init_mm(gops); | 451 | gm20b_init_mm(gops); |
429 | gm20b_init_pmu_ops(g); | 452 | gm20b_init_pmu_ops(g); |
430 | gm20b_init_clk_ops(gops); | ||
431 | 453 | ||
432 | g->name = "gm20b"; | 454 | g->name = "gm20b"; |
433 | 455 | ||
diff --git a/drivers/gpu/nvgpu/gp106/clk_arb_gp106.c b/drivers/gpu/nvgpu/gp106/clk_arb_gp106.c index 4a907521..5f9c251f 100644 --- a/drivers/gpu/nvgpu/gp106/clk_arb_gp106.c +++ b/drivers/gpu/nvgpu/gp106/clk_arb_gp106.c | |||
@@ -16,13 +16,13 @@ | |||
16 | #include "clk/clk_arb.h" | 16 | #include "clk/clk_arb.h" |
17 | #include "clk_arb_gp106.h" | 17 | #include "clk_arb_gp106.h" |
18 | 18 | ||
19 | static u32 gp106_get_arbiter_clk_domains(struct gk20a *g) | 19 | u32 gp106_get_arbiter_clk_domains(struct gk20a *g) |
20 | { | 20 | { |
21 | (void)g; | 21 | (void)g; |
22 | return (CTRL_CLK_DOMAIN_MCLK|CTRL_CLK_DOMAIN_GPC2CLK); | 22 | return (CTRL_CLK_DOMAIN_MCLK|CTRL_CLK_DOMAIN_GPC2CLK); |
23 | } | 23 | } |
24 | 24 | ||
25 | static int gp106_get_arbiter_clk_range(struct gk20a *g, u32 api_domain, | 25 | int gp106_get_arbiter_clk_range(struct gk20a *g, u32 api_domain, |
26 | u16 *min_mhz, u16 *max_mhz) | 26 | u16 *min_mhz, u16 *max_mhz) |
27 | { | 27 | { |
28 | enum nv_pmu_clk_clkwhich clkwhich; | 28 | enum nv_pmu_clk_clkwhich clkwhich; |
@@ -68,7 +68,7 @@ static int gp106_get_arbiter_clk_range(struct gk20a *g, u32 api_domain, | |||
68 | return 0; | 68 | return 0; |
69 | } | 69 | } |
70 | 70 | ||
71 | static int gp106_get_arbiter_clk_default(struct gk20a *g, u32 api_domain, | 71 | int gp106_get_arbiter_clk_default(struct gk20a *g, u32 api_domain, |
72 | u16 *default_mhz) | 72 | u16 *default_mhz) |
73 | { | 73 | { |
74 | enum nv_pmu_clk_clkwhich clkwhich; | 74 | enum nv_pmu_clk_clkwhich clkwhich; |
@@ -96,11 +96,3 @@ static int gp106_get_arbiter_clk_default(struct gk20a *g, u32 api_domain, | |||
96 | 96 | ||
97 | return 0; | 97 | return 0; |
98 | } | 98 | } |
99 | |||
100 | void gp106_init_clk_arb_ops(struct gpu_ops *gops) | ||
101 | { | ||
102 | gops->clk_arb.get_arbiter_clk_domains = gp106_get_arbiter_clk_domains; | ||
103 | gops->clk_arb.get_arbiter_clk_range = gp106_get_arbiter_clk_range; | ||
104 | gops->clk_arb.get_arbiter_clk_default = gp106_get_arbiter_clk_default; | ||
105 | gops->clk_arb.get_current_pstate = nvgpu_clk_arb_get_current_pstate; | ||
106 | } | ||
diff --git a/drivers/gpu/nvgpu/gp106/clk_arb_gp106.h b/drivers/gpu/nvgpu/gp106/clk_arb_gp106.h index a9877199..5b5ca4a9 100644 --- a/drivers/gpu/nvgpu/gp106/clk_arb_gp106.h +++ b/drivers/gpu/nvgpu/gp106/clk_arb_gp106.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -16,6 +16,10 @@ | |||
16 | #ifndef CLK_ARB_GP106_H | 16 | #ifndef CLK_ARB_GP106_H |
17 | #define CLK_ARB_GP106_H | 17 | #define CLK_ARB_GP106_H |
18 | 18 | ||
19 | void gp106_init_clk_arb_ops(struct gpu_ops *gops); | 19 | u32 gp106_get_arbiter_clk_domains(struct gk20a *g); |
20 | int gp106_get_arbiter_clk_range(struct gk20a *g, u32 api_domain, | ||
21 | u16 *min_mhz, u16 *max_mhz); | ||
22 | int gp106_get_arbiter_clk_default(struct gk20a *g, u32 api_domain, | ||
23 | u16 *default_mhz); | ||
20 | 24 | ||
21 | #endif /* CLK_ARB_GP106_H */ | 25 | #endif /* CLK_ARB_GP106_H */ |
diff --git a/drivers/gpu/nvgpu/gp106/clk_gp106.c b/drivers/gpu/nvgpu/gp106/clk_gp106.c index e9aec7ac..105f8bd5 100644 --- a/drivers/gpu/nvgpu/gp106/clk_gp106.c +++ b/drivers/gpu/nvgpu/gp106/clk_gp106.c | |||
@@ -47,12 +47,12 @@ static int clk_gp106_debugfs_init(struct gk20a *g); | |||
47 | 47 | ||
48 | 48 | ||
49 | static u32 gp106_get_rate_cntr(struct gk20a *g, struct namemap_cfg *); | 49 | static u32 gp106_get_rate_cntr(struct gk20a *g, struct namemap_cfg *); |
50 | static u32 gp106_crystal_clk_hz(struct gk20a *g) | 50 | u32 gp106_crystal_clk_hz(struct gk20a *g) |
51 | { | 51 | { |
52 | return (XTAL4X_KHZ * 1000); | 52 | return (XTAL4X_KHZ * 1000); |
53 | } | 53 | } |
54 | 54 | ||
55 | static unsigned long gp106_clk_measure_freq(struct gk20a *g, u32 api_domain) | 55 | unsigned long gp106_clk_measure_freq(struct gk20a *g, u32 api_domain) |
56 | { | 56 | { |
57 | struct clk_gk20a *clk = &g->clk; | 57 | struct clk_gk20a *clk = &g->clk; |
58 | u32 freq_khz; | 58 | u32 freq_khz; |
@@ -76,7 +76,8 @@ static unsigned long gp106_clk_measure_freq(struct gk20a *g, u32 api_domain) | |||
76 | return freq_khz * 1000UL; | 76 | return freq_khz * 1000UL; |
77 | } | 77 | } |
78 | 78 | ||
79 | static int gp106_init_clk_support(struct gk20a *g) { | 79 | int gp106_init_clk_support(struct gk20a *g) |
80 | { | ||
80 | struct clk_gk20a *clk = &g->clk; | 81 | struct clk_gk20a *clk = &g->clk; |
81 | u32 err = 0; | 82 | u32 err = 0; |
82 | 83 | ||
@@ -273,18 +274,8 @@ err_out: | |||
273 | } | 274 | } |
274 | #endif /* CONFIG_DEBUG_FS */ | 275 | #endif /* CONFIG_DEBUG_FS */ |
275 | 276 | ||
276 | static int gp106_suspend_clk_support(struct gk20a *g) | 277 | int gp106_suspend_clk_support(struct gk20a *g) |
277 | { | 278 | { |
278 | nvgpu_mutex_destroy(&g->clk.clk_mutex); | 279 | nvgpu_mutex_destroy(&g->clk.clk_mutex); |
279 | return 0; | 280 | return 0; |
280 | } | 281 | } |
281 | |||
282 | void gp106_init_clk_ops(struct gpu_ops *gops) { | ||
283 | gops->clk.init_clk_support = gp106_init_clk_support; | ||
284 | gops->clk.get_crystal_clk_hz = gp106_crystal_clk_hz; | ||
285 | gops->clk.measure_freq = gp106_clk_measure_freq; | ||
286 | gops->clk.suspend_clk_support = gp106_suspend_clk_support; | ||
287 | gops->clk.mclk_init = gp106_mclk_init; | ||
288 | gops->clk.mclk_change = gp106_mclk_change; | ||
289 | gops->clk.mclk_deinit = gp106_mclk_deinit; | ||
290 | } | ||
diff --git a/drivers/gpu/nvgpu/gp106/clk_gp106.h b/drivers/gpu/nvgpu/gp106/clk_gp106.h index 3c2e31d1..9adea2b2 100644 --- a/drivers/gpu/nvgpu/gp106/clk_gp106.h +++ b/drivers/gpu/nvgpu/gp106/clk_gp106.h | |||
@@ -51,6 +51,9 @@ struct namemap_cfg { | |||
51 | char name[24]; | 51 | char name[24]; |
52 | }; | 52 | }; |
53 | 53 | ||
54 | void gp106_init_clk_ops(struct gpu_ops *gops); | 54 | int gp106_init_clk_support(struct gk20a *g); |
55 | u32 gp106_crystal_clk_hz(struct gk20a *g); | ||
56 | unsigned long gp106_clk_measure_freq(struct gk20a *g, u32 api_domain); | ||
57 | int gp106_suspend_clk_support(struct gk20a *g); | ||
55 | 58 | ||
56 | #endif /* CLK_GP106_H */ | 59 | #endif /* CLK_GP106_H */ |
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c index 0caf890f..38778da7 100644 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c | |||
@@ -46,6 +46,7 @@ | |||
46 | 46 | ||
47 | #include "gp106/clk_gp106.h" | 47 | #include "gp106/clk_gp106.h" |
48 | #include "gp106/clk_arb_gp106.h" | 48 | #include "gp106/clk_arb_gp106.h" |
49 | #include "gp106/mclk_gp106.h" | ||
49 | #include "gm206/bios_gm206.h" | 50 | #include "gm206/bios_gm206.h" |
50 | #include "gp106/therm_gp106.h" | 51 | #include "gp106/therm_gp106.h" |
51 | #include "gp106/xve_gp106.h" | 52 | #include "gp106/xve_gp106.h" |
@@ -72,6 +73,7 @@ | |||
72 | #include <nvgpu/hw/gp106/hw_top_gp106.h> | 73 | #include <nvgpu/hw/gp106/hw_top_gp106.h> |
73 | #include <nvgpu/hw/gp106/hw_pram_gp106.h> | 74 | #include <nvgpu/hw/gp106/hw_pram_gp106.h> |
74 | 75 | ||
76 | |||
75 | static int gp106_get_litter_value(struct gk20a *g, int value) | 77 | static int gp106_get_litter_value(struct gk20a *g, int value) |
76 | { | 78 | { |
77 | int ret = -EINVAL; | 79 | int ret = -EINVAL; |
@@ -353,6 +355,21 @@ static const struct gpu_ops gp106_ops = { | |||
353 | .get_internal_sensor_limits = gp106_get_internal_sensor_limits, | 355 | .get_internal_sensor_limits = gp106_get_internal_sensor_limits, |
354 | .configure_therm_alert = gp106_configure_therm_alert, | 356 | .configure_therm_alert = gp106_configure_therm_alert, |
355 | }, | 357 | }, |
358 | .clk = { | ||
359 | .init_clk_support = gp106_init_clk_support, | ||
360 | .get_crystal_clk_hz = gp106_crystal_clk_hz, | ||
361 | .measure_freq = gp106_clk_measure_freq, | ||
362 | .suspend_clk_support = gp106_suspend_clk_support, | ||
363 | .mclk_init = gp106_mclk_init, | ||
364 | .mclk_change = gp106_mclk_change, | ||
365 | .mclk_deinit = gp106_mclk_deinit, | ||
366 | }, | ||
367 | .clk_arb = { | ||
368 | .get_arbiter_clk_domains = gp106_get_arbiter_clk_domains, | ||
369 | .get_arbiter_clk_range = gp106_get_arbiter_clk_range, | ||
370 | .get_arbiter_clk_default = gp106_get_arbiter_clk_default, | ||
371 | .get_current_pstate = nvgpu_clk_arb_get_current_pstate, | ||
372 | }, | ||
356 | .regops = { | 373 | .regops = { |
357 | .get_global_whitelist_ranges = | 374 | .get_global_whitelist_ranges = |
358 | gp106_get_global_whitelist_ranges, | 375 | gp106_get_global_whitelist_ranges, |
@@ -470,6 +487,19 @@ int gp106_init_hal(struct gk20a *g) | |||
470 | gops->fecs_trace = gp106_ops.fecs_trace; | 487 | gops->fecs_trace = gp106_ops.fecs_trace; |
471 | gops->pramin = gp106_ops.pramin; | 488 | gops->pramin = gp106_ops.pramin; |
472 | gops->therm = gp106_ops.therm; | 489 | gops->therm = gp106_ops.therm; |
490 | /* | ||
491 | * clk must be assigned member by member | ||
492 | * since some clk ops are assigned during probe prior to HAL init | ||
493 | */ | ||
494 | gops->clk.init_clk_support = gp106_ops.clk.init_clk_support; | ||
495 | gops->clk.get_crystal_clk_hz = gp106_ops.clk.get_crystal_clk_hz; | ||
496 | gops->clk.measure_freq = gp106_ops.clk.measure_freq; | ||
497 | gops->clk.suspend_clk_support = gp106_ops.clk.suspend_clk_support; | ||
498 | gops->clk.mclk_init = gp106_ops.clk.mclk_init; | ||
499 | gops->clk.mclk_change = gp106_ops.clk.mclk_change; | ||
500 | gops->clk.mclk_deinit = gp106_ops.clk.mclk_deinit; | ||
501 | |||
502 | gops->clk_arb = gp106_ops.clk_arb; | ||
473 | gops->regops = gp106_ops.regops; | 503 | gops->regops = gp106_ops.regops; |
474 | gops->mc = gp106_ops.mc; | 504 | gops->mc = gp106_ops.mc; |
475 | gops->debug = gp106_ops.debug; | 505 | gops->debug = gp106_ops.debug; |
@@ -499,8 +529,6 @@ int gp106_init_hal(struct gk20a *g) | |||
499 | gp106_init_fb(gops); | 529 | gp106_init_fb(gops); |
500 | gp106_init_mm(gops); | 530 | gp106_init_mm(gops); |
501 | gp106_init_pmu_ops(g); | 531 | gp106_init_pmu_ops(g); |
502 | gp106_init_clk_ops(gops); | ||
503 | gp106_init_clk_arb_ops(gops); | ||
504 | 532 | ||
505 | g->name = "gp10x"; | 533 | g->name = "gp10x"; |
506 | 534 | ||