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-rw-r--r--drivers/gpu/nvgpu/gk20a/fifo_gk20a.c24
1 files changed, 16 insertions, 8 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
index 9d323803..56b954a9 100644
--- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
@@ -1252,10 +1252,10 @@ static bool gk20a_fifo_handle_sched_error(struct gk20a *g)
1252 u32 engine_id; 1252 u32 engine_id;
1253 int id = -1; 1253 int id = -1;
1254 bool non_chid = false; 1254 bool non_chid = false;
1255 bool ret = false;
1255 1256
1256 /* read and reset the scheduler error register */ 1257 /* read the scheduler error register */
1257 sched_error = gk20a_readl(g, fifo_intr_sched_error_r()); 1258 sched_error = gk20a_readl(g, fifo_intr_sched_error_r());
1258 gk20a_writel(g, fifo_intr_0_r(), fifo_intr_0_sched_error_reset_f());
1259 1259
1260 for (engine_id = 0; engine_id < g->fifo.max_engines; engine_id++) { 1260 for (engine_id = 0; engine_id < g->fifo.max_engines; engine_id++) {
1261 u32 status = gk20a_readl(g, fifo_engine_status_r(engine_id)); 1261 u32 status = gk20a_readl(g, fifo_engine_status_r(engine_id));
@@ -1287,8 +1287,12 @@ static bool gk20a_fifo_handle_sched_error(struct gk20a *g)
1287 } 1287 }
1288 1288
1289 /* could not find the engine - should never happen */ 1289 /* could not find the engine - should never happen */
1290 if (unlikely(engine_id >= g->fifo.max_engines)) 1290 if (unlikely(engine_id >= g->fifo.max_engines)) {
1291 gk20a_err(dev_from_gk20a(g), "fifo sched error : 0x%08x, failed to find engine\n",
1292 sched_error);
1293 ret = false;
1291 goto err; 1294 goto err;
1295 }
1292 1296
1293 if (fifo_intr_sched_error_code_f(sched_error) == 1297 if (fifo_intr_sched_error_code_f(sched_error) ==
1294 fifo_intr_sched_error_code_ctxsw_timeout_v()) { 1298 fifo_intr_sched_error_code_ctxsw_timeout_v()) {
@@ -1297,6 +1301,7 @@ static bool gk20a_fifo_handle_sched_error(struct gk20a *g)
1297 1301
1298 if (non_chid) { 1302 if (non_chid) {
1299 gk20a_fifo_recover(g, BIT(engine_id), true); 1303 gk20a_fifo_recover(g, BIT(engine_id), true);
1304 ret = true;
1300 goto err; 1305 goto err;
1301 } 1306 }
1302 1307
@@ -1310,20 +1315,23 @@ static bool gk20a_fifo_handle_sched_error(struct gk20a *g)
1310 gk20a_gr_debug_dump(g->dev); 1315 gk20a_gr_debug_dump(g->dev);
1311 gk20a_fifo_recover(g, BIT(engine_id), 1316 gk20a_fifo_recover(g, BIT(engine_id),
1312 ch->timeout_debug_dump); 1317 ch->timeout_debug_dump);
1318 ret = true;
1313 } else { 1319 } else {
1314 gk20a_dbg_info( 1320 gk20a_dbg_info(
1315 "fifo is waiting for ctx switch for %d ms," 1321 "fifo is waiting for ctx switch for %d ms,"
1316 "ch = %d\n", 1322 "ch = %d\n",
1317 ch->timeout_accumulated_ms, 1323 ch->timeout_accumulated_ms,
1318 id); 1324 id);
1325 ret = false;
1319 } 1326 }
1320 return ch->timeout_debug_dump; 1327 return ret;
1321 } 1328 }
1322err: 1329
1323 gk20a_err(dev_from_gk20a(g), "fifo sched error : 0x%08x, engine=%u, %s=%d", 1330 gk20a_err(dev_from_gk20a(g), "fifo sched error : 0x%08x, engine=%u, %s=%d",
1324 sched_error, engine_id, non_chid ? "non-ch" : "ch", id); 1331 sched_error, engine_id, non_chid ? "non-ch" : "ch", id);
1325 1332
1326 return true; 1333err:
1334 return ret;
1327} 1335}
1328 1336
1329static u32 fifo_error_isr(struct gk20a *g, u32 fifo_intr) 1337static u32 fifo_error_isr(struct gk20a *g, u32 fifo_intr)
@@ -1375,7 +1383,7 @@ static u32 fifo_error_isr(struct gk20a *g, u32 fifo_intr)
1375 if (print_channel_reset_log) { 1383 if (print_channel_reset_log) {
1376 int engine_id; 1384 int engine_id;
1377 gk20a_err(dev_from_gk20a(g), 1385 gk20a_err(dev_from_gk20a(g),
1378 "channel reset initated from %s; intr=0x%08x", 1386 "channel reset initiated from %s; intr=0x%08x",
1379 __func__, fifo_intr); 1387 __func__, fifo_intr);
1380 for (engine_id = 0; 1388 for (engine_id = 0;
1381 engine_id < g->fifo.max_engines; 1389 engine_id < g->fifo.max_engines;