diff options
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hw_gmmu_gv11b.h | 12 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h | 372 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hw_mc_gv11b.h | 4 |
3 files changed, 384 insertions, 4 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/hw_gmmu_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_gmmu_gv11b.h index 99cc3442..b7aa46bc 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_gmmu_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_gmmu_gv11b.h | |||
@@ -1074,6 +1074,14 @@ static inline u32 gmmu_pte_kind_c32_ms2_2c_v(void) | |||
1074 | { | 1074 | { |
1075 | return 0x000000dd; | 1075 | return 0x000000dd; |
1076 | } | 1076 | } |
1077 | static inline u32 gmmu_pte_kind_c32_ms2_2cbr_v(void) | ||
1078 | { | ||
1079 | return 0x000000de; | ||
1080 | } | ||
1081 | static inline u32 gmmu_pte_kind_c32_ms2_4cbra_v(void) | ||
1082 | { | ||
1083 | return 0x000000cc; | ||
1084 | } | ||
1077 | static inline u32 gmmu_pte_kind_c32_ms4_2c_v(void) | 1085 | static inline u32 gmmu_pte_kind_c32_ms4_2c_v(void) |
1078 | { | 1086 | { |
1079 | return 0x000000df; | 1087 | return 0x000000df; |
@@ -1134,6 +1142,10 @@ static inline u32 gmmu_pte_kind_c64_ms2_2cbr_v(void) | |||
1134 | { | 1142 | { |
1135 | return 0x000000ec; | 1143 | return 0x000000ec; |
1136 | } | 1144 | } |
1145 | static inline u32 gmmu_pte_kind_c64_ms2_2cbra_v(void) | ||
1146 | { | ||
1147 | return 0x000000cd; | ||
1148 | } | ||
1137 | static inline u32 gmmu_pte_kind_c64_ms4_2c_v(void) | 1149 | static inline u32 gmmu_pte_kind_c64_ms4_2c_v(void) |
1138 | { | 1150 | { |
1139 | return 0x000000ed; | 1151 | return 0x000000ed; |
diff --git a/drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h index 3772d9ab..37556fb9 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h | |||
@@ -706,6 +706,10 @@ static inline u32 gr_fe_object_table_nvclass_v(u32 r) | |||
706 | { | 706 | { |
707 | return (r >> 0) & 0xffff; | 707 | return (r >> 0) & 0xffff; |
708 | } | 708 | } |
709 | static inline u32 gr_fe_tpc_fs_r(u32 i) | ||
710 | { | ||
711 | return 0x0040a200 + i*4; | ||
712 | } | ||
709 | static inline u32 gr_pri_mme_shadow_raw_index_r(void) | 713 | static inline u32 gr_pri_mme_shadow_raw_index_r(void) |
710 | { | 714 | { |
711 | return 0x00404488; | 715 | return 0x00404488; |
@@ -1518,6 +1522,10 @@ static inline u32 gr_gpc0_gpccs_ctxsw_idlestate_r(void) | |||
1518 | { | 1522 | { |
1519 | return 0x00502420; | 1523 | return 0x00502420; |
1520 | } | 1524 | } |
1525 | static inline u32 gr_rstr2d_gpc_map_r(u32 i) | ||
1526 | { | ||
1527 | return 0x0040780c + i*4; | ||
1528 | } | ||
1521 | static inline u32 gr_rstr2d_map_table_cfg_r(void) | 1529 | static inline u32 gr_rstr2d_map_table_cfg_r(void) |
1522 | { | 1530 | { |
1523 | return 0x004078bc; | 1531 | return 0x004078bc; |
@@ -2302,6 +2310,14 @@ static inline u32 gr_gpc0_tpc0_sm_cfg_r(void) | |||
2302 | { | 2310 | { |
2303 | return 0x00504608; | 2311 | return 0x00504608; |
2304 | } | 2312 | } |
2313 | static inline u32 gr_gpc0_tpc0_sm_cfg_sm_id_f(u32 v) | ||
2314 | { | ||
2315 | return (v & 0xffff) << 0; | ||
2316 | } | ||
2317 | static inline u32 gr_gpc0_tpc0_sm_cfg_sm_id_v(u32 r) | ||
2318 | { | ||
2319 | return (r >> 0) & 0xffff; | ||
2320 | } | ||
2305 | static inline u32 gr_gpc0_tpc0_sm_arch_r(void) | 2321 | static inline u32 gr_gpc0_tpc0_sm_arch_r(void) |
2306 | { | 2322 | { |
2307 | return 0x00504330; | 2323 | return 0x00504330; |
@@ -2810,6 +2826,34 @@ static inline u32 gr_gpcs_setup_attrib_cb_base_valid_true_f(void) | |||
2810 | { | 2826 | { |
2811 | return 0x80000000; | 2827 | return 0x80000000; |
2812 | } | 2828 | } |
2829 | static inline u32 gr_crstr_gpc_map_r(u32 i) | ||
2830 | { | ||
2831 | return 0x00418b08 + i*4; | ||
2832 | } | ||
2833 | static inline u32 gr_crstr_gpc_map_tile0_f(u32 v) | ||
2834 | { | ||
2835 | return (v & 0x1f) << 0; | ||
2836 | } | ||
2837 | static inline u32 gr_crstr_gpc_map_tile1_f(u32 v) | ||
2838 | { | ||
2839 | return (v & 0x1f) << 5; | ||
2840 | } | ||
2841 | static inline u32 gr_crstr_gpc_map_tile2_f(u32 v) | ||
2842 | { | ||
2843 | return (v & 0x1f) << 10; | ||
2844 | } | ||
2845 | static inline u32 gr_crstr_gpc_map_tile3_f(u32 v) | ||
2846 | { | ||
2847 | return (v & 0x1f) << 15; | ||
2848 | } | ||
2849 | static inline u32 gr_crstr_gpc_map_tile4_f(u32 v) | ||
2850 | { | ||
2851 | return (v & 0x1f) << 20; | ||
2852 | } | ||
2853 | static inline u32 gr_crstr_gpc_map_tile5_f(u32 v) | ||
2854 | { | ||
2855 | return (v & 0x1f) << 25; | ||
2856 | } | ||
2813 | static inline u32 gr_crstr_map_table_cfg_r(void) | 2857 | static inline u32 gr_crstr_map_table_cfg_r(void) |
2814 | { | 2858 | { |
2815 | return 0x00418bb8; | 2859 | return 0x00418bb8; |
@@ -2822,6 +2866,42 @@ static inline u32 gr_crstr_map_table_cfg_num_entries_f(u32 v) | |||
2822 | { | 2866 | { |
2823 | return (v & 0xff) << 8; | 2867 | return (v & 0xff) << 8; |
2824 | } | 2868 | } |
2869 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_r(u32 i) | ||
2870 | { | ||
2871 | return 0x00418980 + i*4; | ||
2872 | } | ||
2873 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_0_f(u32 v) | ||
2874 | { | ||
2875 | return (v & 0x7) << 0; | ||
2876 | } | ||
2877 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_1_f(u32 v) | ||
2878 | { | ||
2879 | return (v & 0x7) << 4; | ||
2880 | } | ||
2881 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_2_f(u32 v) | ||
2882 | { | ||
2883 | return (v & 0x7) << 8; | ||
2884 | } | ||
2885 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_3_f(u32 v) | ||
2886 | { | ||
2887 | return (v & 0x7) << 12; | ||
2888 | } | ||
2889 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_4_f(u32 v) | ||
2890 | { | ||
2891 | return (v & 0x7) << 16; | ||
2892 | } | ||
2893 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_5_f(u32 v) | ||
2894 | { | ||
2895 | return (v & 0x7) << 20; | ||
2896 | } | ||
2897 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_6_f(u32 v) | ||
2898 | { | ||
2899 | return (v & 0x7) << 24; | ||
2900 | } | ||
2901 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_7_f(u32 v) | ||
2902 | { | ||
2903 | return (v & 0x7) << 28; | ||
2904 | } | ||
2825 | static inline u32 gr_gpcs_gpm_pd_cfg_r(void) | 2905 | static inline u32 gr_gpcs_gpm_pd_cfg_r(void) |
2826 | { | 2906 | { |
2827 | return 0x00418c6c; | 2907 | return 0x00418c6c; |
@@ -2902,6 +2982,90 @@ static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f(void) | |||
2902 | { | 2982 | { |
2903 | return 0x10000000; | 2983 | return 0x10000000; |
2904 | } | 2984 | } |
2985 | static inline u32 gr_gpcs_tpcs_sm1_hww_warp_esr_report_mask_r(void) | ||
2986 | { | ||
2987 | return 0x00419fa8; | ||
2988 | } | ||
2989 | static inline u32 gr_gpcs_tpcs_sm1_hww_warp_esr_report_mask_stack_error_report_f(void) | ||
2990 | { | ||
2991 | return 0x2; | ||
2992 | } | ||
2993 | static inline u32 gr_gpcs_tpcs_sm1_hww_warp_esr_report_mask_api_stack_error_report_f(void) | ||
2994 | { | ||
2995 | return 0x4; | ||
2996 | } | ||
2997 | static inline u32 gr_gpcs_tpcs_sm1_hww_warp_esr_report_mask_pc_wrap_report_f(void) | ||
2998 | { | ||
2999 | return 0x10; | ||
3000 | } | ||
3001 | static inline u32 gr_gpcs_tpcs_sm1_hww_warp_esr_report_mask_misaligned_pc_report_f(void) | ||
3002 | { | ||
3003 | return 0x20; | ||
3004 | } | ||
3005 | static inline u32 gr_gpcs_tpcs_sm1_hww_warp_esr_report_mask_pc_overflow_report_f(void) | ||
3006 | { | ||
3007 | return 0x40; | ||
3008 | } | ||
3009 | static inline u32 gr_gpcs_tpcs_sm1_hww_warp_esr_report_mask_misaligned_reg_report_f(void) | ||
3010 | { | ||
3011 | return 0x100; | ||
3012 | } | ||
3013 | static inline u32 gr_gpcs_tpcs_sm1_hww_warp_esr_report_mask_illegal_instr_encoding_report_f(void) | ||
3014 | { | ||
3015 | return 0x200; | ||
3016 | } | ||
3017 | static inline u32 gr_gpcs_tpcs_sm1_hww_warp_esr_report_mask_illegal_instr_param_report_f(void) | ||
3018 | { | ||
3019 | return 0x800; | ||
3020 | } | ||
3021 | static inline u32 gr_gpcs_tpcs_sm1_hww_warp_esr_report_mask_oor_reg_report_f(void) | ||
3022 | { | ||
3023 | return 0x2000; | ||
3024 | } | ||
3025 | static inline u32 gr_gpcs_tpcs_sm1_hww_warp_esr_report_mask_oor_addr_report_f(void) | ||
3026 | { | ||
3027 | return 0x4000; | ||
3028 | } | ||
3029 | static inline u32 gr_gpcs_tpcs_sm1_hww_warp_esr_report_mask_misaligned_addr_report_f(void) | ||
3030 | { | ||
3031 | return 0x8000; | ||
3032 | } | ||
3033 | static inline u32 gr_gpcs_tpcs_sm1_hww_warp_esr_report_mask_invalid_addr_space_report_f(void) | ||
3034 | { | ||
3035 | return 0x10000; | ||
3036 | } | ||
3037 | static inline u32 gr_gpcs_tpcs_sm1_hww_warp_esr_report_mask_invalid_const_addr_ldc_report_f(void) | ||
3038 | { | ||
3039 | return 0x40000; | ||
3040 | } | ||
3041 | static inline u32 gr_gpcs_tpcs_sm1_hww_warp_esr_report_mask_mmu_fault_report_f(void) | ||
3042 | { | ||
3043 | return 0x800000; | ||
3044 | } | ||
3045 | static inline u32 gr_gpcs_tpcs_sm1_hww_warp_esr_report_mask_stack_overflow_report_f(void) | ||
3046 | { | ||
3047 | return 0x400000; | ||
3048 | } | ||
3049 | static inline u32 gr_gpcs_tpcs_sm1_hww_global_esr_report_mask_r(void) | ||
3050 | { | ||
3051 | return 0x00419fac; | ||
3052 | } | ||
3053 | static inline u32 gr_gpcs_tpcs_sm1_hww_global_esr_report_mask_multiple_warp_errors_report_f(void) | ||
3054 | { | ||
3055 | return 0x4; | ||
3056 | } | ||
3057 | static inline u32 gr_gpcs_tpcs_sm1_hww_global_esr_report_mask_bpt_int_report_f(void) | ||
3058 | { | ||
3059 | return 0x10; | ||
3060 | } | ||
3061 | static inline u32 gr_gpcs_tpcs_sm1_hww_global_esr_report_mask_bpt_pause_report_f(void) | ||
3062 | { | ||
3063 | return 0x20; | ||
3064 | } | ||
3065 | static inline u32 gr_gpcs_tpcs_sm1_hww_global_esr_report_mask_single_step_complete_report_f(void) | ||
3066 | { | ||
3067 | return 0x40; | ||
3068 | } | ||
2905 | static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_r(void) | 3069 | static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_r(void) |
2906 | { | 3070 | { |
2907 | return 0x00419d0c; | 3071 | return 0x00419d0c; |
@@ -2966,13 +3130,117 @@ static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_pending_v(void) | |||
2966 | { | 3130 | { |
2967 | return 0x00000001; | 3131 | return 0x00000001; |
2968 | } | 3132 | } |
2969 | static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_r(void) | 3133 | static inline u32 gr_gpc0_tpc0_sm1_dbgr_control0_r(void) |
2970 | { | 3134 | { |
2971 | return 0x00419e14; | 3135 | return 0x00504784; |
2972 | } | 3136 | } |
2973 | static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_r(void) | 3137 | static inline u32 gr_gpc0_tpc0_sm1_dbgr_control0_debugger_mode_m(void) |
2974 | { | 3138 | { |
2975 | return 0x00504614; | 3139 | return 0x1 << 0; |
3140 | } | ||
3141 | static inline u32 gr_gpc0_tpc0_sm1_dbgr_control0_debugger_mode_v(u32 r) | ||
3142 | { | ||
3143 | return (r >> 0) & 0x1; | ||
3144 | } | ||
3145 | static inline u32 gr_gpc0_tpc0_sm1_dbgr_control0_debugger_mode_on_v(void) | ||
3146 | { | ||
3147 | return 0x00000001; | ||
3148 | } | ||
3149 | static inline u32 gr_gpc0_tpc0_sm1_dbgr_control0_debugger_mode_off_v(void) | ||
3150 | { | ||
3151 | return 0x00000000; | ||
3152 | } | ||
3153 | static inline u32 gr_gpc0_tpc0_sm1_dbgr_control0_stop_trigger_enable_f(void) | ||
3154 | { | ||
3155 | return 0x80000000; | ||
3156 | } | ||
3157 | static inline u32 gr_gpc0_tpc0_sm1_dbgr_control0_stop_trigger_disable_f(void) | ||
3158 | { | ||
3159 | return 0x0; | ||
3160 | } | ||
3161 | static inline u32 gr_gpc0_tpc0_sm1_dbgr_control0_single_step_mode_enable_f(void) | ||
3162 | { | ||
3163 | return 0x8; | ||
3164 | } | ||
3165 | static inline u32 gr_gpc0_tpc0_sm1_dbgr_control0_single_step_mode_disable_f(void) | ||
3166 | { | ||
3167 | return 0x0; | ||
3168 | } | ||
3169 | static inline u32 gr_gpc0_tpc0_sm1_dbgr_control0_run_trigger_task_f(void) | ||
3170 | { | ||
3171 | return 0x40000000; | ||
3172 | } | ||
3173 | static inline u32 gr_gpc0_tpc0_sm1_warp_valid_mask_r(void) | ||
3174 | { | ||
3175 | return 0x00504788; | ||
3176 | } | ||
3177 | static inline u32 gr_gpc0_tpc0_sm1_dbgr_bpt_pause_mask_r(void) | ||
3178 | { | ||
3179 | return 0x00504790; | ||
3180 | } | ||
3181 | static inline u32 gr_gpc0_tpc0_sm1_dbgr_bpt_trap_mask_r(void) | ||
3182 | { | ||
3183 | return 0x00504798; | ||
3184 | } | ||
3185 | static inline u32 gr_gpcs_tpcs_sm1_dbgr_bpt_pause_mask_r(void) | ||
3186 | { | ||
3187 | return 0x00419f90; | ||
3188 | } | ||
3189 | static inline u32 gr_gpc0_tpc0_sm1_dbgr_status0_r(void) | ||
3190 | { | ||
3191 | return 0x00504780; | ||
3192 | } | ||
3193 | static inline u32 gr_gpc0_tpc0_sm1_dbgr_status0_sm_in_trap_mode_v(u32 r) | ||
3194 | { | ||
3195 | return (r >> 0) & 0x1; | ||
3196 | } | ||
3197 | static inline u32 gr_gpc0_tpc0_sm1_dbgr_status0_locked_down_v(u32 r) | ||
3198 | { | ||
3199 | return (r >> 4) & 0x1; | ||
3200 | } | ||
3201 | static inline u32 gr_gpc0_tpc0_sm1_dbgr_status0_locked_down_true_v(void) | ||
3202 | { | ||
3203 | return 0x00000001; | ||
3204 | } | ||
3205 | static inline u32 gr_gpcs_tpcs_sm1_hww_global_esr_r(void) | ||
3206 | { | ||
3207 | return 0x00419fb4; | ||
3208 | } | ||
3209 | static inline u32 gr_gpcs_tpcs_sm1_hww_global_esr_bpt_int_pending_f(void) | ||
3210 | { | ||
3211 | return 0x10; | ||
3212 | } | ||
3213 | static inline u32 gr_gpcs_tpcs_sm1_hww_global_esr_bpt_pause_pending_f(void) | ||
3214 | { | ||
3215 | return 0x20; | ||
3216 | } | ||
3217 | static inline u32 gr_gpcs_tpcs_sm1_hww_global_esr_single_step_complete_pending_f(void) | ||
3218 | { | ||
3219 | return 0x40; | ||
3220 | } | ||
3221 | static inline u32 gr_gpcs_tpcs_sm1_hww_global_esr_multiple_warp_errors_pending_f(void) | ||
3222 | { | ||
3223 | return 0x4; | ||
3224 | } | ||
3225 | static inline u32 gr_gpc0_tpc0_sm1_hww_global_esr_r(void) | ||
3226 | { | ||
3227 | return 0x005047b4; | ||
3228 | } | ||
3229 | static inline u32 gr_gpc0_tpc0_sm1_hww_global_esr_bpt_int_pending_f(void) | ||
3230 | { | ||
3231 | return 0x10; | ||
3232 | } | ||
3233 | static inline u32 gr_gpc0_tpc0_sm1_hww_global_esr_bpt_pause_pending_f(void) | ||
3234 | { | ||
3235 | return 0x20; | ||
3236 | } | ||
3237 | static inline u32 gr_gpc0_tpc0_sm1_hww_global_esr_single_step_complete_pending_f(void) | ||
3238 | { | ||
3239 | return 0x40; | ||
3240 | } | ||
3241 | static inline u32 gr_gpc0_tpc0_sm1_hww_global_esr_multiple_warp_errors_pending_f(void) | ||
3242 | { | ||
3243 | return 0x4; | ||
2976 | } | 3244 | } |
2977 | static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_r(void) | 3245 | static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_r(void) |
2978 | { | 3246 | { |
@@ -2990,6 +3258,38 @@ static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_ecc_ded_pending_f(void) | |||
2990 | { | 3258 | { |
2991 | return 0x100; | 3259 | return 0x100; |
2992 | } | 3260 | } |
3261 | static inline u32 gr_gpc0_tpc0_sm1_hww_warp_esr_r(void) | ||
3262 | { | ||
3263 | return 0x005047b0; | ||
3264 | } | ||
3265 | static inline u32 gr_gpc0_tpc0_sm1_hww_warp_esr_error_v(u32 r) | ||
3266 | { | ||
3267 | return (r >> 0) & 0xffff; | ||
3268 | } | ||
3269 | static inline u32 gr_gpc0_tpc0_sm1_hww_warp_esr_error_none_v(void) | ||
3270 | { | ||
3271 | return 0x00000000; | ||
3272 | } | ||
3273 | static inline u32 gr_gpc0_tpc0_sm1_hww_warp_esr_error_none_f(void) | ||
3274 | { | ||
3275 | return 0x0; | ||
3276 | } | ||
3277 | static inline u32 gr_gpc0_tpc0_sm1_hww_warp_esr_addr_valid_m(void) | ||
3278 | { | ||
3279 | return 0x1 << 24; | ||
3280 | } | ||
3281 | static inline u32 gr_gpc0_tpc0_sm1_hww_warp_esr_addr_error_type_m(void) | ||
3282 | { | ||
3283 | return 0x7 << 25; | ||
3284 | } | ||
3285 | static inline u32 gr_gpc0_tpc0_sm1_hww_warp_esr_addr_error_type_none_f(void) | ||
3286 | { | ||
3287 | return 0x0; | ||
3288 | } | ||
3289 | static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_pc_r(void) | ||
3290 | { | ||
3291 | return 0x005047b8; | ||
3292 | } | ||
2993 | static inline u32 gr_gpc0_tpc0_sm_halfctl_ctrl_r(void) | 3293 | static inline u32 gr_gpc0_tpc0_sm_halfctl_ctrl_r(void) |
2994 | { | 3294 | { |
2995 | return 0x005043a0; | 3295 | return 0x005043a0; |
@@ -3030,6 +3330,10 @@ static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_fast_mode_switch_true_f(void) | |||
3030 | { | 3330 | { |
3031 | return 0x4; | 3331 | return 0x4; |
3032 | } | 3332 | } |
3333 | static inline u32 gr_ppcs_wwdx_map_gpc_map_r(u32 i) | ||
3334 | { | ||
3335 | return 0x0041bf00 + i*4; | ||
3336 | } | ||
3033 | static inline u32 gr_ppcs_wwdx_map_table_cfg_r(void) | 3337 | static inline u32 gr_ppcs_wwdx_map_table_cfg_r(void) |
3034 | { | 3338 | { |
3035 | return 0x0041bfd0; | 3339 | return 0x0041bfd0; |
@@ -3166,6 +3470,14 @@ static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter7_control_r(void) | |||
3166 | { | 3470 | { |
3167 | return 0x00504394; | 3471 | return 0x00504394; |
3168 | } | 3472 | } |
3473 | static inline u32 gr_pri_gpc0_tpc0_sm1_dsm_perf_counter_status_s1_r(void) | ||
3474 | { | ||
3475 | return 0x005047c4; | ||
3476 | } | ||
3477 | static inline u32 gr_pri_gpc0_tpc0_sm1_dsm_perf_counter_status1_r(void) | ||
3478 | { | ||
3479 | return 0x005047d0; | ||
3480 | } | ||
3169 | static inline u32 gr_fe_pwr_mode_r(void) | 3481 | static inline u32 gr_fe_pwr_mode_r(void) |
3170 | { | 3482 | { |
3171 | return 0x00404170; | 3483 | return 0x00404170; |
@@ -3262,6 +3574,58 @@ static inline u32 gr_gpcs_mmu_num_active_ltcs_r(void) | |||
3262 | { | 3574 | { |
3263 | return 0x004188ac; | 3575 | return 0x004188ac; |
3264 | } | 3576 | } |
3577 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_r(void) | ||
3578 | { | ||
3579 | return 0x00419f84; | ||
3580 | } | ||
3581 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_f(u32 v) | ||
3582 | { | ||
3583 | return (v & 0x1) << 0; | ||
3584 | } | ||
3585 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_on_v(void) | ||
3586 | { | ||
3587 | return 0x00000001; | ||
3588 | } | ||
3589 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_m(void) | ||
3590 | { | ||
3591 | return 0x1 << 31; | ||
3592 | } | ||
3593 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_v(u32 r) | ||
3594 | { | ||
3595 | return (r >> 31) & 0x1; | ||
3596 | } | ||
3597 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_enable_f(void) | ||
3598 | { | ||
3599 | return 0x80000000; | ||
3600 | } | ||
3601 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_disable_f(void) | ||
3602 | { | ||
3603 | return 0x0; | ||
3604 | } | ||
3605 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_m(void) | ||
3606 | { | ||
3607 | return 0x1 << 3; | ||
3608 | } | ||
3609 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_enable_f(void) | ||
3610 | { | ||
3611 | return 0x8; | ||
3612 | } | ||
3613 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_disable_f(void) | ||
3614 | { | ||
3615 | return 0x0; | ||
3616 | } | ||
3617 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_m(void) | ||
3618 | { | ||
3619 | return 0x1 << 30; | ||
3620 | } | ||
3621 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_v(u32 r) | ||
3622 | { | ||
3623 | return (r >> 30) & 0x1; | ||
3624 | } | ||
3625 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_task_f(void) | ||
3626 | { | ||
3627 | return 0x40000000; | ||
3628 | } | ||
3265 | static inline u32 gr_fe_gfxp_wfi_timeout_r(void) | 3629 | static inline u32 gr_fe_gfxp_wfi_timeout_r(void) |
3266 | { | 3630 | { |
3267 | return 0x004041c0; | 3631 | return 0x004041c0; |
diff --git a/drivers/gpu/nvgpu/gv11b/hw_mc_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_mc_gv11b.h index 7fe4d158..98bec43a 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_mc_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_mc_gv11b.h | |||
@@ -78,6 +78,10 @@ static inline u32 mc_intr_pfifo_pending_f(void) | |||
78 | { | 78 | { |
79 | return 0x100; | 79 | return 0x100; |
80 | } | 80 | } |
81 | static inline u32 mc_intr_hub_pending_f(void) | ||
82 | { | ||
83 | return 0x200; | ||
84 | } | ||
81 | static inline u32 mc_intr_pgraph_pending_f(void) | 85 | static inline u32 mc_intr_pgraph_pending_f(void) |
82 | { | 86 | { |
83 | return 0x1000; | 87 | return 0x1000; |