diff options
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hw_ctxsw_prog_gp10b.h | 68 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hw_fb_gp10b.h | 32 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h | 20 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hw_fuse_gp10b.h | 44 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h | 228 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h | 250 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hw_mc_gp10b.h | 50 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hw_pbdma_gp10b.h | 20 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hw_pwr_gp10b.h | 12 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h | 62 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hw_therm_gp10b.h | 72 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hw_trim_gp10b.h | 289 |
13 files changed, 662 insertions, 487 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/hw_ctxsw_prog_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_ctxsw_prog_gp10b.h index 6339cf5b..79890f3c 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_ctxsw_prog_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_ctxsw_prog_gp10b.h | |||
@@ -90,13 +90,25 @@ static inline u32 ctxsw_prog_main_image_pm_o(void) | |||
90 | { | 90 | { |
91 | return 0x00000028; | 91 | return 0x00000028; |
92 | } | 92 | } |
93 | static inline u32 ctxsw_prog_main_image_pm_mode_v(u32 r) | 93 | static inline u32 ctxsw_prog_main_image_pm_mode_m(void) |
94 | { | 94 | { |
95 | return (r >> 0) & 0x7; | 95 | return 0x7 << 0; |
96 | } | 96 | } |
97 | static inline u32 ctxsw_prog_main_image_pm_mode_no_ctxsw_v(void) | 97 | static inline u32 ctxsw_prog_main_image_pm_mode_no_ctxsw_f(void) |
98 | { | 98 | { |
99 | return 0x00000000; | 99 | return 0x0; |
100 | } | ||
101 | static inline u32 ctxsw_prog_main_image_pm_smpc_mode_m(void) | ||
102 | { | ||
103 | return 0x7 << 3; | ||
104 | } | ||
105 | static inline u32 ctxsw_prog_main_image_pm_smpc_mode_ctxsw_f(void) | ||
106 | { | ||
107 | return 0x8; | ||
108 | } | ||
109 | static inline u32 ctxsw_prog_main_image_pm_smpc_mode_no_ctxsw_f(void) | ||
110 | { | ||
111 | return 0x0; | ||
100 | } | 112 | } |
101 | static inline u32 ctxsw_prog_main_image_pm_ptr_o(void) | 113 | static inline u32 ctxsw_prog_main_image_pm_ptr_o(void) |
102 | { | 114 | { |
@@ -178,4 +190,52 @@ static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_control_register_strid | |||
178 | { | 190 | { |
179 | return 0x00000002; | 191 | return 0x00000002; |
180 | } | 192 | } |
193 | static inline u32 ctxsw_prog_main_image_priv_access_map_config_o(void) | ||
194 | { | ||
195 | return 0x000000a0; | ||
196 | } | ||
197 | static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_s(void) | ||
198 | { | ||
199 | return 2; | ||
200 | } | ||
201 | static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_f(u32 v) | ||
202 | { | ||
203 | return (v & 0x3) << 0; | ||
204 | } | ||
205 | static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_m(void) | ||
206 | { | ||
207 | return 0x3 << 0; | ||
208 | } | ||
209 | static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_v(u32 r) | ||
210 | { | ||
211 | return (r >> 0) & 0x3; | ||
212 | } | ||
213 | static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_allow_all_f(void) | ||
214 | { | ||
215 | return 0x0; | ||
216 | } | ||
217 | static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_use_map_f(void) | ||
218 | { | ||
219 | return 0x2; | ||
220 | } | ||
221 | static inline u32 ctxsw_prog_main_image_priv_access_map_addr_lo_o(void) | ||
222 | { | ||
223 | return 0x000000a4; | ||
224 | } | ||
225 | static inline u32 ctxsw_prog_main_image_priv_access_map_addr_hi_o(void) | ||
226 | { | ||
227 | return 0x000000a8; | ||
228 | } | ||
229 | static inline u32 ctxsw_prog_main_image_misc_options_o(void) | ||
230 | { | ||
231 | return 0x0000003c; | ||
232 | } | ||
233 | static inline u32 ctxsw_prog_main_image_misc_options_verif_features_m(void) | ||
234 | { | ||
235 | return 0x1 << 3; | ||
236 | } | ||
237 | static inline u32 ctxsw_prog_main_image_misc_options_verif_features_disabled_f(void) | ||
238 | { | ||
239 | return 0x0; | ||
240 | } | ||
181 | #endif | 241 | #endif |
diff --git a/drivers/gpu/nvgpu/gp10b/hw_fb_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_fb_gp10b.h index 9dacabce..d2ecdce1 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_fb_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_fb_gp10b.h | |||
@@ -66,6 +66,10 @@ static inline u32 fb_mmu_ctrl_vm_pg_size_128kb_f(void) | |||
66 | { | 66 | { |
67 | return 0x0; | 67 | return 0x0; |
68 | } | 68 | } |
69 | static inline u32 fb_mmu_ctrl_vm_pg_size_64kb_f(void) | ||
70 | { | ||
71 | return 0x1; | ||
72 | } | ||
69 | static inline u32 fb_mmu_ctrl_pri_fifo_empty_v(u32 r) | 73 | static inline u32 fb_mmu_ctrl_pri_fifo_empty_v(u32 r) |
70 | { | 74 | { |
71 | return (r >> 15) & 0x1; | 75 | return (r >> 15) & 0x1; |
@@ -78,6 +82,22 @@ static inline u32 fb_mmu_ctrl_pri_fifo_space_v(u32 r) | |||
78 | { | 82 | { |
79 | return (r >> 16) & 0xff; | 83 | return (r >> 16) & 0xff; |
80 | } | 84 | } |
85 | static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_v(u32 r) | ||
86 | { | ||
87 | return (r >> 11) & 0x1; | ||
88 | } | ||
89 | static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_true_f(void) | ||
90 | { | ||
91 | return 0x800; | ||
92 | } | ||
93 | static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_false_f(void) | ||
94 | { | ||
95 | return 0x0; | ||
96 | } | ||
97 | static inline u32 fb_priv_mmu_phy_secure_r(void) | ||
98 | { | ||
99 | return 0x00100ce4; | ||
100 | } | ||
81 | static inline u32 fb_mmu_invalidate_pdb_r(void) | 101 | static inline u32 fb_mmu_invalidate_pdb_r(void) |
82 | { | 102 | { |
83 | return 0x00100cb8; | 103 | return 0x00100cb8; |
@@ -158,9 +178,9 @@ static inline u32 fb_mmu_debug_wr_vol_true_f(void) | |||
158 | { | 178 | { |
159 | return 0x4; | 179 | return 0x4; |
160 | } | 180 | } |
161 | static inline u32 fb_mmu_debug_wr_addr_v(u32 r) | 181 | static inline u32 fb_mmu_debug_wr_addr_f(u32 v) |
162 | { | 182 | { |
163 | return (r >> 4) & 0xfffffff; | 183 | return (v & 0xfffffff) << 4; |
164 | } | 184 | } |
165 | static inline u32 fb_mmu_debug_wr_addr_alignment_v(void) | 185 | static inline u32 fb_mmu_debug_wr_addr_alignment_v(void) |
166 | { | 186 | { |
@@ -178,9 +198,9 @@ static inline u32 fb_mmu_debug_rd_vol_false_f(void) | |||
178 | { | 198 | { |
179 | return 0x0; | 199 | return 0x0; |
180 | } | 200 | } |
181 | static inline u32 fb_mmu_debug_rd_addr_v(u32 r) | 201 | static inline u32 fb_mmu_debug_rd_addr_f(u32 v) |
182 | { | 202 | { |
183 | return (r >> 4) & 0xfffffff; | 203 | return (v & 0xfffffff) << 4; |
184 | } | 204 | } |
185 | static inline u32 fb_mmu_debug_rd_addr_alignment_v(void) | 205 | static inline u32 fb_mmu_debug_rd_addr_alignment_v(void) |
186 | { | 206 | { |
@@ -202,10 +222,6 @@ static inline u32 fb_mmu_vpr_info_r(void) | |||
202 | { | 222 | { |
203 | return 0x00100cd0; | 223 | return 0x00100cd0; |
204 | } | 224 | } |
205 | static inline u32 fb_mmu_vpr_info_fetch_f(u32 v) | ||
206 | { | ||
207 | return (v & 0x1) << 2; | ||
208 | } | ||
209 | static inline u32 fb_mmu_vpr_info_fetch_v(u32 r) | 225 | static inline u32 fb_mmu_vpr_info_fetch_v(u32 r) |
210 | { | 226 | { |
211 | return (r >> 2) & 0x1; | 227 | return (r >> 2) & 0x1; |
diff --git a/drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h index 764c1b6c..b79758d2 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h | |||
@@ -206,6 +206,10 @@ static inline u32 fifo_intr_en_0_r(void) | |||
206 | { | 206 | { |
207 | return 0x00002140; | 207 | return 0x00002140; |
208 | } | 208 | } |
209 | static inline u32 fifo_intr_en_0_sched_error_m(void) | ||
210 | { | ||
211 | return 0x1 << 8; | ||
212 | } | ||
209 | static inline u32 fifo_intr_en_1_r(void) | 213 | static inline u32 fifo_intr_en_1_r(void) |
210 | { | 214 | { |
211 | return 0x00002528; | 215 | return 0x00002528; |
@@ -346,10 +350,18 @@ static inline u32 fifo_preempt_type_channel_f(void) | |||
346 | { | 350 | { |
347 | return 0x0; | 351 | return 0x0; |
348 | } | 352 | } |
353 | static inline u32 fifo_preempt_type_tsg_f(void) | ||
354 | { | ||
355 | return 0x1000000; | ||
356 | } | ||
349 | static inline u32 fifo_preempt_chid_f(u32 v) | 357 | static inline u32 fifo_preempt_chid_f(u32 v) |
350 | { | 358 | { |
351 | return (v & 0xfff) << 0; | 359 | return (v & 0xfff) << 0; |
352 | } | 360 | } |
361 | static inline u32 fifo_preempt_id_f(u32 v) | ||
362 | { | ||
363 | return (v & 0xfff) << 0; | ||
364 | } | ||
353 | static inline u32 fifo_trigger_mmu_fault_r(u32 i) | 365 | static inline u32 fifo_trigger_mmu_fault_r(u32 i) |
354 | { | 366 | { |
355 | return 0x00002a30 + i*4; | 367 | return 0x00002a30 + i*4; |
@@ -382,6 +394,10 @@ static inline u32 fifo_engine_status_id_type_chid_v(void) | |||
382 | { | 394 | { |
383 | return 0x00000000; | 395 | return 0x00000000; |
384 | } | 396 | } |
397 | static inline u32 fifo_engine_status_id_type_tsgid_v(void) | ||
398 | { | ||
399 | return 0x00000001; | ||
400 | } | ||
385 | static inline u32 fifo_engine_status_ctx_status_v(u32 r) | 401 | static inline u32 fifo_engine_status_ctx_status_v(u32 r) |
386 | { | 402 | { |
387 | return (r >> 13) & 0x7; | 403 | return (r >> 13) & 0x7; |
@@ -466,6 +482,10 @@ static inline u32 fifo_pbdma_status_id_type_chid_v(void) | |||
466 | { | 482 | { |
467 | return 0x00000000; | 483 | return 0x00000000; |
468 | } | 484 | } |
485 | static inline u32 fifo_pbdma_status_id_type_tsgid_v(void) | ||
486 | { | ||
487 | return 0x00000001; | ||
488 | } | ||
469 | static inline u32 fifo_pbdma_status_chan_status_v(u32 r) | 489 | static inline u32 fifo_pbdma_status_chan_status_v(u32 r) |
470 | { | 490 | { |
471 | return (r >> 13) & 0x7; | 491 | return (r >> 13) & 0x7; |
diff --git a/drivers/gpu/nvgpu/gp10b/hw_fuse_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_fuse_gp10b.h index 00291d30..272f7fb3 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_fuse_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_fuse_gp10b.h | |||
@@ -54,4 +54,48 @@ static inline u32 fuse_status_opt_tpc_gpc_r(u32 i) | |||
54 | { | 54 | { |
55 | return 0x00021c38 + i*4; | 55 | return 0x00021c38 + i*4; |
56 | } | 56 | } |
57 | static inline u32 fuse_ctrl_opt_tpc_gpc_r(u32 i) | ||
58 | { | ||
59 | return 0x00021838 + i*4; | ||
60 | } | ||
61 | static inline u32 fuse_ctrl_opt_ram_svop_pdp_r(void) | ||
62 | { | ||
63 | return 0x00021944; | ||
64 | } | ||
65 | static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_f(u32 v) | ||
66 | { | ||
67 | return (v & 0x3) << 0; | ||
68 | } | ||
69 | static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_m(void) | ||
70 | { | ||
71 | return 0x3 << 0; | ||
72 | } | ||
73 | static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_v(u32 r) | ||
74 | { | ||
75 | return (r >> 0) & 0x3; | ||
76 | } | ||
77 | static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_r(void) | ||
78 | { | ||
79 | return 0x00021948; | ||
80 | } | ||
81 | static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_f(u32 v) | ||
82 | { | ||
83 | return (v & 0x1) << 0; | ||
84 | } | ||
85 | static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_m(void) | ||
86 | { | ||
87 | return 0x1 << 0; | ||
88 | } | ||
89 | static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_v(u32 r) | ||
90 | { | ||
91 | return (r >> 0) & 0x1; | ||
92 | } | ||
93 | static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_yes_f(void) | ||
94 | { | ||
95 | return 0x1; | ||
96 | } | ||
97 | static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_no_f(void) | ||
98 | { | ||
99 | return 0x0; | ||
100 | } | ||
57 | #endif | 101 | #endif |
diff --git a/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h index f6020434..161c1ce0 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h | |||
@@ -200,7 +200,7 @@ static inline u32 gmmu_pte_read_disable_true_f(void) | |||
200 | } | 200 | } |
201 | static inline u32 gmmu_pte_comptagline_f(u32 v) | 201 | static inline u32 gmmu_pte_comptagline_f(u32 v) |
202 | { | 202 | { |
203 | return (v & 0x3ffff) << 12; | 203 | return (v & 0x1ffff) << 12; |
204 | } | 204 | } |
205 | static inline u32 gmmu_pte_comptagline_w(void) | 205 | static inline u32 gmmu_pte_comptagline_w(void) |
206 | { | 206 | { |
diff --git a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h index 03164957..f8607618 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h | |||
@@ -78,6 +78,26 @@ static inline u32 gr_intr_illegal_method_reset_f(void) | |||
78 | { | 78 | { |
79 | return 0x10; | 79 | return 0x10; |
80 | } | 80 | } |
81 | static inline u32 gr_intr_illegal_notify_pending_f(void) | ||
82 | { | ||
83 | return 0x40; | ||
84 | } | ||
85 | static inline u32 gr_intr_illegal_notify_reset_f(void) | ||
86 | { | ||
87 | return 0x40; | ||
88 | } | ||
89 | static inline u32 gr_intr_firmware_method_f(u32 v) | ||
90 | { | ||
91 | return (v & 0x1) << 8; | ||
92 | } | ||
93 | static inline u32 gr_intr_firmware_method_pending_f(void) | ||
94 | { | ||
95 | return 0x100; | ||
96 | } | ||
97 | static inline u32 gr_intr_firmware_method_reset_f(void) | ||
98 | { | ||
99 | return 0x100; | ||
100 | } | ||
81 | static inline u32 gr_intr_illegal_class_pending_f(void) | 101 | static inline u32 gr_intr_illegal_class_pending_f(void) |
82 | { | 102 | { |
83 | return 0x20; | 103 | return 0x20; |
@@ -86,6 +106,14 @@ static inline u32 gr_intr_illegal_class_reset_f(void) | |||
86 | { | 106 | { |
87 | return 0x20; | 107 | return 0x20; |
88 | } | 108 | } |
109 | static inline u32 gr_intr_fecs_error_pending_f(void) | ||
110 | { | ||
111 | return 0x80000; | ||
112 | } | ||
113 | static inline u32 gr_intr_fecs_error_reset_f(void) | ||
114 | { | ||
115 | return 0x80000; | ||
116 | } | ||
89 | static inline u32 gr_intr_class_error_pending_f(void) | 117 | static inline u32 gr_intr_class_error_pending_f(void) |
90 | { | 118 | { |
91 | return 0x100000; | 119 | return 0x100000; |
@@ -102,6 +130,26 @@ static inline u32 gr_intr_exception_reset_f(void) | |||
102 | { | 130 | { |
103 | return 0x200000; | 131 | return 0x200000; |
104 | } | 132 | } |
133 | static inline u32 gr_fecs_intr_r(void) | ||
134 | { | ||
135 | return 0x00400144; | ||
136 | } | ||
137 | static inline u32 gr_class_error_r(void) | ||
138 | { | ||
139 | return 0x00400110; | ||
140 | } | ||
141 | static inline u32 gr_class_error_code_v(u32 r) | ||
142 | { | ||
143 | return (r >> 0) & 0xffff; | ||
144 | } | ||
145 | static inline u32 gr_intr_nonstall_r(void) | ||
146 | { | ||
147 | return 0x00400120; | ||
148 | } | ||
149 | static inline u32 gr_intr_nonstall_trap_pending_f(void) | ||
150 | { | ||
151 | return 0x2; | ||
152 | } | ||
105 | static inline u32 gr_intr_en_r(void) | 153 | static inline u32 gr_intr_en_r(void) |
106 | { | 154 | { |
107 | return 0x0040013c; | 155 | return 0x0040013c; |
@@ -198,6 +246,10 @@ static inline u32 gr_status_r(void) | |||
198 | { | 246 | { |
199 | return 0x00400700; | 247 | return 0x00400700; |
200 | } | 248 | } |
249 | static inline u32 gr_status_fe_method_upper_v(u32 r) | ||
250 | { | ||
251 | return (r >> 1) & 0x1; | ||
252 | } | ||
201 | static inline u32 gr_status_fe_method_lower_v(u32 r) | 253 | static inline u32 gr_status_fe_method_lower_v(u32 r) |
202 | { | 254 | { |
203 | return (r >> 2) & 0x1; | 255 | return (r >> 2) & 0x1; |
@@ -206,6 +258,10 @@ static inline u32 gr_status_fe_method_lower_idle_v(void) | |||
206 | { | 258 | { |
207 | return 0x00000000; | 259 | return 0x00000000; |
208 | } | 260 | } |
261 | static inline u32 gr_status_fe_gi_v(u32 r) | ||
262 | { | ||
263 | return (r >> 21) & 0x1; | ||
264 | } | ||
209 | static inline u32 gr_status_mask_r(void) | 265 | static inline u32 gr_status_mask_r(void) |
210 | { | 266 | { |
211 | return 0x00400610; | 267 | return 0x00400610; |
@@ -662,6 +718,22 @@ static inline u32 gr_fecs_method_push_adr_set_watchdog_timeout_f(void) | |||
662 | { | 718 | { |
663 | return 0x21; | 719 | return 0x21; |
664 | } | 720 | } |
721 | static inline u32 gr_fecs_host_int_status_r(void) | ||
722 | { | ||
723 | return 0x00409c18; | ||
724 | } | ||
725 | static inline u32 gr_fecs_host_int_status_umimp_firmware_method_f(u32 v) | ||
726 | { | ||
727 | return (v & 0x1) << 17; | ||
728 | } | ||
729 | static inline u32 gr_fecs_host_int_status_umimp_illegal_method_f(u32 v) | ||
730 | { | ||
731 | return (v & 0x1) << 18; | ||
732 | } | ||
733 | static inline u32 gr_fecs_host_int_clear_r(void) | ||
734 | { | ||
735 | return 0x00409c20; | ||
736 | } | ||
665 | static inline u32 gr_fecs_host_int_enable_r(void) | 737 | static inline u32 gr_fecs_host_int_enable_r(void) |
666 | { | 738 | { |
667 | return 0x00409c24; | 739 | return 0x00409c24; |
@@ -1292,15 +1364,19 @@ static inline u32 gr_ds_zbc_tbl_ld_trigger_active_f(void) | |||
1292 | } | 1364 | } |
1293 | static inline u32 gr_ds_tga_constraintlogic_r(void) | 1365 | static inline u32 gr_ds_tga_constraintlogic_r(void) |
1294 | { | 1366 | { |
1295 | return 0xffffffff; | 1367 | return 0x00405830; |
1296 | } | 1368 | } |
1297 | static inline u32 gr_ds_tga_constraintlogic_beta_cbsize_f(u32 v) | 1369 | static inline u32 gr_ds_tga_constraintlogic_beta_cbsize_f(u32 v) |
1298 | { | 1370 | { |
1299 | return (v & 0x1) << -1; | 1371 | return (v & 0x3fffff) << 0; |
1372 | } | ||
1373 | static inline u32 gr_ds_tga_constraintlogic_r(void) | ||
1374 | { | ||
1375 | return 0x0040585c; | ||
1300 | } | 1376 | } |
1301 | static inline u32 gr_ds_tga_constraintlogic_alpha_cbsize_f(u32 v) | 1377 | static inline u32 gr_ds_tga_constraintlogic_alpha_cbsize_f(u32 v) |
1302 | { | 1378 | { |
1303 | return (v & 0x1) << -1; | 1379 | return (v & 0xffff) << 0; |
1304 | } | 1380 | } |
1305 | static inline u32 gr_ds_hww_esr_r(void) | 1381 | static inline u32 gr_ds_hww_esr_r(void) |
1306 | { | 1382 | { |
@@ -1674,6 +1750,34 @@ static inline u32 gr_gpccs_rc_lanes_num_chains_v(u32 r) | |||
1674 | { | 1750 | { |
1675 | return (r >> 0) & 0x3f; | 1751 | return (r >> 0) & 0x3f; |
1676 | } | 1752 | } |
1753 | static inline u32 gr_gpccs_rc_lane_size_r(void) | ||
1754 | { | ||
1755 | return 0x00502910; | ||
1756 | } | ||
1757 | static inline u32 gr_gpccs_rc_lane_size_v_s(void) | ||
1758 | { | ||
1759 | return 24; | ||
1760 | } | ||
1761 | static inline u32 gr_gpccs_rc_lane_size_v_f(u32 v) | ||
1762 | { | ||
1763 | return (v & 0xffffff) << 0; | ||
1764 | } | ||
1765 | static inline u32 gr_gpccs_rc_lane_size_v_m(void) | ||
1766 | { | ||
1767 | return 0xffffff << 0; | ||
1768 | } | ||
1769 | static inline u32 gr_gpccs_rc_lane_size_v_v(u32 r) | ||
1770 | { | ||
1771 | return (r >> 0) & 0xffffff; | ||
1772 | } | ||
1773 | static inline u32 gr_gpccs_rc_lane_size_v_0_v(void) | ||
1774 | { | ||
1775 | return 0x00000000; | ||
1776 | } | ||
1777 | static inline u32 gr_gpccs_rc_lane_size_v_0_f(void) | ||
1778 | { | ||
1779 | return 0x0; | ||
1780 | } | ||
1677 | static inline u32 gr_gpc0_zcull_fs_r(void) | 1781 | static inline u32 gr_gpc0_zcull_fs_r(void) |
1678 | { | 1782 | { |
1679 | return 0x00500910; | 1783 | return 0x00500910; |
@@ -2068,19 +2172,11 @@ static inline u32 gr_gpcs_swdx_tc_beta_cb_size_r(u32 i) | |||
2068 | } | 2172 | } |
2069 | static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_f(u32 v) | 2173 | static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_f(u32 v) |
2070 | { | 2174 | { |
2071 | return (v & 0xffffffff) << -1; | 2175 | return (v & 0x3fffff) << 0; |
2072 | } | 2176 | } |
2073 | static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_m(void) | 2177 | static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_m(void) |
2074 | { | 2178 | { |
2075 | return 0xffffffff << -1; | 2179 | return 0x3fffff << 0; |
2076 | } | ||
2077 | static inline u32 gr_gpcs_swdx_tc_beta_cb_size_div3_f(u32 v) | ||
2078 | { | ||
2079 | return (v & 0xffffffff) << -1; | ||
2080 | } | ||
2081 | static inline u32 gr_gpcs_swdx_tc_beta_cb_size_div3_m(void) | ||
2082 | { | ||
2083 | return 0xffffffff << -1; | ||
2084 | } | 2180 | } |
2085 | static inline u32 gr_gpcs_swdx_rm_pagepool_r(void) | 2181 | static inline u32 gr_gpcs_swdx_rm_pagepool_r(void) |
2086 | { | 2182 | { |
@@ -2526,26 +2622,6 @@ static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f(void) | |||
2526 | { | 2622 | { |
2527 | return 0x10000000; | 2623 | return 0x10000000; |
2528 | } | 2624 | } |
2529 | static inline u32 gr_gpcs_tpcs_sm_pm_ctrl_r(void) | ||
2530 | { | ||
2531 | return 0x00419e00; | ||
2532 | } | ||
2533 | static inline u32 gr_gpcs_tpcs_sm_pm_ctrl_core_enable_m(void) | ||
2534 | { | ||
2535 | return 0x1 << 7; | ||
2536 | } | ||
2537 | static inline u32 gr_gpcs_tpcs_sm_pm_ctrl_core_enable_enable_f(void) | ||
2538 | { | ||
2539 | return 0x80; | ||
2540 | } | ||
2541 | static inline u32 gr_gpcs_tpcs_sm_pm_ctrl_qctl_enable_m(void) | ||
2542 | { | ||
2543 | return 0x1 << 15; | ||
2544 | } | ||
2545 | static inline u32 gr_gpcs_tpcs_sm_pm_ctrl_qctl_enable_enable_f(void) | ||
2546 | { | ||
2547 | return 0x8000; | ||
2548 | } | ||
2549 | static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_r(void) | 2625 | static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_r(void) |
2550 | { | 2626 | { |
2551 | return 0x00419e44; | 2627 | return 0x00419e44; |
@@ -2670,51 +2746,51 @@ static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_single_step_complet | |||
2670 | { | 2746 | { |
2671 | return 0x40; | 2747 | return 0x40; |
2672 | } | 2748 | } |
2673 | static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_r(void) | 2749 | static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_r(void) |
2674 | { | 2750 | { |
2675 | return 0x0050450c; | 2751 | return 0x00419d0c; |
2676 | } | 2752 | } |
2677 | static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f(void) | 2753 | static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_sm_enabled_f(void) |
2678 | { | 2754 | { |
2679 | return 0x2; | 2755 | return 0x2; |
2680 | } | 2756 | } |
2681 | static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_disabled_f(void) | 2757 | static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_r(void) |
2682 | { | 2758 | { |
2683 | return 0x0; | 2759 | return 0x0050450c; |
2684 | } | 2760 | } |
2685 | static inline u32 gr_gpc0_gpccs_gpc_exception_en_r(void) | 2761 | static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f(void) |
2686 | { | 2762 | { |
2687 | return 0x00502c94; | 2763 | return 0x2; |
2688 | } | 2764 | } |
2689 | static inline u32 gr_gpc0_gpccs_gpc_exception_en_tpc_0_enabled_f(void) | 2765 | static inline u32 gr_gpcs_gpccs_gpc_exception_en_r(void) |
2690 | { | 2766 | { |
2691 | return 0x10000; | 2767 | return 0x0041ac94; |
2692 | } | 2768 | } |
2693 | static inline u32 gr_gpc0_gpccs_gpc_exception_en_tpc_0_disabled_f(void) | 2769 | static inline u32 gr_gpcs_gpccs_gpc_exception_en_tpc_f(u32 v) |
2694 | { | 2770 | { |
2695 | return 0x0; | 2771 | return (v & 0xff) << 16; |
2696 | } | 2772 | } |
2697 | static inline u32 gr_gpcs_gpccs_gpc_exception_r(void) | 2773 | static inline u32 gr_gpc0_gpccs_gpc_exception_r(void) |
2698 | { | 2774 | { |
2699 | return 0x0041ac90; | 2775 | return 0x00502c90; |
2700 | } | 2776 | } |
2701 | static inline u32 gr_gpcs_gpccs_gpc_exception_tpc_v(u32 r) | 2777 | static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_v(u32 r) |
2702 | { | 2778 | { |
2703 | return (r >> 16) & 0xff; | 2779 | return (r >> 16) & 0xff; |
2704 | } | 2780 | } |
2705 | static inline u32 gr_gpcs_gpccs_gpc_exception_tpc_0_pending_v(void) | 2781 | static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_0_pending_v(void) |
2706 | { | 2782 | { |
2707 | return 0x00000001; | 2783 | return 0x00000001; |
2708 | } | 2784 | } |
2709 | static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_r(void) | 2785 | static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_r(void) |
2710 | { | 2786 | { |
2711 | return 0x00419d08; | 2787 | return 0x00504508; |
2712 | } | 2788 | } |
2713 | static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_sm_v(u32 r) | 2789 | static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_v(u32 r) |
2714 | { | 2790 | { |
2715 | return (r >> 1) & 0x1; | 2791 | return (r >> 1) & 0x1; |
2716 | } | 2792 | } |
2717 | static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_sm_pending_v(void) | 2793 | static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_pending_v(void) |
2718 | { | 2794 | { |
2719 | return 0x00000001; | 2795 | return 0x00000001; |
2720 | } | 2796 | } |
@@ -2810,10 +2886,6 @@ static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_f(u32 v) | |||
2810 | { | 2886 | { |
2811 | return (v & 0x1) << 0; | 2887 | return (v & 0x1) << 0; |
2812 | } | 2888 | } |
2813 | static inline u32 gr_gpcs_tpcs_sm_power_throttle_r(void) | ||
2814 | { | ||
2815 | return 0x00419ed8; | ||
2816 | } | ||
2817 | static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_r(void) | 2889 | static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_r(void) |
2818 | { | 2890 | { |
2819 | return 0x0041be08; | 2891 | return 0x0041be08; |
@@ -3078,42 +3150,6 @@ static inline u32 gr_fe_pwr_mode_req_done_v(void) | |||
3078 | { | 3150 | { |
3079 | return 0x00000000; | 3151 | return 0x00000000; |
3080 | } | 3152 | } |
3081 | static inline u32 gr_gpcs_tpcs_sm_sfe_ba_control_r(void) | ||
3082 | { | ||
3083 | return 0x00419f88; | ||
3084 | } | ||
3085 | static inline u32 gr_gpcs_tpcs_sm_sfe_ba_control_blkactivity_enable_f(u32 v) | ||
3086 | { | ||
3087 | return (v & 0x1) << 31; | ||
3088 | } | ||
3089 | static inline u32 gr_gpcs_tpcs_sm_sfe_ba_control_blkactivity_enable_m(void) | ||
3090 | { | ||
3091 | return 0x1 << 31; | ||
3092 | } | ||
3093 | static inline u32 gr_gpcs_tpcs_sm_quad_ba_control_r(void) | ||
3094 | { | ||
3095 | return 0x00419f80; | ||
3096 | } | ||
3097 | static inline u32 gr_gpcs_tpcs_sm_quad_ba_control_blkactivity_enable_f(u32 v) | ||
3098 | { | ||
3099 | return (v & 0x1) << 31; | ||
3100 | } | ||
3101 | static inline u32 gr_gpcs_tpcs_sm_quad_ba_control_blkactivity_enable_m(void) | ||
3102 | { | ||
3103 | return 0x1 << 31; | ||
3104 | } | ||
3105 | static inline u32 gr_gpcs_tpcs_sm_mio_ba_control_r(void) | ||
3106 | { | ||
3107 | return 0x00419ccc; | ||
3108 | } | ||
3109 | static inline u32 gr_gpcs_tpcs_sm_mio_ba_control_blkactivity_enable_f(u32 v) | ||
3110 | { | ||
3111 | return (v & 0x1) << 31; | ||
3112 | } | ||
3113 | static inline u32 gr_gpcs_tpcs_sm_mio_ba_control_blkactivity_enable_m(void) | ||
3114 | { | ||
3115 | return 0x1 << 31; | ||
3116 | } | ||
3117 | static inline u32 gr_gpcs_pri_mmu_ctrl_r(void) | 3153 | static inline u32 gr_gpcs_pri_mmu_ctrl_r(void) |
3118 | { | 3154 | { |
3119 | return 0x00418880; | 3155 | return 0x00418880; |
@@ -3166,6 +3202,14 @@ static inline u32 gr_gpcs_pri_mmu_debug_ctrl_r(void) | |||
3166 | { | 3202 | { |
3167 | return 0x004188b0; | 3203 | return 0x004188b0; |
3168 | } | 3204 | } |
3205 | static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_v(u32 r) | ||
3206 | { | ||
3207 | return (r >> 16) & 0x1; | ||
3208 | } | ||
3209 | static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_v(void) | ||
3210 | { | ||
3211 | return 0x00000001; | ||
3212 | } | ||
3169 | static inline u32 gr_gpcs_pri_mmu_debug_wr_r(void) | 3213 | static inline u32 gr_gpcs_pri_mmu_debug_wr_r(void) |
3170 | { | 3214 | { |
3171 | return 0x004188b4; | 3215 | return 0x004188b4; |
diff --git a/drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h index 2b20199e..a38cfe8d 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h | |||
@@ -50,30 +50,6 @@ | |||
50 | #ifndef _hw_ltc_gp10b_h_ | 50 | #ifndef _hw_ltc_gp10b_h_ |
51 | #define _hw_ltc_gp10b_h_ | 51 | #define _hw_ltc_gp10b_h_ |
52 | 52 | ||
53 | static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_r(void) | ||
54 | { | ||
55 | return 0xffffffff; | ||
56 | } | ||
57 | static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_r(void) | ||
58 | { | ||
59 | return 0xffffffff; | ||
60 | } | ||
61 | static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_r(void) | ||
62 | { | ||
63 | return 0xffffffff; | ||
64 | } | ||
65 | static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_r(void) | ||
66 | { | ||
67 | return 0xffffffff; | ||
68 | } | ||
69 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_r(void) | ||
70 | { | ||
71 | return 0xffffffff; | ||
72 | } | ||
73 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_r(void) | ||
74 | { | ||
75 | return 0xffffffff; | ||
76 | } | ||
77 | static inline u32 ltc_ltcs_lts0_cbc_ctrl1_r(void) | 53 | static inline u32 ltc_ltcs_lts0_cbc_ctrl1_r(void) |
78 | { | 54 | { |
79 | return 0x0014046c; | 55 | return 0x0014046c; |
@@ -140,7 +116,7 @@ static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_f(void) | |||
140 | } | 116 | } |
141 | static inline u32 ltc_ltc0_lts0_cbc_ctrl1_r(void) | 117 | static inline u32 ltc_ltc0_lts0_cbc_ctrl1_r(void) |
142 | { | 118 | { |
143 | return 0x0017e26c; | 119 | return 0x0014046c; |
144 | } | 120 | } |
145 | static inline u32 ltc_ltcs_ltss_cbc_ctrl2_r(void) | 121 | static inline u32 ltc_ltcs_ltss_cbc_ctrl2_r(void) |
146 | { | 122 | { |
@@ -148,7 +124,7 @@ static inline u32 ltc_ltcs_ltss_cbc_ctrl2_r(void) | |||
148 | } | 124 | } |
149 | static inline u32 ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(u32 v) | 125 | static inline u32 ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(u32 v) |
150 | { | 126 | { |
151 | return (v & 0x3ffff) << 0; | 127 | return (v & 0x1ffff) << 0; |
152 | } | 128 | } |
153 | static inline u32 ltc_ltcs_ltss_cbc_ctrl3_r(void) | 129 | static inline u32 ltc_ltcs_ltss_cbc_ctrl3_r(void) |
154 | { | 130 | { |
@@ -156,7 +132,7 @@ static inline u32 ltc_ltcs_ltss_cbc_ctrl3_r(void) | |||
156 | } | 132 | } |
157 | static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(u32 v) | 133 | static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(u32 v) |
158 | { | 134 | { |
159 | return (v & 0x3ffff) << 0; | 135 | return (v & 0x1ffff) << 0; |
160 | } | 136 | } |
161 | static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v(void) | 137 | static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v(void) |
162 | { | 138 | { |
@@ -298,8 +274,224 @@ static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_f(void) | |||
298 | { | 274 | { |
299 | return 0x1; | 275 | return 0x1; |
300 | } | 276 | } |
301 | static inline u32 ltc_ltc0_ltss_intr_r(void) | 277 | static inline u32 ltc_ltcs_ltss_intr_r(void) |
302 | { | 278 | { |
303 | return 0x0014020c; | 279 | return 0x0017e20c; |
280 | } | ||
281 | static inline u32 ltc_ltcs_ltss_intr_en_evicted_cb_m(void) | ||
282 | { | ||
283 | return 0x1 << 20; | ||
284 | } | ||
285 | static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_access_m(void) | ||
286 | { | ||
287 | return 0x1 << 30; | ||
288 | } | ||
289 | static inline u32 ltc_ltc0_lts0_intr_r(void) | ||
290 | { | ||
291 | return 0x0014040c; | ||
292 | } | ||
293 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_r(void) | ||
294 | { | ||
295 | return 0x0017e2a0; | ||
296 | } | ||
297 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_v(u32 r) | ||
298 | { | ||
299 | return (r >> 0) & 0x1; | ||
300 | } | ||
301 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_v(void) | ||
302 | { | ||
303 | return 0x00000001; | ||
304 | } | ||
305 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_f(void) | ||
306 | { | ||
307 | return 0x1; | ||
308 | } | ||
309 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_v(u32 r) | ||
310 | { | ||
311 | return (r >> 8) & 0xf; | ||
312 | } | ||
313 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_v(void) | ||
314 | { | ||
315 | return 0x00000003; | ||
316 | } | ||
317 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_f(void) | ||
318 | { | ||
319 | return 0x300; | ||
320 | } | ||
321 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_v(u32 r) | ||
322 | { | ||
323 | return (r >> 28) & 0x1; | ||
324 | } | ||
325 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_v(void) | ||
326 | { | ||
327 | return 0x00000001; | ||
328 | } | ||
329 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_f(void) | ||
330 | { | ||
331 | return 0x10000000; | ||
332 | } | ||
333 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_v(u32 r) | ||
334 | { | ||
335 | return (r >> 29) & 0x1; | ||
336 | } | ||
337 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_v(void) | ||
338 | { | ||
339 | return 0x00000001; | ||
340 | } | ||
341 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_f(void) | ||
342 | { | ||
343 | return 0x20000000; | ||
344 | } | ||
345 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_v(u32 r) | ||
346 | { | ||
347 | return (r >> 30) & 0x1; | ||
348 | } | ||
349 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_v(void) | ||
350 | { | ||
351 | return 0x00000001; | ||
352 | } | ||
353 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_f(void) | ||
354 | { | ||
355 | return 0x40000000; | ||
356 | } | ||
357 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_r(void) | ||
358 | { | ||
359 | return 0x0017e2a4; | ||
360 | } | ||
361 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_v(u32 r) | ||
362 | { | ||
363 | return (r >> 0) & 0x1; | ||
364 | } | ||
365 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_v(void) | ||
366 | { | ||
367 | return 0x00000001; | ||
368 | } | ||
369 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_f(void) | ||
370 | { | ||
371 | return 0x1; | ||
372 | } | ||
373 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_v(u32 r) | ||
374 | { | ||
375 | return (r >> 8) & 0xf; | ||
376 | } | ||
377 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_v(void) | ||
378 | { | ||
379 | return 0x00000003; | ||
380 | } | ||
381 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_f(void) | ||
382 | { | ||
383 | return 0x300; | ||
384 | } | ||
385 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_v(u32 r) | ||
386 | { | ||
387 | return (r >> 16) & 0x1; | ||
388 | } | ||
389 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_v(void) | ||
390 | { | ||
391 | return 0x00000001; | ||
392 | } | ||
393 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_f(void) | ||
394 | { | ||
395 | return 0x10000; | ||
396 | } | ||
397 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_v(u32 r) | ||
398 | { | ||
399 | return (r >> 28) & 0x1; | ||
400 | } | ||
401 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_v(void) | ||
402 | { | ||
403 | return 0x00000001; | ||
404 | } | ||
405 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_f(void) | ||
406 | { | ||
407 | return 0x10000000; | ||
408 | } | ||
409 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_v(u32 r) | ||
410 | { | ||
411 | return (r >> 29) & 0x1; | ||
412 | } | ||
413 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_v(void) | ||
414 | { | ||
415 | return 0x00000001; | ||
416 | } | ||
417 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_f(void) | ||
418 | { | ||
419 | return 0x20000000; | ||
420 | } | ||
421 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_v(u32 r) | ||
422 | { | ||
423 | return (r >> 30) & 0x1; | ||
424 | } | ||
425 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_v(void) | ||
426 | { | ||
427 | return 0x00000001; | ||
428 | } | ||
429 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_f(void) | ||
430 | { | ||
431 | return 0x40000000; | ||
432 | } | ||
433 | static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_r(void) | ||
434 | { | ||
435 | return 0x001402a0; | ||
436 | } | ||
437 | static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_v(u32 r) | ||
438 | { | ||
439 | return (r >> 0) & 0x1; | ||
440 | } | ||
441 | static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_v(void) | ||
442 | { | ||
443 | return 0x00000001; | ||
444 | } | ||
445 | static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_f(void) | ||
446 | { | ||
447 | return 0x1; | ||
448 | } | ||
449 | static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_r(void) | ||
450 | { | ||
451 | return 0x001402a4; | ||
452 | } | ||
453 | static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_v(u32 r) | ||
454 | { | ||
455 | return (r >> 0) & 0x1; | ||
456 | } | ||
457 | static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_v(void) | ||
458 | { | ||
459 | return 0x00000001; | ||
460 | } | ||
461 | static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_f(void) | ||
462 | { | ||
463 | return 0x1; | ||
464 | } | ||
465 | static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_r(void) | ||
466 | { | ||
467 | return 0x001422a0; | ||
468 | } | ||
469 | static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_v(u32 r) | ||
470 | { | ||
471 | return (r >> 0) & 0x1; | ||
472 | } | ||
473 | static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_v(void) | ||
474 | { | ||
475 | return 0x00000001; | ||
476 | } | ||
477 | static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_f(void) | ||
478 | { | ||
479 | return 0x1; | ||
480 | } | ||
481 | static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_r(void) | ||
482 | { | ||
483 | return 0x001422a4; | ||
484 | } | ||
485 | static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_v(u32 r) | ||
486 | { | ||
487 | return (r >> 0) & 0x1; | ||
488 | } | ||
489 | static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_v(void) | ||
490 | { | ||
491 | return 0x00000001; | ||
492 | } | ||
493 | static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_f(void) | ||
494 | { | ||
495 | return 0x1; | ||
304 | } | 496 | } |
305 | #endif | 497 | #endif |
diff --git a/drivers/gpu/nvgpu/gp10b/hw_mc_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_mc_gp10b.h index 83e06e8e..ba0af497 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_mc_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_mc_gp10b.h | |||
@@ -50,38 +50,62 @@ | |||
50 | #ifndef _hw_mc_gp10b_h_ | 50 | #ifndef _hw_mc_gp10b_h_ |
51 | #define _hw_mc_gp10b_h_ | 51 | #define _hw_mc_gp10b_h_ |
52 | 52 | ||
53 | static inline u32 mc_intr_0_r(u32 i) | 53 | static inline u32 mc_boot_0_r(void) |
54 | { | 54 | { |
55 | return 0x00000100 + i*4; | 55 | return 0x00000000; |
56 | } | 56 | } |
57 | static inline u32 mc_intr_0_pfifo_pending_f(void) | 57 | static inline u32 mc_boot_0_architecture_v(u32 r) |
58 | { | 58 | { |
59 | return 0x100; | 59 | return (r >> 24) & 0x1f; |
60 | } | 60 | } |
61 | static inline u32 mc_intr_0_pgraph_pending_f(void) | 61 | static inline u32 mc_boot_0_implementation_v(u32 r) |
62 | { | 62 | { |
63 | return 0x1000; | 63 | return (r >> 20) & 0xf; |
64 | } | ||
65 | static inline u32 mc_boot_0_major_revision_v(u32 r) | ||
66 | { | ||
67 | return (r >> 4) & 0xf; | ||
68 | } | ||
69 | static inline u32 mc_boot_0_minor_revision_v(u32 r) | ||
70 | { | ||
71 | return (r >> 0) & 0xf; | ||
72 | } | ||
73 | static inline u32 mc_intr_r(u32 i) | ||
74 | { | ||
75 | return 0x00000100 + i*4; | ||
64 | } | 76 | } |
65 | static inline u32 mc_intr_0_pmu_pending_f(void) | 77 | static inline u32 mc_intr_pfifo_pending_f(void) |
78 | { | ||
79 | return 0x100; | ||
80 | } | ||
81 | static inline u32 mc_intr_pmu_pending_f(void) | ||
66 | { | 82 | { |
67 | return 0x1000000; | 83 | return 0x1000000; |
68 | } | 84 | } |
69 | static inline u32 mc_intr_0_ltc_pending_f(void) | 85 | static inline u32 mc_intr_ltc_pending_f(void) |
70 | { | 86 | { |
71 | return 0x2000000; | 87 | return 0x2000000; |
72 | } | 88 | } |
73 | static inline u32 mc_intr_0_priv_ring_pending_f(void) | 89 | static inline u32 mc_intr_priv_ring_pending_f(void) |
74 | { | 90 | { |
75 | return 0x40000000; | 91 | return 0x40000000; |
76 | } | 92 | } |
77 | static inline u32 mc_intr_0_pbus_pending_f(void) | 93 | static inline u32 mc_intr_pbus_pending_f(void) |
78 | { | 94 | { |
79 | return 0x10000000; | 95 | return 0x10000000; |
80 | } | 96 | } |
81 | static inline u32 mc_intr_en_0_r(u32 i) | 97 | static inline u32 mc_intr_en_r(u32 i) |
82 | { | 98 | { |
83 | return 0x00000140 + i*4; | 99 | return 0x00000140 + i*4; |
84 | } | 100 | } |
101 | static inline u32 mc_intr_en_set_r(u32 i) | ||
102 | { | ||
103 | return 0x00000160 + i*4; | ||
104 | } | ||
105 | static inline u32 mc_intr_en_clear_r(u32 i) | ||
106 | { | ||
107 | return 0x00000180 + i*4; | ||
108 | } | ||
85 | static inline u32 mc_enable_r(void) | 109 | static inline u32 mc_enable_r(void) |
86 | { | 110 | { |
87 | return 0x00000200; | 111 | return 0x00000200; |
@@ -162,6 +186,10 @@ static inline u32 mc_enable_hub_enabled_f(void) | |||
162 | { | 186 | { |
163 | return 0x20000000; | 187 | return 0x20000000; |
164 | } | 188 | } |
189 | static inline u32 mc_intr_ltc_r(void) | ||
190 | { | ||
191 | return 0x000001c0; | ||
192 | } | ||
165 | static inline u32 mc_enable_pb_r(void) | 193 | static inline u32 mc_enable_pb_r(void) |
166 | { | 194 | { |
167 | return 0x00000204; | 195 | return 0x00000204; |
diff --git a/drivers/gpu/nvgpu/gp10b/hw_pbdma_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_pbdma_gp10b.h index 5720cde1..91429b47 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_pbdma_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_pbdma_gp10b.h | |||
@@ -174,6 +174,10 @@ static inline u32 pbdma_pb_header_type_inc_f(void) | |||
174 | { | 174 | { |
175 | return 0x20000000; | 175 | return 0x20000000; |
176 | } | 176 | } |
177 | static inline u32 pbdma_hdr_shadow_r(u32 i) | ||
178 | { | ||
179 | return 0x00040118 + i*8192; | ||
180 | } | ||
177 | static inline u32 pbdma_subdevice_r(u32 i) | 181 | static inline u32 pbdma_subdevice_r(u32 i) |
178 | { | 182 | { |
179 | return 0x00040094 + i*8192; | 183 | return 0x00040094 + i*8192; |
@@ -466,4 +470,20 @@ static inline u32 pbdma_syncpointb_syncpt_index_v(u32 r) | |||
466 | { | 470 | { |
467 | return (r >> 8) & 0xfff; | 471 | return (r >> 8) & 0xfff; |
468 | } | 472 | } |
473 | static inline u32 pbdma_runlist_timeslice_r(u32 i) | ||
474 | { | ||
475 | return 0x000400f8 + i*8192; | ||
476 | } | ||
477 | static inline u32 pbdma_runlist_timeslice_timeout_128_f(void) | ||
478 | { | ||
479 | return 0x80; | ||
480 | } | ||
481 | static inline u32 pbdma_runlist_timeslice_timescale_3_f(void) | ||
482 | { | ||
483 | return 0x3000; | ||
484 | } | ||
485 | static inline u32 pbdma_runlist_timeslice_enable_true_f(void) | ||
486 | { | ||
487 | return 0x10000000; | ||
488 | } | ||
469 | #endif | 489 | #endif |
diff --git a/drivers/gpu/nvgpu/gp10b/hw_pwr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_pwr_gp10b.h index d76095ac..0de70b96 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_pwr_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_pwr_gp10b.h | |||
@@ -378,6 +378,18 @@ static inline u32 pwr_falcon_bootvec_vec_f(u32 v) | |||
378 | { | 378 | { |
379 | return (v & 0xffffffff) << 0; | 379 | return (v & 0xffffffff) << 0; |
380 | } | 380 | } |
381 | static inline u32 pwr_falcon_dmactl_r(void) | ||
382 | { | ||
383 | return 0x0010a10c; | ||
384 | } | ||
385 | static inline u32 pwr_falcon_dmactl_dmem_scrubbing_m(void) | ||
386 | { | ||
387 | return 0x1 << 1; | ||
388 | } | ||
389 | static inline u32 pwr_falcon_dmactl_imem_scrubbing_m(void) | ||
390 | { | ||
391 | return 0x1 << 2; | ||
392 | } | ||
381 | static inline u32 pwr_falcon_hwcfg_r(void) | 393 | static inline u32 pwr_falcon_hwcfg_r(void) |
382 | { | 394 | { |
383 | return 0x0010a108; | 395 | return 0x0010a108; |
diff --git a/drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h index ef53882b..509031e5 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h | |||
@@ -78,6 +78,26 @@ static inline u32 ram_in_page_dir_base_vol_true_f(void) | |||
78 | { | 78 | { |
79 | return 0x4; | 79 | return 0x4; |
80 | } | 80 | } |
81 | static inline u32 ram_in_big_page_size_f(u32 v) | ||
82 | { | ||
83 | return (v & 0x1) << 11; | ||
84 | } | ||
85 | static inline u32 ram_in_big_page_size_m(void) | ||
86 | { | ||
87 | return 0x1 << 11; | ||
88 | } | ||
89 | static inline u32 ram_in_big_page_size_w(void) | ||
90 | { | ||
91 | return 128; | ||
92 | } | ||
93 | static inline u32 ram_in_big_page_size_128kb_f(void) | ||
94 | { | ||
95 | return 0x0; | ||
96 | } | ||
97 | static inline u32 ram_in_big_page_size_64kb_f(void) | ||
98 | { | ||
99 | return 0x800; | ||
100 | } | ||
81 | static inline u32 ram_in_page_dir_base_lo_f(u32 v) | 101 | static inline u32 ram_in_page_dir_base_lo_f(u32 v) |
82 | { | 102 | { |
83 | return (v & 0xfffff) << 12; | 103 | return (v & 0xfffff) << 12; |
@@ -318,7 +338,7 @@ static inline u32 ram_fc_chid_id_w(void) | |||
318 | { | 338 | { |
319 | return 0; | 339 | return 0; |
320 | } | 340 | } |
321 | static inline u32 ram_fc_pb_timeslice_w(void) | 341 | static inline u32 ram_fc_runlist_timeslice_w(void) |
322 | { | 342 | { |
323 | return 62; | 343 | return 62; |
324 | } | 344 | } |
@@ -382,4 +402,44 @@ static inline u32 ram_rl_entry_size_v(void) | |||
382 | { | 402 | { |
383 | return 0x00000008; | 403 | return 0x00000008; |
384 | } | 404 | } |
405 | static inline u32 ram_rl_entry_chid_f(u32 v) | ||
406 | { | ||
407 | return (v & 0xfff) << 0; | ||
408 | } | ||
409 | static inline u32 ram_rl_entry_id_f(u32 v) | ||
410 | { | ||
411 | return (v & 0xfff) << 0; | ||
412 | } | ||
413 | static inline u32 ram_rl_entry_type_f(u32 v) | ||
414 | { | ||
415 | return (v & 0x1) << 13; | ||
416 | } | ||
417 | static inline u32 ram_rl_entry_type_chid_f(void) | ||
418 | { | ||
419 | return 0x0; | ||
420 | } | ||
421 | static inline u32 ram_rl_entry_type_tsg_f(void) | ||
422 | { | ||
423 | return 0x2000; | ||
424 | } | ||
425 | static inline u32 ram_rl_entry_timeslice_scale_f(u32 v) | ||
426 | { | ||
427 | return (v & 0xf) << 14; | ||
428 | } | ||
429 | static inline u32 ram_rl_entry_timeslice_scale_3_f(void) | ||
430 | { | ||
431 | return 0xc000; | ||
432 | } | ||
433 | static inline u32 ram_rl_entry_timeslice_timeout_f(u32 v) | ||
434 | { | ||
435 | return (v & 0xff) << 18; | ||
436 | } | ||
437 | static inline u32 ram_rl_entry_timeslice_timeout_128_f(void) | ||
438 | { | ||
439 | return 0x2000000; | ||
440 | } | ||
441 | static inline u32 ram_rl_entry_tsg_length_f(u32 v) | ||
442 | { | ||
443 | return (v & 0x3f) << 26; | ||
444 | } | ||
385 | #endif | 445 | #endif |
diff --git a/drivers/gpu/nvgpu/gp10b/hw_therm_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_therm_gp10b.h index 16bbb3ca..25eecb70 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_therm_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_therm_gp10b.h | |||
@@ -70,58 +70,6 @@ static inline u32 therm_weight_1_r(void) | |||
70 | { | 70 | { |
71 | return 0x00020024; | 71 | return 0x00020024; |
72 | } | 72 | } |
73 | static inline u32 therm_peakpower_config1_r(u32 i) | ||
74 | { | ||
75 | return 0x00020154 + i*4; | ||
76 | } | ||
77 | static inline u32 therm_peakpower_config1_window_period_2m_v(void) | ||
78 | { | ||
79 | return 0x00000015; | ||
80 | } | ||
81 | static inline u32 therm_peakpower_config1_window_period_2m_f(void) | ||
82 | { | ||
83 | return 0x15; | ||
84 | } | ||
85 | static inline u32 therm_peakpower_config1_window_en_enabled_f(void) | ||
86 | { | ||
87 | return 0x80000000; | ||
88 | } | ||
89 | static inline u32 therm_peakpower_config1_r(u32 i) | ||
90 | { | ||
91 | return 0x000202e8 + i*4; | ||
92 | } | ||
93 | static inline u32 therm_peakpower_config1_ba_sum_shift_s(void) | ||
94 | { | ||
95 | return 5; | ||
96 | } | ||
97 | static inline u32 therm_peakpower_config1_ba_sum_shift_f(u32 v) | ||
98 | { | ||
99 | return (v & 0x1f) << 8; | ||
100 | } | ||
101 | static inline u32 therm_peakpower_config1_ba_sum_shift_m(void) | ||
102 | { | ||
103 | return 0x1f << 8; | ||
104 | } | ||
105 | static inline u32 therm_peakpower_config1_ba_sum_shift_v(u32 r) | ||
106 | { | ||
107 | return (r >> 8) & 0x1f; | ||
108 | } | ||
109 | static inline u32 therm_peakpower_config2_r(u32 i) | ||
110 | { | ||
111 | return 0x00020170 + i*4; | ||
112 | } | ||
113 | static inline u32 therm_peakpower_config4_r(u32 i) | ||
114 | { | ||
115 | return 0x000201c0 + i*4; | ||
116 | } | ||
117 | static inline u32 therm_peakpower_config8_r(u32 i) | ||
118 | { | ||
119 | return 0x000202e8 + i*4; | ||
120 | } | ||
121 | static inline u32 therm_peakpower_config9_r(u32 i) | ||
122 | { | ||
123 | return 0x000202f4 + i*4; | ||
124 | } | ||
125 | static inline u32 therm_config1_r(void) | 73 | static inline u32 therm_config1_r(void) |
126 | { | 74 | { |
127 | return 0x00020050; | 75 | return 0x00020050; |
@@ -214,4 +162,24 @@ static inline u32 therm_hubmmu_idle_filter_value_m(void) | |||
214 | { | 162 | { |
215 | return 0xffffffff << 0; | 163 | return 0xffffffff << 0; |
216 | } | 164 | } |
165 | static inline u32 therm_clk_slowdown_r(u32 i) | ||
166 | { | ||
167 | return 0x00020160 + i*4; | ||
168 | } | ||
169 | static inline u32 therm_clk_slowdown_idle_factor_f(u32 v) | ||
170 | { | ||
171 | return (v & 0x3f) << 16; | ||
172 | } | ||
173 | static inline u32 therm_clk_slowdown_idle_factor_m(void) | ||
174 | { | ||
175 | return 0x3f << 16; | ||
176 | } | ||
177 | static inline u32 therm_clk_slowdown_idle_factor_v(u32 r) | ||
178 | { | ||
179 | return (r >> 16) & 0x3f; | ||
180 | } | ||
181 | static inline u32 therm_clk_slowdown_idle_factor_disabled_f(void) | ||
182 | { | ||
183 | return 0x0; | ||
184 | } | ||
217 | #endif | 185 | #endif |
diff --git a/drivers/gpu/nvgpu/gp10b/hw_trim_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_trim_gp10b.h deleted file mode 100644 index 94da91b0..00000000 --- a/drivers/gpu/nvgpu/gp10b/hw_trim_gp10b.h +++ /dev/null | |||
@@ -1,289 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | /* | ||
17 | * Function naming determines intended use: | ||
18 | * | ||
19 | * <x>_r(void) : Returns the offset for register <x>. | ||
20 | * | ||
21 | * <x>_o(void) : Returns the offset for element <x>. | ||
22 | * | ||
23 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
24 | * | ||
25 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
26 | * | ||
27 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
28 | * and masked to place it at field <y> of register <x>. This value | ||
29 | * can be |'d with others to produce a full register value for | ||
30 | * register <x>. | ||
31 | * | ||
32 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
33 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
34 | * register <x>. | ||
35 | * | ||
36 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
37 | * to place it at field <y> of register <x>. This value can be |'d | ||
38 | * with others to produce a full register value for <x>. | ||
39 | * | ||
40 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
41 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
42 | * This value is suitable for direct comparison with other unshifted | ||
43 | * values appropriate for use in field <y> of register <x>. | ||
44 | * | ||
45 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
46 | * field <y> of register <x>. This value is suitable for direct | ||
47 | * comparison with unshifted values appropriate for use in field <y> | ||
48 | * of register <x>. | ||
49 | */ | ||
50 | #ifndef _hw_trim_gp10b_h_ | ||
51 | #define _hw_trim_gp10b_h_ | ||
52 | |||
53 | static inline u32 trim_sys_gpcpll_cfg_r(void) | ||
54 | { | ||
55 | return 0x00137000; | ||
56 | } | ||
57 | static inline u32 trim_sys_gpcpll_cfg_enable_m(void) | ||
58 | { | ||
59 | return 0x1 << 0; | ||
60 | } | ||
61 | static inline u32 trim_sys_gpcpll_cfg_enable_v(u32 r) | ||
62 | { | ||
63 | return (r >> 0) & 0x1; | ||
64 | } | ||
65 | static inline u32 trim_sys_gpcpll_cfg_enable_no_f(void) | ||
66 | { | ||
67 | return 0x0; | ||
68 | } | ||
69 | static inline u32 trim_sys_gpcpll_cfg_enable_yes_f(void) | ||
70 | { | ||
71 | return 0x1; | ||
72 | } | ||
73 | static inline u32 trim_sys_gpcpll_cfg_iddq_m(void) | ||
74 | { | ||
75 | return 0x1 << 1; | ||
76 | } | ||
77 | static inline u32 trim_sys_gpcpll_cfg_iddq_v(u32 r) | ||
78 | { | ||
79 | return (r >> 1) & 0x1; | ||
80 | } | ||
81 | static inline u32 trim_sys_gpcpll_cfg_iddq_power_on_v(void) | ||
82 | { | ||
83 | return 0x00000000; | ||
84 | } | ||
85 | static inline u32 trim_sys_gpcpll_cfg_enb_lckdet_m(void) | ||
86 | { | ||
87 | return 0x1 << 4; | ||
88 | } | ||
89 | static inline u32 trim_sys_gpcpll_cfg_enb_lckdet_power_on_f(void) | ||
90 | { | ||
91 | return 0x0; | ||
92 | } | ||
93 | static inline u32 trim_sys_gpcpll_cfg_enb_lckdet_power_off_f(void) | ||
94 | { | ||
95 | return 0x10; | ||
96 | } | ||
97 | static inline u32 trim_sys_gpcpll_cfg_pll_lock_v(u32 r) | ||
98 | { | ||
99 | return (r >> 17) & 0x1; | ||
100 | } | ||
101 | static inline u32 trim_sys_gpcpll_cfg_pll_lock_true_f(void) | ||
102 | { | ||
103 | return 0x20000; | ||
104 | } | ||
105 | static inline u32 trim_sys_gpcpll_coeff_r(void) | ||
106 | { | ||
107 | return 0x00137004; | ||
108 | } | ||
109 | static inline u32 trim_sys_gpcpll_coeff_mdiv_f(u32 v) | ||
110 | { | ||
111 | return (v & 0xff) << 0; | ||
112 | } | ||
113 | static inline u32 trim_sys_gpcpll_coeff_mdiv_v(u32 r) | ||
114 | { | ||
115 | return (r >> 0) & 0xff; | ||
116 | } | ||
117 | static inline u32 trim_sys_gpcpll_coeff_ndiv_f(u32 v) | ||
118 | { | ||
119 | return (v & 0xff) << 8; | ||
120 | } | ||
121 | static inline u32 trim_sys_gpcpll_coeff_ndiv_m(void) | ||
122 | { | ||
123 | return 0xff << 8; | ||
124 | } | ||
125 | static inline u32 trim_sys_gpcpll_coeff_ndiv_v(u32 r) | ||
126 | { | ||
127 | return (r >> 8) & 0xff; | ||
128 | } | ||
129 | static inline u32 trim_sys_gpcpll_coeff_pldiv_f(u32 v) | ||
130 | { | ||
131 | return (v & 0x3f) << 16; | ||
132 | } | ||
133 | static inline u32 trim_sys_gpcpll_coeff_pldiv_v(u32 r) | ||
134 | { | ||
135 | return (r >> 16) & 0x3f; | ||
136 | } | ||
137 | static inline u32 trim_sys_sel_vco_r(void) | ||
138 | { | ||
139 | return 0x00137100; | ||
140 | } | ||
141 | static inline u32 trim_sys_sel_vco_gpc2clk_out_m(void) | ||
142 | { | ||
143 | return 0x1 << 0; | ||
144 | } | ||
145 | static inline u32 trim_sys_sel_vco_gpc2clk_out_init_v(void) | ||
146 | { | ||
147 | return 0x00000000; | ||
148 | } | ||
149 | static inline u32 trim_sys_sel_vco_gpc2clk_out_init_f(void) | ||
150 | { | ||
151 | return 0x0; | ||
152 | } | ||
153 | static inline u32 trim_sys_sel_vco_gpc2clk_out_bypass_f(void) | ||
154 | { | ||
155 | return 0x0; | ||
156 | } | ||
157 | static inline u32 trim_sys_sel_vco_gpc2clk_out_vco_f(void) | ||
158 | { | ||
159 | return 0x1; | ||
160 | } | ||
161 | static inline u32 trim_sys_gpc2clk_out_r(void) | ||
162 | { | ||
163 | return 0x00137250; | ||
164 | } | ||
165 | static inline u32 trim_sys_gpc2clk_out_bypdiv_s(void) | ||
166 | { | ||
167 | return 6; | ||
168 | } | ||
169 | static inline u32 trim_sys_gpc2clk_out_bypdiv_f(u32 v) | ||
170 | { | ||
171 | return (v & 0x3f) << 0; | ||
172 | } | ||
173 | static inline u32 trim_sys_gpc2clk_out_bypdiv_m(void) | ||
174 | { | ||
175 | return 0x3f << 0; | ||
176 | } | ||
177 | static inline u32 trim_sys_gpc2clk_out_bypdiv_v(u32 r) | ||
178 | { | ||
179 | return (r >> 0) & 0x3f; | ||
180 | } | ||
181 | static inline u32 trim_sys_gpc2clk_out_bypdiv_by31_f(void) | ||
182 | { | ||
183 | return 0x3c; | ||
184 | } | ||
185 | static inline u32 trim_sys_gpc2clk_out_vcodiv_m(void) | ||
186 | { | ||
187 | return 0x3f << 8; | ||
188 | } | ||
189 | static inline u32 trim_sys_gpc2clk_out_vcodiv_by1_f(void) | ||
190 | { | ||
191 | return 0x0; | ||
192 | } | ||
193 | static inline u32 trim_sys_gpc2clk_out_sdiv14_m(void) | ||
194 | { | ||
195 | return 0x1 << 31; | ||
196 | } | ||
197 | static inline u32 trim_sys_gpc2clk_out_sdiv14_indiv4_mode_f(void) | ||
198 | { | ||
199 | return 0x80000000; | ||
200 | } | ||
201 | static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_r(u32 i) | ||
202 | { | ||
203 | return 0x001e0124 + i*1024; | ||
204 | } | ||
205 | static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_noofipclks_f(u32 v) | ||
206 | { | ||
207 | return (v & 0xffff) << 0; | ||
208 | } | ||
209 | static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_write_en_asserted_f(void) | ||
210 | { | ||
211 | return 0x10000; | ||
212 | } | ||
213 | static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_enable_asserted_f(void) | ||
214 | { | ||
215 | return 0x100000; | ||
216 | } | ||
217 | static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_reset_asserted_f(void) | ||
218 | { | ||
219 | return 0x1000000; | ||
220 | } | ||
221 | static inline u32 trim_gpc_clk_cntr_ncgpcclk_cnt_r(u32 i) | ||
222 | { | ||
223 | return 0x001e0128 + i*1024; | ||
224 | } | ||
225 | static inline u32 trim_gpc_clk_cntr_ncgpcclk_cnt_value_v(u32 r) | ||
226 | { | ||
227 | return (r >> 0) & 0xfffffff; | ||
228 | } | ||
229 | static inline u32 trim_sys_gpcpll_cfg2_r(void) | ||
230 | { | ||
231 | return 0x0013700c; | ||
232 | } | ||
233 | static inline u32 trim_sys_gpcpll_cfg2_pll_stepa_f(u32 v) | ||
234 | { | ||
235 | return (v & 0xff) << 24; | ||
236 | } | ||
237 | static inline u32 trim_sys_gpcpll_cfg2_pll_stepa_m(void) | ||
238 | { | ||
239 | return 0xff << 24; | ||
240 | } | ||
241 | static inline u32 trim_sys_gpcpll_cfg3_r(void) | ||
242 | { | ||
243 | return 0x00137018; | ||
244 | } | ||
245 | static inline u32 trim_sys_gpcpll_cfg3_pll_stepb_f(u32 v) | ||
246 | { | ||
247 | return (v & 0xff) << 16; | ||
248 | } | ||
249 | static inline u32 trim_sys_gpcpll_cfg3_pll_stepb_m(void) | ||
250 | { | ||
251 | return 0xff << 16; | ||
252 | } | ||
253 | static inline u32 trim_sys_gpcpll_ndiv_slowdown_r(void) | ||
254 | { | ||
255 | return 0x0013701c; | ||
256 | } | ||
257 | static inline u32 trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_m(void) | ||
258 | { | ||
259 | return 0x1 << 22; | ||
260 | } | ||
261 | static inline u32 trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_yes_f(void) | ||
262 | { | ||
263 | return 0x400000; | ||
264 | } | ||
265 | static inline u32 trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_no_f(void) | ||
266 | { | ||
267 | return 0x0; | ||
268 | } | ||
269 | static inline u32 trim_sys_gpcpll_ndiv_slowdown_en_dynramp_m(void) | ||
270 | { | ||
271 | return 0x1 << 31; | ||
272 | } | ||
273 | static inline u32 trim_sys_gpcpll_ndiv_slowdown_en_dynramp_yes_f(void) | ||
274 | { | ||
275 | return 0x80000000; | ||
276 | } | ||
277 | static inline u32 trim_sys_gpcpll_ndiv_slowdown_en_dynramp_no_f(void) | ||
278 | { | ||
279 | return 0x0; | ||
280 | } | ||
281 | static inline u32 trim_gpc_bcast_gpcpll_ndiv_slowdown_debug_r(void) | ||
282 | { | ||
283 | return 0x001328a0; | ||
284 | } | ||
285 | static inline u32 trim_gpc_bcast_gpcpll_ndiv_slowdown_debug_pll_dynramp_done_synced_v(u32 r) | ||
286 | { | ||
287 | return (r >> 24) & 0x1; | ||
288 | } | ||
289 | #endif | ||