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Diffstat (limited to 'drivers/gpu/nvgpu/vgpu')
-rw-r--r--drivers/gpu/nvgpu/vgpu/gr_vgpu.c7
-rw-r--r--drivers/gpu/nvgpu/vgpu/gr_vgpu.h2
2 files changed, 7 insertions, 2 deletions
diff --git a/drivers/gpu/nvgpu/vgpu/gr_vgpu.c b/drivers/gpu/nvgpu/vgpu/gr_vgpu.c
index c7996fd9..1c72ca76 100644
--- a/drivers/gpu/nvgpu/vgpu/gr_vgpu.c
+++ b/drivers/gpu/nvgpu/vgpu/gr_vgpu.c
@@ -1026,7 +1026,7 @@ int vgpu_gr_update_smpc_ctxsw_mode(struct gk20a *g,
1026} 1026}
1027 1027
1028int vgpu_gr_update_hwpm_ctxsw_mode(struct gk20a *g, 1028int vgpu_gr_update_hwpm_ctxsw_mode(struct gk20a *g,
1029 struct channel_gk20a *ch, bool enable) 1029 struct channel_gk20a *ch, u64 gpu_va, bool enable)
1030{ 1030{
1031 struct tsg_gk20a *tsg; 1031 struct tsg_gk20a *tsg;
1032 struct nvgpu_gr_ctx *ch_ctx; 1032 struct nvgpu_gr_ctx *ch_ctx;
@@ -1041,6 +1041,11 @@ int vgpu_gr_update_hwpm_ctxsw_mode(struct gk20a *g,
1041 if (!tsg) 1041 if (!tsg)
1042 return -EINVAL; 1042 return -EINVAL;
1043 1043
1044 if (gpu_va) {
1045 nvgpu_err(g, "gpu_va suppose to be allocated by this function.");
1046 return -EINVAL;
1047 }
1048
1044 ch_ctx = &tsg->gr_ctx; 1049 ch_ctx = &tsg->gr_ctx;
1045 pm_ctx = &ch_ctx->pm_ctx; 1050 pm_ctx = &ch_ctx->pm_ctx;
1046 1051
diff --git a/drivers/gpu/nvgpu/vgpu/gr_vgpu.h b/drivers/gpu/nvgpu/vgpu/gr_vgpu.h
index 1f55823c..d6b25b97 100644
--- a/drivers/gpu/nvgpu/vgpu/gr_vgpu.h
+++ b/drivers/gpu/nvgpu/vgpu/gr_vgpu.h
@@ -58,7 +58,7 @@ int vgpu_gr_set_sm_debug_mode(struct gk20a *g,
58int vgpu_gr_update_smpc_ctxsw_mode(struct gk20a *g, 58int vgpu_gr_update_smpc_ctxsw_mode(struct gk20a *g,
59 struct channel_gk20a *ch, bool enable); 59 struct channel_gk20a *ch, bool enable);
60int vgpu_gr_update_hwpm_ctxsw_mode(struct gk20a *g, 60int vgpu_gr_update_hwpm_ctxsw_mode(struct gk20a *g,
61 struct channel_gk20a *ch, bool enable); 61 struct channel_gk20a *ch, u64 gpu_va, bool enable);
62int vgpu_gr_clear_sm_error_state(struct gk20a *g, 62int vgpu_gr_clear_sm_error_state(struct gk20a *g,
63 struct channel_gk20a *ch, u32 sm_id); 63 struct channel_gk20a *ch, u32 sm_id);
64int vgpu_gr_suspend_contexts(struct gk20a *g, 64int vgpu_gr_suspend_contexts(struct gk20a *g,