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-rw-r--r--drivers/gpu/nvgpu/vgpu/fifo_vgpu.c10
-rw-r--r--drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c2
-rw-r--r--drivers/gpu/nvgpu/vgpu/gr_vgpu.c12
-rw-r--r--drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c2
4 files changed, 16 insertions, 10 deletions
diff --git a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c
index 6406c0da..c8a8ce49 100644
--- a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c
+++ b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c
@@ -643,7 +643,8 @@ int vgpu_fifo_force_reset_ch(struct channel_gk20a *ch,
643 nvgpu_list_for_each_entry(ch_tsg, &tsg->ch_list, 643 nvgpu_list_for_each_entry(ch_tsg, &tsg->ch_list,
644 channel_gk20a, ch_entry) { 644 channel_gk20a, ch_entry) {
645 if (gk20a_channel_get(ch_tsg)) { 645 if (gk20a_channel_get(ch_tsg)) {
646 nvgpu_set_error_notifier(ch_tsg, err_code); 646 g->ops.fifo.set_error_notifier(ch_tsg,
647 err_code);
647 ch_tsg->has_timedout = true; 648 ch_tsg->has_timedout = true;
648 gk20a_channel_put(ch_tsg); 649 gk20a_channel_put(ch_tsg);
649 } 650 }
@@ -651,7 +652,7 @@ int vgpu_fifo_force_reset_ch(struct channel_gk20a *ch,
651 652
652 nvgpu_rwsem_up_read(&tsg->ch_list_lock); 653 nvgpu_rwsem_up_read(&tsg->ch_list_lock);
653 } else { 654 } else {
654 nvgpu_set_error_notifier(ch, err_code); 655 g->ops.fifo.set_error_notifier(ch, err_code);
655 ch->has_timedout = true; 656 ch->has_timedout = true;
656 } 657 }
657 658
@@ -726,10 +727,11 @@ int vgpu_fifo_isr(struct gk20a *g, struct tegra_vgpu_fifo_intr_info *info)
726 727
727 switch (info->type) { 728 switch (info->type) {
728 case TEGRA_VGPU_FIFO_INTR_PBDMA: 729 case TEGRA_VGPU_FIFO_INTR_PBDMA:
729 nvgpu_set_error_notifier(ch, NVGPU_ERR_NOTIFIER_PBDMA_ERROR); 730 g->ops.fifo.set_error_notifier(ch,
731 NVGPU_ERR_NOTIFIER_PBDMA_ERROR);
730 break; 732 break;
731 case TEGRA_VGPU_FIFO_INTR_CTXSW_TIMEOUT: 733 case TEGRA_VGPU_FIFO_INTR_CTXSW_TIMEOUT:
732 nvgpu_set_error_notifier(ch, 734 g->ops.fifo.set_error_notifier(ch,
733 NVGPU_ERR_NOTIFIER_FIFO_ERROR_IDLE_TIMEOUT); 735 NVGPU_ERR_NOTIFIER_FIFO_ERROR_IDLE_TIMEOUT);
734 break; 736 break;
735 case TEGRA_VGPU_FIFO_INTR_MMU_FAULT: 737 case TEGRA_VGPU_FIFO_INTR_MMU_FAULT:
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
index ab08e09d..8b9f04dd 100644
--- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
+++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
@@ -65,6 +65,7 @@
65 65
66#include <nvgpu/enabled.h> 66#include <nvgpu/enabled.h>
67#include <nvgpu/vgpu/vgpu.h> 67#include <nvgpu/vgpu/vgpu.h>
68#include <nvgpu/error_notifier.h>
68 69
69#include <nvgpu/hw/gp10b/hw_fuse_gp10b.h> 70#include <nvgpu/hw/gp10b/hw_fuse_gp10b.h>
70#include <nvgpu/hw/gp10b/hw_fifo_gp10b.h> 71#include <nvgpu/hw/gp10b/hw_fifo_gp10b.h>
@@ -349,6 +350,7 @@ static const struct gpu_ops vgpu_gp10b_ops = {
349 .check_ch_ctxsw_timeout = gk20a_fifo_check_ch_ctxsw_timeout, 350 .check_ch_ctxsw_timeout = gk20a_fifo_check_ch_ctxsw_timeout,
350 .channel_suspend = gk20a_channel_suspend, 351 .channel_suspend = gk20a_channel_suspend,
351 .channel_resume = gk20a_channel_resume, 352 .channel_resume = gk20a_channel_resume,
353 .set_error_notifier = nvgpu_set_error_notifier,
352#ifdef CONFIG_TEGRA_GK20A_NVHOST 354#ifdef CONFIG_TEGRA_GK20A_NVHOST
353 .alloc_syncpt_buf = gk20a_fifo_alloc_syncpt_buf, 355 .alloc_syncpt_buf = gk20a_fifo_alloc_syncpt_buf,
354 .free_syncpt_buf = gk20a_fifo_free_syncpt_buf, 356 .free_syncpt_buf = gk20a_fifo_free_syncpt_buf,
diff --git a/drivers/gpu/nvgpu/vgpu/gr_vgpu.c b/drivers/gpu/nvgpu/vgpu/gr_vgpu.c
index 1c72ca76..a6cb3828 100644
--- a/drivers/gpu/nvgpu/vgpu/gr_vgpu.c
+++ b/drivers/gpu/nvgpu/vgpu/gr_vgpu.c
@@ -926,30 +926,30 @@ int vgpu_gr_isr(struct gk20a *g, struct tegra_vgpu_gr_intr_info *info)
926 nvgpu_cond_broadcast_interruptible(&ch->semaphore_wq); 926 nvgpu_cond_broadcast_interruptible(&ch->semaphore_wq);
927 break; 927 break;
928 case TEGRA_VGPU_GR_INTR_SEMAPHORE_TIMEOUT: 928 case TEGRA_VGPU_GR_INTR_SEMAPHORE_TIMEOUT:
929 nvgpu_set_error_notifier(ch, 929 g->ops.fifo.set_error_notifier(ch,
930 NVGPU_ERR_NOTIFIER_GR_SEMAPHORE_TIMEOUT); 930 NVGPU_ERR_NOTIFIER_GR_SEMAPHORE_TIMEOUT);
931 break; 931 break;
932 case TEGRA_VGPU_GR_INTR_ILLEGAL_NOTIFY: 932 case TEGRA_VGPU_GR_INTR_ILLEGAL_NOTIFY:
933 nvgpu_set_error_notifier(ch, 933 g->ops.fifo.set_error_notifier(ch,
934 NVGPU_ERR_NOTIFIER_GR_ILLEGAL_NOTIFY); 934 NVGPU_ERR_NOTIFIER_GR_ILLEGAL_NOTIFY);
935 case TEGRA_VGPU_GR_INTR_ILLEGAL_METHOD: 935 case TEGRA_VGPU_GR_INTR_ILLEGAL_METHOD:
936 break; 936 break;
937 case TEGRA_VGPU_GR_INTR_ILLEGAL_CLASS: 937 case TEGRA_VGPU_GR_INTR_ILLEGAL_CLASS:
938 nvgpu_set_error_notifier(ch, 938 g->ops.fifo.set_error_notifier(ch,
939 NVGPU_ERR_NOTIFIER_GR_ERROR_SW_NOTIFY); 939 NVGPU_ERR_NOTIFIER_GR_ERROR_SW_NOTIFY);
940 break; 940 break;
941 case TEGRA_VGPU_GR_INTR_FECS_ERROR: 941 case TEGRA_VGPU_GR_INTR_FECS_ERROR:
942 break; 942 break;
943 case TEGRA_VGPU_GR_INTR_CLASS_ERROR: 943 case TEGRA_VGPU_GR_INTR_CLASS_ERROR:
944 nvgpu_set_error_notifier(ch, 944 g->ops.fifo.set_error_notifier(ch,
945 NVGPU_ERR_NOTIFIER_GR_ERROR_SW_NOTIFY); 945 NVGPU_ERR_NOTIFIER_GR_ERROR_SW_NOTIFY);
946 break; 946 break;
947 case TEGRA_VGPU_GR_INTR_FIRMWARE_METHOD: 947 case TEGRA_VGPU_GR_INTR_FIRMWARE_METHOD:
948 nvgpu_set_error_notifier(ch, 948 g->ops.fifo.set_error_notifier(ch,
949 NVGPU_ERR_NOTIFIER_GR_ERROR_SW_NOTIFY); 949 NVGPU_ERR_NOTIFIER_GR_ERROR_SW_NOTIFY);
950 break; 950 break;
951 case TEGRA_VGPU_GR_INTR_EXCEPTION: 951 case TEGRA_VGPU_GR_INTR_EXCEPTION:
952 nvgpu_set_error_notifier(ch, 952 g->ops.fifo.set_error_notifier(ch,
953 NVGPU_ERR_NOTIFIER_GR_ERROR_SW_NOTIFY); 953 NVGPU_ERR_NOTIFIER_GR_ERROR_SW_NOTIFY);
954 break; 954 break;
955 case TEGRA_VGPU_GR_INTR_SM_EXCEPTION: 955 case TEGRA_VGPU_GR_INTR_SM_EXCEPTION:
diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c
index 5e3af9d7..32edbd21 100644
--- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c
+++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c
@@ -23,6 +23,7 @@
23#include <gk20a/gk20a.h> 23#include <gk20a/gk20a.h>
24#include <gv11b/hal_gv11b.h> 24#include <gv11b/hal_gv11b.h>
25#include <nvgpu/vgpu/vgpu.h> 25#include <nvgpu/vgpu/vgpu.h>
26#include <nvgpu/error_notifier.h>
26 27
27#include "vgpu/fifo_vgpu.h" 28#include "vgpu/fifo_vgpu.h"
28#include "vgpu/gr_vgpu.h" 29#include "vgpu/gr_vgpu.h"
@@ -392,6 +393,7 @@ static const struct gpu_ops vgpu_gv11b_ops = {
392 .check_ch_ctxsw_timeout = gk20a_fifo_check_ch_ctxsw_timeout, 393 .check_ch_ctxsw_timeout = gk20a_fifo_check_ch_ctxsw_timeout,
393 .channel_suspend = gk20a_channel_suspend, 394 .channel_suspend = gk20a_channel_suspend,
394 .channel_resume = gk20a_channel_resume, 395 .channel_resume = gk20a_channel_resume,
396 .set_error_notifier = nvgpu_set_error_notifier,
395#ifdef CONFIG_TEGRA_GK20A_NVHOST 397#ifdef CONFIG_TEGRA_GK20A_NVHOST
396 .alloc_syncpt_buf = vgpu_gv11b_fifo_alloc_syncpt_buf, 398 .alloc_syncpt_buf = vgpu_gv11b_fifo_alloc_syncpt_buf,
397 .free_syncpt_buf = gv11b_fifo_free_syncpt_buf, 399 .free_syncpt_buf = gv11b_fifo_free_syncpt_buf,