summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/nvgpu/vgpu
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/gpu/nvgpu/vgpu')
-rw-r--r--drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c2
-rw-r--r--drivers/gpu/nvgpu/vgpu/gr_vgpu.c27
-rw-r--r--drivers/gpu/nvgpu/vgpu/gr_vgpu.h2
-rw-r--r--drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c2
4 files changed, 30 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
index 6b593359..5630e406 100644
--- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
+++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
@@ -139,7 +139,7 @@ static const struct gpu_ops vgpu_gp10b_ops = {
139 .update_ctxsw_preemption_mode = 139 .update_ctxsw_preemption_mode =
140 gr_gp10b_update_ctxsw_preemption_mode, 140 gr_gp10b_update_ctxsw_preemption_mode,
141 .dump_gr_regs = NULL, 141 .dump_gr_regs = NULL,
142 .update_pc_sampling = gr_gm20b_update_pc_sampling, 142 .update_pc_sampling = vgpu_gr_update_pc_sampling,
143 .get_fbp_en_mask = vgpu_gr_get_fbp_en_mask, 143 .get_fbp_en_mask = vgpu_gr_get_fbp_en_mask,
144 .get_max_ltc_per_fbp = vgpu_gr_get_max_ltc_per_fbp, 144 .get_max_ltc_per_fbp = vgpu_gr_get_max_ltc_per_fbp,
145 .get_max_lts_per_ltc = vgpu_gr_get_max_lts_per_ltc, 145 .get_max_lts_per_ltc = vgpu_gr_get_max_lts_per_ltc,
diff --git a/drivers/gpu/nvgpu/vgpu/gr_vgpu.c b/drivers/gpu/nvgpu/vgpu/gr_vgpu.c
index 1e633d5f..9d765984 100644
--- a/drivers/gpu/nvgpu/vgpu/gr_vgpu.c
+++ b/drivers/gpu/nvgpu/vgpu/gr_vgpu.c
@@ -1310,3 +1310,30 @@ int vgpu_gr_init_fs_state(struct gk20a *g)
1310 1310
1311 return g->ops.gr.init_sm_id_table(g); 1311 return g->ops.gr.init_sm_id_table(g);
1312} 1312}
1313
1314int vgpu_gr_update_pc_sampling(struct channel_gk20a *ch, bool enable)
1315{
1316 struct tegra_vgpu_cmd_msg msg;
1317 struct tegra_vgpu_channel_update_pc_sampling *p =
1318 &msg.params.update_pc_sampling;
1319 struct gk20a *g;
1320 int err = -EINVAL;
1321
1322 if (!ch->g)
1323 return err;
1324 g = ch->g;
1325 nvgpu_log_fn(g, " ");
1326
1327 msg.cmd = TEGRA_VGPU_CMD_UPDATE_PC_SAMPLING;
1328 msg.handle = vgpu_get_handle(g);
1329 p->handle = ch->virt_ctx;
1330 if (enable)
1331 p->mode = TEGRA_VGPU_ENABLE_SAMPLING;
1332 else
1333 p->mode = TEGRA_VGPU_DISABLE_SAMPLING;
1334
1335 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
1336 WARN_ON(err || msg.ret);
1337
1338 return err ? err : msg.ret;
1339}
diff --git a/drivers/gpu/nvgpu/vgpu/gr_vgpu.h b/drivers/gpu/nvgpu/vgpu/gr_vgpu.h
index d6b25b97..c4b3944e 100644
--- a/drivers/gpu/nvgpu/vgpu/gr_vgpu.h
+++ b/drivers/gpu/nvgpu/vgpu/gr_vgpu.h
@@ -70,5 +70,5 @@ int vgpu_gr_resume_contexts(struct gk20a *g,
70int vgpu_gr_commit_inst(struct channel_gk20a *c, u64 gpu_va); 70int vgpu_gr_commit_inst(struct channel_gk20a *c, u64 gpu_va);
71int vgpu_gr_init_sm_id_table(struct gk20a *g); 71int vgpu_gr_init_sm_id_table(struct gk20a *g);
72int vgpu_gr_init_fs_state(struct gk20a *g); 72int vgpu_gr_init_fs_state(struct gk20a *g);
73 73int vgpu_gr_update_pc_sampling(struct channel_gk20a *ch, bool enable);
74#endif 74#endif
diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c
index 1b78a4c9..7b536329 100644
--- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c
+++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c
@@ -156,7 +156,7 @@ static const struct gpu_ops vgpu_gv11b_ops = {
156 .update_ctxsw_preemption_mode = 156 .update_ctxsw_preemption_mode =
157 gr_gv11b_update_ctxsw_preemption_mode, 157 gr_gv11b_update_ctxsw_preemption_mode,
158 .dump_gr_regs = NULL, 158 .dump_gr_regs = NULL,
159 .update_pc_sampling = gr_gm20b_update_pc_sampling, 159 .update_pc_sampling = vgpu_gr_update_pc_sampling,
160 .get_fbp_en_mask = vgpu_gr_get_fbp_en_mask, 160 .get_fbp_en_mask = vgpu_gr_get_fbp_en_mask,
161 .get_max_ltc_per_fbp = vgpu_gr_get_max_ltc_per_fbp, 161 .get_max_ltc_per_fbp = vgpu_gr_get_max_ltc_per_fbp,
162 .get_max_lts_per_ltc = vgpu_gr_get_max_lts_per_ltc, 162 .get_max_lts_per_ltc = vgpu_gr_get_max_lts_per_ltc,