diff options
Diffstat (limited to 'drivers/gpu/nvgpu/vgpu')
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/clk_vgpu.c | 160 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/clk_vgpu.h | 29 |
2 files changed, 189 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/vgpu/clk_vgpu.c b/drivers/gpu/nvgpu/vgpu/clk_vgpu.c new file mode 100644 index 00000000..efcb4fb0 --- /dev/null +++ b/drivers/gpu/nvgpu/vgpu/clk_vgpu.c | |||
@@ -0,0 +1,160 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | |||
23 | #include <nvgpu/vgpu/vgpu.h> | ||
24 | |||
25 | #include "gk20a/gk20a.h" | ||
26 | #include "clk_vgpu.h" | ||
27 | #include "ctrl/ctrlclk.h" | ||
28 | |||
29 | static unsigned long | ||
30 | vgpu_freq_table[TEGRA_VGPU_GPU_FREQ_TABLE_SIZE]; | ||
31 | |||
32 | static unsigned long vgpu_clk_get_rate(struct gk20a *g, u32 api_domain) | ||
33 | { | ||
34 | struct tegra_vgpu_cmd_msg msg = {}; | ||
35 | struct tegra_vgpu_gpu_clk_rate_params *p = &msg.params.gpu_clk_rate; | ||
36 | int err; | ||
37 | unsigned long ret = 0; | ||
38 | |||
39 | nvgpu_log_fn(g, " "); | ||
40 | |||
41 | switch (api_domain) { | ||
42 | case CTRL_CLK_DOMAIN_GPCCLK: | ||
43 | msg.cmd = TEGRA_VGPU_CMD_GET_GPU_CLK_RATE; | ||
44 | msg.handle = vgpu_get_handle(g); | ||
45 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
46 | err = err ? err : msg.ret; | ||
47 | if (err) | ||
48 | nvgpu_err(g, "%s failed - %d", __func__, err); | ||
49 | else | ||
50 | /* return frequency in Hz */ | ||
51 | ret = p->rate * 1000; | ||
52 | break; | ||
53 | case CTRL_CLK_DOMAIN_PWRCLK: | ||
54 | nvgpu_err(g, "unsupported clock: %u", api_domain); | ||
55 | break; | ||
56 | default: | ||
57 | nvgpu_err(g, "unknown clock: %u", api_domain); | ||
58 | break; | ||
59 | } | ||
60 | |||
61 | return ret; | ||
62 | } | ||
63 | |||
64 | static int vgpu_clk_set_rate(struct gk20a *g, | ||
65 | u32 api_domain, unsigned long rate) | ||
66 | { | ||
67 | struct tegra_vgpu_cmd_msg msg = {}; | ||
68 | struct tegra_vgpu_gpu_clk_rate_params *p = &msg.params.gpu_clk_rate; | ||
69 | int err = -EINVAL; | ||
70 | |||
71 | nvgpu_log_fn(g, " "); | ||
72 | |||
73 | switch (api_domain) { | ||
74 | case CTRL_CLK_DOMAIN_GPCCLK: | ||
75 | msg.cmd = TEGRA_VGPU_CMD_SET_GPU_CLK_RATE; | ||
76 | msg.handle = vgpu_get_handle(g); | ||
77 | |||
78 | /* server dvfs framework requires frequency in kHz */ | ||
79 | p->rate = (u32)(rate / 1000); | ||
80 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
81 | err = err ? err : msg.ret; | ||
82 | if (err) | ||
83 | nvgpu_err(g, "%s failed - %d", __func__, err); | ||
84 | break; | ||
85 | case CTRL_CLK_DOMAIN_PWRCLK: | ||
86 | nvgpu_err(g, "unsupported clock: %u", api_domain); | ||
87 | break; | ||
88 | default: | ||
89 | nvgpu_err(g, "unknown clock: %u", api_domain); | ||
90 | break; | ||
91 | } | ||
92 | |||
93 | return err; | ||
94 | } | ||
95 | |||
96 | static unsigned long vgpu_clk_get_maxrate(struct gk20a *g, u32 api_domain) | ||
97 | { | ||
98 | struct vgpu_priv_data *priv = vgpu_get_priv_data(g); | ||
99 | |||
100 | return priv->constants.max_freq; | ||
101 | } | ||
102 | |||
103 | void vgpu_init_clk_support(struct gk20a *g) | ||
104 | { | ||
105 | g->ops.clk.get_rate = vgpu_clk_get_rate; | ||
106 | g->ops.clk.set_rate = vgpu_clk_set_rate; | ||
107 | g->ops.clk.get_maxrate = vgpu_clk_get_maxrate; | ||
108 | } | ||
109 | |||
110 | int vgpu_clk_get_freqs(struct gk20a *g, unsigned long **freqs, int *num_freqs) | ||
111 | { | ||
112 | struct tegra_vgpu_cmd_msg msg = {}; | ||
113 | struct tegra_vgpu_get_gpu_freq_table_params *p = | ||
114 | &msg.params.get_gpu_freq_table; | ||
115 | unsigned int i; | ||
116 | int err; | ||
117 | |||
118 | nvgpu_log_fn(g, " "); | ||
119 | |||
120 | msg.cmd = TEGRA_VGPU_CMD_GET_GPU_FREQ_TABLE; | ||
121 | msg.handle = vgpu_get_handle(g); | ||
122 | |||
123 | p->num_freqs = TEGRA_VGPU_GPU_FREQ_TABLE_SIZE; | ||
124 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
125 | err = err ? err : msg.ret; | ||
126 | if (err) { | ||
127 | nvgpu_err(g, "%s failed - %d", __func__, err); | ||
128 | return err; | ||
129 | } | ||
130 | |||
131 | /* return frequency in Hz */ | ||
132 | for (i = 0; i < p->num_freqs; i++) | ||
133 | vgpu_freq_table[i] = p->freqs[i] * 1000; | ||
134 | |||
135 | *freqs = vgpu_freq_table; | ||
136 | *num_freqs = p->num_freqs; | ||
137 | |||
138 | return 0; | ||
139 | } | ||
140 | |||
141 | int vgpu_clk_cap_rate(struct gk20a *g, unsigned long rate) | ||
142 | { | ||
143 | struct tegra_vgpu_cmd_msg msg = {}; | ||
144 | struct tegra_vgpu_gpu_clk_rate_params *p = &msg.params.gpu_clk_rate; | ||
145 | int err = 0; | ||
146 | |||
147 | nvgpu_log_fn(g, " "); | ||
148 | |||
149 | msg.cmd = TEGRA_VGPU_CMD_CAP_GPU_CLK_RATE; | ||
150 | msg.handle = vgpu_get_handle(g); | ||
151 | p->rate = (u32)rate; | ||
152 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
153 | err = err ? err : msg.ret; | ||
154 | if (err) { | ||
155 | nvgpu_err(g, "%s failed - %d", __func__, err); | ||
156 | return err; | ||
157 | } | ||
158 | |||
159 | return 0; | ||
160 | } | ||
diff --git a/drivers/gpu/nvgpu/vgpu/clk_vgpu.h b/drivers/gpu/nvgpu/vgpu/clk_vgpu.h new file mode 100644 index 00000000..ae9f8345 --- /dev/null +++ b/drivers/gpu/nvgpu/vgpu/clk_vgpu.h | |||
@@ -0,0 +1,29 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | |||
23 | #ifndef _CLK_VGPU_H_ | ||
24 | #define _CLK_VGPU_H_ | ||
25 | |||
26 | void vgpu_init_clk_support(struct gk20a *g); | ||
27 | int vgpu_clk_get_freqs(struct gk20a *g, unsigned long **freqs, int *num_freqs); | ||
28 | int vgpu_clk_cap_rate(struct gk20a *g, unsigned long rate); | ||
29 | #endif | ||