diff options
Diffstat (limited to 'drivers/gpu/nvgpu/vgpu/vgpu.h')
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/vgpu.h | 194 |
1 files changed, 194 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/vgpu/vgpu.h b/drivers/gpu/nvgpu/vgpu/vgpu.h new file mode 100644 index 00000000..dcfbddf2 --- /dev/null +++ b/drivers/gpu/nvgpu/vgpu/vgpu.h | |||
@@ -0,0 +1,194 @@ | |||
1 | /* | ||
2 | * Virtualized GPU Interfaces | ||
3 | * | ||
4 | * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice shall be included in | ||
14 | * all copies or substantial portions of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
22 | * DEALINGS IN THE SOFTWARE. | ||
23 | */ | ||
24 | |||
25 | #ifndef _VIRT_H_ | ||
26 | #define _VIRT_H_ | ||
27 | |||
28 | struct device; | ||
29 | struct tegra_vgpu_gr_intr_info; | ||
30 | struct tegra_vgpu_fifo_intr_info; | ||
31 | struct tegra_vgpu_cmd_msg; | ||
32 | struct gk20a_platform; | ||
33 | |||
34 | #ifdef CONFIG_TEGRA_GR_VIRTUALIZATION | ||
35 | #include <linux/tegra_gr_comm.h> | ||
36 | #include <linux/tegra_vgpu.h> | ||
37 | #include "gk20a/gk20a.h" | ||
38 | #include "common/linux/platform_gk20a.h" | ||
39 | #include "common/linux/os_linux.h" | ||
40 | |||
41 | #include <nvgpu/thread.h> | ||
42 | |||
43 | struct vgpu_priv_data { | ||
44 | u64 virt_handle; | ||
45 | struct nvgpu_thread intr_handler; | ||
46 | struct tegra_vgpu_constants_params constants; | ||
47 | }; | ||
48 | |||
49 | static inline | ||
50 | struct vgpu_priv_data *vgpu_get_priv_data_from_dev(struct device *dev) | ||
51 | { | ||
52 | struct gk20a_platform *plat = gk20a_get_platform(dev); | ||
53 | |||
54 | return (struct vgpu_priv_data *)plat->vgpu_priv; | ||
55 | } | ||
56 | |||
57 | static inline struct vgpu_priv_data *vgpu_get_priv_data(struct gk20a *g) | ||
58 | { | ||
59 | return vgpu_get_priv_data_from_dev(dev_from_gk20a(g)); | ||
60 | } | ||
61 | |||
62 | static inline u64 vgpu_get_handle_from_dev(struct device *dev) | ||
63 | { | ||
64 | struct vgpu_priv_data *priv = vgpu_get_priv_data_from_dev(dev); | ||
65 | |||
66 | if (unlikely(!priv)) { | ||
67 | dev_err(dev, "invalid vgpu_priv_data in %s\n", __func__); | ||
68 | return INT_MAX; | ||
69 | } | ||
70 | |||
71 | return priv->virt_handle; | ||
72 | } | ||
73 | |||
74 | static inline u64 vgpu_get_handle(struct gk20a *g) | ||
75 | { | ||
76 | return vgpu_get_handle_from_dev(dev_from_gk20a(g)); | ||
77 | } | ||
78 | |||
79 | int vgpu_pm_prepare_poweroff(struct device *dev); | ||
80 | int vgpu_pm_finalize_poweron(struct device *dev); | ||
81 | int vgpu_probe(struct platform_device *dev); | ||
82 | int vgpu_remove(struct platform_device *dev); | ||
83 | u64 vgpu_bar1_map(struct gk20a *g, struct sg_table **sgt, u64 size); | ||
84 | int vgpu_gr_isr(struct gk20a *g, struct tegra_vgpu_gr_intr_info *info); | ||
85 | int vgpu_gr_nonstall_isr(struct gk20a *g, | ||
86 | struct tegra_vgpu_gr_nonstall_intr_info *info); | ||
87 | int vgpu_gr_alloc_gr_ctx(struct gk20a *g, | ||
88 | struct gr_ctx_desc **__gr_ctx, | ||
89 | struct vm_gk20a *vm, | ||
90 | u32 class, | ||
91 | u32 flags); | ||
92 | void vgpu_gr_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm, | ||
93 | struct gr_ctx_desc *gr_ctx); | ||
94 | void vgpu_gr_handle_sm_esr_event(struct gk20a *g, | ||
95 | struct tegra_vgpu_sm_esr_info *info); | ||
96 | int vgpu_gr_init_ctx_state(struct gk20a *g); | ||
97 | int vgpu_fifo_isr(struct gk20a *g, struct tegra_vgpu_fifo_intr_info *info); | ||
98 | int vgpu_fifo_nonstall_isr(struct gk20a *g, | ||
99 | struct tegra_vgpu_fifo_nonstall_intr_info *info); | ||
100 | int vgpu_ce2_nonstall_isr(struct gk20a *g, | ||
101 | struct tegra_vgpu_ce2_nonstall_intr_info *info); | ||
102 | u32 vgpu_ce_get_num_pce(struct gk20a *g); | ||
103 | int vgpu_init_mm_support(struct gk20a *g); | ||
104 | int vgpu_init_gr_support(struct gk20a *g); | ||
105 | int vgpu_init_fifo_support(struct gk20a *g); | ||
106 | |||
107 | int vgpu_get_attribute(u64 handle, u32 attrib, u32 *value); | ||
108 | int vgpu_comm_sendrecv(struct tegra_vgpu_cmd_msg *msg, size_t size_in, | ||
109 | size_t size_out); | ||
110 | |||
111 | int vgpu_gm20b_init_hal(struct gk20a *g); | ||
112 | int vgpu_gp10b_init_hal(struct gk20a *g); | ||
113 | |||
114 | int vgpu_init_gpu_characteristics(struct gk20a *g); | ||
115 | |||
116 | void vgpu_create_sysfs(struct device *dev); | ||
117 | void vgpu_remove_sysfs(struct device *dev); | ||
118 | int vgpu_read_ptimer(struct gk20a *g, u64 *value); | ||
119 | int vgpu_get_timestamps_zipper(struct gk20a *g, | ||
120 | u32 source_id, u32 count, | ||
121 | struct nvgpu_cpu_time_correlation_sample *samples); | ||
122 | #else | ||
123 | static inline int vgpu_pm_prepare_poweroff(struct device *dev) | ||
124 | { | ||
125 | return -ENOSYS; | ||
126 | } | ||
127 | static inline int vgpu_pm_finalize_poweron(struct device *dev) | ||
128 | { | ||
129 | return -ENOSYS; | ||
130 | } | ||
131 | static inline int vgpu_probe(struct platform_device *dev) | ||
132 | { | ||
133 | return -ENOSYS; | ||
134 | } | ||
135 | static inline int vgpu_remove(struct platform_device *dev) | ||
136 | { | ||
137 | return -ENOSYS; | ||
138 | } | ||
139 | static inline u64 vgpu_bar1_map(struct gk20a *g, struct sg_table **sgt, | ||
140 | u64 size) | ||
141 | { | ||
142 | return 0; | ||
143 | } | ||
144 | static inline int vgpu_gr_isr(struct gk20a *g, | ||
145 | struct tegra_vgpu_gr_intr_info *info) | ||
146 | { | ||
147 | return 0; | ||
148 | } | ||
149 | static inline int vgpu_gr_alloc_gr_ctx(struct gk20a *g, | ||
150 | struct gr_ctx_desc **__gr_ctx, | ||
151 | struct vm_gk20a *vm, | ||
152 | u32 class, | ||
153 | u32 flags) | ||
154 | { | ||
155 | return -ENOSYS; | ||
156 | } | ||
157 | static inline void vgpu_gr_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm, | ||
158 | struct gr_ctx_desc *gr_ctx) | ||
159 | { | ||
160 | } | ||
161 | static inline int vgpu_gr_init_ctx_state(struct gk20a *g) | ||
162 | { | ||
163 | return -ENOSYS; | ||
164 | } | ||
165 | static inline int vgpu_fifo_isr(struct gk20a *g, | ||
166 | struct tegra_vgpu_fifo_intr_info *info) | ||
167 | { | ||
168 | return 0; | ||
169 | } | ||
170 | static inline int vgpu_init_mm_support(struct gk20a *g) | ||
171 | { | ||
172 | return -ENOSYS; | ||
173 | } | ||
174 | static inline int vgpu_init_gr_support(struct gk20a *g) | ||
175 | { | ||
176 | return -ENOSYS; | ||
177 | } | ||
178 | static inline int vgpu_init_fifo_support(struct gk20a *g) | ||
179 | { | ||
180 | return -ENOSYS; | ||
181 | } | ||
182 | |||
183 | static inline int vgpu_get_attribute(u64 handle, u32 attrib, u32 *value) | ||
184 | { | ||
185 | return -ENOSYS; | ||
186 | } | ||
187 | static inline int vgpu_comm_sendrecv(struct tegra_vgpu_cmd_msg *msg, size_t size_in, | ||
188 | size_t size_out) | ||
189 | { | ||
190 | return -ENOSYS; | ||
191 | } | ||
192 | #endif | ||
193 | |||
194 | #endif | ||