diff options
Diffstat (limited to 'drivers/gpu/nvgpu/vgpu/vgpu.c')
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/vgpu.c | 30 |
1 files changed, 16 insertions, 14 deletions
diff --git a/drivers/gpu/nvgpu/vgpu/vgpu.c b/drivers/gpu/nvgpu/vgpu/vgpu.c index c03086e1..300ffc98 100644 --- a/drivers/gpu/nvgpu/vgpu/vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/vgpu.c | |||
@@ -187,7 +187,7 @@ static int vgpu_intr_thread(void *dev_id) | |||
187 | static void vgpu_remove_support(struct device *dev) | 187 | static void vgpu_remove_support(struct device *dev) |
188 | { | 188 | { |
189 | struct gk20a *g = get_gk20a(dev); | 189 | struct gk20a *g = get_gk20a(dev); |
190 | struct gk20a_platform *platform = gk20a_get_platform(dev); | 190 | struct vgpu_priv_data *priv = vgpu_get_priv_data_from_dev(dev); |
191 | struct tegra_vgpu_intr_msg msg; | 191 | struct tegra_vgpu_intr_msg msg; |
192 | int err; | 192 | int err; |
193 | 193 | ||
@@ -208,7 +208,7 @@ static void vgpu_remove_support(struct device *dev) | |||
208 | TEGRA_GR_COMM_ID_SELF, TEGRA_VGPU_QUEUE_INTR, | 208 | TEGRA_GR_COMM_ID_SELF, TEGRA_VGPU_QUEUE_INTR, |
209 | &msg, sizeof(msg)); | 209 | &msg, sizeof(msg)); |
210 | WARN_ON(err); | 210 | WARN_ON(err); |
211 | kthread_stop(platform->intr_handler); | 211 | kthread_stop(priv->intr_handler); |
212 | 212 | ||
213 | /* free mappings to registers, etc*/ | 213 | /* free mappings to registers, etc*/ |
214 | 214 | ||
@@ -271,11 +271,10 @@ int vgpu_pm_prepare_poweroff(struct device *dev) | |||
271 | static void vgpu_detect_chip(struct gk20a *g) | 271 | static void vgpu_detect_chip(struct gk20a *g) |
272 | { | 272 | { |
273 | struct nvgpu_gpu_characteristics *gpu = &g->gpu_characteristics; | 273 | struct nvgpu_gpu_characteristics *gpu = &g->gpu_characteristics; |
274 | struct gk20a_platform *platform = gk20a_get_platform(g->dev); | ||
275 | 274 | ||
276 | u32 mc_boot_0_value; | 275 | u32 mc_boot_0_value; |
277 | 276 | ||
278 | if (vgpu_get_attribute(platform->virt_handle, | 277 | if (vgpu_get_attribute(vgpu_get_handle(g), |
279 | TEGRA_VGPU_ATTRIB_PMC_BOOT_0, | 278 | TEGRA_VGPU_ATTRIB_PMC_BOOT_0, |
280 | &mc_boot_0_value)) { | 279 | &mc_boot_0_value)) { |
281 | gk20a_err(dev_from_gk20a(g), "failed to detect chip"); | 280 | gk20a_err(dev_from_gk20a(g), "failed to detect chip"); |
@@ -297,7 +296,6 @@ static void vgpu_detect_chip(struct gk20a *g) | |||
297 | 296 | ||
298 | static int vgpu_init_gpu_characteristics(struct gk20a *g) | 297 | static int vgpu_init_gpu_characteristics(struct gk20a *g) |
299 | { | 298 | { |
300 | struct gk20a_platform *platform = gk20a_get_platform(g->dev); | ||
301 | u32 max_freq; | 299 | u32 max_freq; |
302 | int err; | 300 | int err; |
303 | 301 | ||
@@ -307,7 +305,7 @@ static int vgpu_init_gpu_characteristics(struct gk20a *g) | |||
307 | if (err) | 305 | if (err) |
308 | return err; | 306 | return err; |
309 | 307 | ||
310 | if (vgpu_get_attribute(platform->virt_handle, | 308 | if (vgpu_get_attribute(vgpu_get_handle(g), |
311 | TEGRA_VGPU_ATTRIB_MAX_FREQ, &max_freq)) | 309 | TEGRA_VGPU_ATTRIB_MAX_FREQ, &max_freq)) |
312 | return -ENOMEM; | 310 | return -ENOMEM; |
313 | 311 | ||
@@ -318,7 +316,6 @@ static int vgpu_init_gpu_characteristics(struct gk20a *g) | |||
318 | 316 | ||
319 | static int vgpu_read_ptimer(struct gk20a *g, u64 *value) | 317 | static int vgpu_read_ptimer(struct gk20a *g, u64 *value) |
320 | { | 318 | { |
321 | struct gk20a_platform *platform = gk20a_get_platform(g->dev); | ||
322 | struct tegra_vgpu_cmd_msg msg = {0}; | 319 | struct tegra_vgpu_cmd_msg msg = {0}; |
323 | struct tegra_vgpu_read_ptimer_params *p = &msg.params.read_ptimer; | 320 | struct tegra_vgpu_read_ptimer_params *p = &msg.params.read_ptimer; |
324 | int err; | 321 | int err; |
@@ -326,7 +323,7 @@ static int vgpu_read_ptimer(struct gk20a *g, u64 *value) | |||
326 | gk20a_dbg_fn(""); | 323 | gk20a_dbg_fn(""); |
327 | 324 | ||
328 | msg.cmd = TEGRA_VGPU_CMD_READ_PTIMER; | 325 | msg.cmd = TEGRA_VGPU_CMD_READ_PTIMER; |
329 | msg.handle = platform->virt_handle; | 326 | msg.handle = vgpu_get_handle(g); |
330 | 327 | ||
331 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | 328 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); |
332 | err = err ? err : msg.ret; | 329 | err = err ? err : msg.ret; |
@@ -441,7 +438,6 @@ static int vgpu_qos_notify(struct notifier_block *nb, | |||
441 | struct gk20a_scale_profile *profile = | 438 | struct gk20a_scale_profile *profile = |
442 | container_of(nb, struct gk20a_scale_profile, | 439 | container_of(nb, struct gk20a_scale_profile, |
443 | qos_notify_block); | 440 | qos_notify_block); |
444 | struct gk20a_platform *platform = gk20a_get_platform(profile->dev); | ||
445 | struct tegra_vgpu_cmd_msg msg = {}; | 441 | struct tegra_vgpu_cmd_msg msg = {}; |
446 | struct tegra_vgpu_gpu_clk_rate_params *p = &msg.params.gpu_clk_rate; | 442 | struct tegra_vgpu_gpu_clk_rate_params *p = &msg.params.gpu_clk_rate; |
447 | u32 max_freq; | 443 | u32 max_freq; |
@@ -452,7 +448,7 @@ static int vgpu_qos_notify(struct notifier_block *nb, | |||
452 | max_freq = (u32)pm_qos_read_max_bound(PM_QOS_GPU_FREQ_BOUNDS); | 448 | max_freq = (u32)pm_qos_read_max_bound(PM_QOS_GPU_FREQ_BOUNDS); |
453 | 449 | ||
454 | msg.cmd = TEGRA_VGPU_CMD_SET_GPU_CLK_RATE; | 450 | msg.cmd = TEGRA_VGPU_CMD_SET_GPU_CLK_RATE; |
455 | msg.handle = platform->virt_handle; | 451 | msg.handle = vgpu_get_handle_from_dev(profile->dev); |
456 | p->rate = max_freq; | 452 | p->rate = max_freq; |
457 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | 453 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); |
458 | err = err ? err : msg.ret; | 454 | err = err ? err : msg.ret; |
@@ -510,6 +506,7 @@ int vgpu_probe(struct platform_device *pdev) | |||
510 | int err; | 506 | int err; |
511 | struct device *dev = &pdev->dev; | 507 | struct device *dev = &pdev->dev; |
512 | struct gk20a_platform *platform = gk20a_get_platform(dev); | 508 | struct gk20a_platform *platform = gk20a_get_platform(dev); |
509 | struct vgpu_priv_data *priv; | ||
513 | 510 | ||
514 | if (!platform) { | 511 | if (!platform) { |
515 | dev_err(dev, "no platform data\n"); | 512 | dev_err(dev, "no platform data\n"); |
@@ -518,6 +515,10 @@ int vgpu_probe(struct platform_device *pdev) | |||
518 | 515 | ||
519 | gk20a_dbg_fn(""); | 516 | gk20a_dbg_fn(""); |
520 | 517 | ||
518 | priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); | ||
519 | if (!priv) | ||
520 | return -ENOMEM; | ||
521 | |||
521 | gk20a = kzalloc(sizeof(struct gk20a), GFP_KERNEL); | 522 | gk20a = kzalloc(sizeof(struct gk20a), GFP_KERNEL); |
522 | if (!gk20a) { | 523 | if (!gk20a) { |
523 | dev_err(dev, "couldn't allocate gk20a support"); | 524 | dev_err(dev, "couldn't allocate gk20a support"); |
@@ -525,6 +526,7 @@ int vgpu_probe(struct platform_device *pdev) | |||
525 | } | 526 | } |
526 | 527 | ||
527 | platform->g = gk20a; | 528 | platform->g = gk20a; |
529 | platform->vgpu_priv = priv; | ||
528 | gk20a->dev = dev; | 530 | gk20a->dev = dev; |
529 | 531 | ||
530 | err = gk20a_user_init(dev, INTERFACE_NAME, &nvgpu_class); | 532 | err = gk20a_user_init(dev, INTERFACE_NAME, &nvgpu_class); |
@@ -564,15 +566,15 @@ int vgpu_probe(struct platform_device *pdev) | |||
564 | return -ENOSYS; | 566 | return -ENOSYS; |
565 | } | 567 | } |
566 | 568 | ||
567 | platform->virt_handle = vgpu_connect(); | 569 | priv->virt_handle = vgpu_connect(); |
568 | if (!platform->virt_handle) { | 570 | if (!priv->virt_handle) { |
569 | dev_err(dev, "failed to connect to server node\n"); | 571 | dev_err(dev, "failed to connect to server node\n"); |
570 | vgpu_comm_deinit(); | 572 | vgpu_comm_deinit(); |
571 | return -ENOSYS; | 573 | return -ENOSYS; |
572 | } | 574 | } |
573 | 575 | ||
574 | platform->intr_handler = kthread_run(vgpu_intr_thread, gk20a, "gk20a"); | 576 | priv->intr_handler = kthread_run(vgpu_intr_thread, gk20a, "gk20a"); |
575 | if (IS_ERR(platform->intr_handler)) | 577 | if (IS_ERR(priv->intr_handler)) |
576 | return -ENOMEM; | 578 | return -ENOMEM; |
577 | 579 | ||
578 | gk20a_debug_init(dev); | 580 | gk20a_debug_init(dev); |