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path: root/drivers/gpu/nvgpu/vgpu/tsg_vgpu.c
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Diffstat (limited to 'drivers/gpu/nvgpu/vgpu/tsg_vgpu.c')
-rw-r--r--drivers/gpu/nvgpu/vgpu/tsg_vgpu.c15
1 files changed, 10 insertions, 5 deletions
diff --git a/drivers/gpu/nvgpu/vgpu/tsg_vgpu.c b/drivers/gpu/nvgpu/vgpu/tsg_vgpu.c
index a6e493d0..7bb8f671 100644
--- a/drivers/gpu/nvgpu/vgpu/tsg_vgpu.c
+++ b/drivers/gpu/nvgpu/vgpu/tsg_vgpu.c
@@ -35,8 +35,9 @@ int vgpu_tsg_open(struct tsg_gk20a *tsg)
35 struct tegra_vgpu_tsg_open_rel_params *p = 35 struct tegra_vgpu_tsg_open_rel_params *p =
36 &msg.params.tsg_open; 36 &msg.params.tsg_open;
37 int err; 37 int err;
38 struct gk20a *g = tsg->g;
38 39
39 gk20a_dbg_fn(""); 40 nvgpu_log_fn(g, " ");
40 41
41 msg.cmd = TEGRA_VGPU_CMD_TSG_OPEN; 42 msg.cmd = TEGRA_VGPU_CMD_TSG_OPEN;
42 msg.handle = vgpu_get_handle(tsg->g); 43 msg.handle = vgpu_get_handle(tsg->g);
@@ -57,8 +58,9 @@ void vgpu_tsg_release(struct tsg_gk20a *tsg)
57 struct tegra_vgpu_tsg_open_rel_params *p = 58 struct tegra_vgpu_tsg_open_rel_params *p =
58 &msg.params.tsg_release; 59 &msg.params.tsg_release;
59 int err; 60 int err;
61 struct gk20a *g = tsg->g;
60 62
61 gk20a_dbg_fn(""); 63 nvgpu_log_fn(g, " ");
62 64
63 msg.cmd = TEGRA_VGPU_CMD_TSG_RELEASE; 65 msg.cmd = TEGRA_VGPU_CMD_TSG_RELEASE;
64 msg.handle = vgpu_get_handle(tsg->g); 66 msg.handle = vgpu_get_handle(tsg->g);
@@ -91,8 +93,9 @@ int vgpu_tsg_bind_channel(struct tsg_gk20a *tsg,
91 struct tegra_vgpu_tsg_bind_unbind_channel_params *p = 93 struct tegra_vgpu_tsg_bind_unbind_channel_params *p =
92 &msg.params.tsg_bind_unbind_channel; 94 &msg.params.tsg_bind_unbind_channel;
93 int err; 95 int err;
96 struct gk20a *g = ch->g;
94 97
95 gk20a_dbg_fn(""); 98 nvgpu_log_fn(g, " ");
96 99
97 err = gk20a_tsg_bind_channel(tsg, ch); 100 err = gk20a_tsg_bind_channel(tsg, ch);
98 if (err) 101 if (err)
@@ -120,8 +123,9 @@ int vgpu_tsg_unbind_channel(struct channel_gk20a *ch)
120 struct tegra_vgpu_tsg_bind_unbind_channel_params *p = 123 struct tegra_vgpu_tsg_bind_unbind_channel_params *p =
121 &msg.params.tsg_bind_unbind_channel; 124 &msg.params.tsg_bind_unbind_channel;
122 int err; 125 int err;
126 struct gk20a *g = ch->g;
123 127
124 gk20a_dbg_fn(""); 128 nvgpu_log_fn(g, " ");
125 129
126 err = gk20a_fifo_tsg_unbind_channel(ch); 130 err = gk20a_fifo_tsg_unbind_channel(ch);
127 if (err) 131 if (err)
@@ -143,8 +147,9 @@ int vgpu_tsg_set_timeslice(struct tsg_gk20a *tsg, u32 timeslice)
143 struct tegra_vgpu_tsg_timeslice_params *p = 147 struct tegra_vgpu_tsg_timeslice_params *p =
144 &msg.params.tsg_timeslice; 148 &msg.params.tsg_timeslice;
145 int err; 149 int err;
150 struct gk20a *g = tsg->g;
146 151
147 gk20a_dbg_fn(""); 152 nvgpu_log_fn(g, " ");
148 153
149 msg.cmd = TEGRA_VGPU_CMD_TSG_SET_TIMESLICE; 154 msg.cmd = TEGRA_VGPU_CMD_TSG_SET_TIMESLICE;
150 msg.handle = vgpu_get_handle(tsg->g); 155 msg.handle = vgpu_get_handle(tsg->g);