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Diffstat (limited to 'drivers/gpu/nvgpu/vgpu/gv11b/vgpu_subctx_gv11b.c')
-rw-r--r--drivers/gpu/nvgpu/vgpu/gv11b/vgpu_subctx_gv11b.c79
1 files changed, 0 insertions, 79 deletions
diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_subctx_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_subctx_gv11b.c
deleted file mode 100644
index 857e58c4..00000000
--- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_subctx_gv11b.c
+++ /dev/null
@@ -1,79 +0,0 @@
1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#include <gk20a/gk20a.h>
24#include <vgpu/vgpu.h>
25#include <linux/tegra_vgpu.h>
26
27int vgpu_gv11b_alloc_subctx_header(struct channel_gk20a *c)
28{
29 struct ctx_header_desc *ctx = &c->ch_ctx.ctx_header;
30 struct tegra_vgpu_cmd_msg msg = {};
31 struct tegra_vgpu_alloc_ctx_header_params *p =
32 &msg.params.t19x.alloc_ctx_header;
33 struct gr_gk20a *gr = &c->g->gr;
34 int err;
35
36 msg.cmd = TEGRA_VGPU_CMD_ALLOC_CTX_HEADER;
37 msg.handle = vgpu_get_handle(c->g);
38 p->ch_handle = c->virt_ctx;
39 p->ctx_header_va = __nvgpu_vm_alloc_va(c->vm,
40 gr->ctx_vars.golden_image_size,
41 gmmu_page_size_kernel);
42 if (!p->ctx_header_va) {
43 nvgpu_err(c->g, "alloc va failed for ctx_header");
44 return -ENOMEM;
45 }
46 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
47 err = err ? err : msg.ret;
48 if (unlikely(err)) {
49 nvgpu_err(c->g, "alloc ctx_header failed err %d", err);
50 __nvgpu_vm_free_va(c->vm, p->ctx_header_va,
51 gmmu_page_size_kernel);
52 return err;
53 }
54 ctx->mem.gpu_va = p->ctx_header_va;
55
56 return err;
57}
58
59void vgpu_gv11b_free_subctx_header(struct channel_gk20a *c)
60{
61 struct ctx_header_desc *ctx = &c->ch_ctx.ctx_header;
62 struct tegra_vgpu_cmd_msg msg = {};
63 struct tegra_vgpu_free_ctx_header_params *p =
64 &msg.params.t19x.free_ctx_header;
65 int err;
66
67 if (ctx->mem.gpu_va) {
68 msg.cmd = TEGRA_VGPU_CMD_FREE_CTX_HEADER;
69 msg.handle = vgpu_get_handle(c->g);
70 p->ch_handle = c->virt_ctx;
71 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
72 err = err ? err : msg.ret;
73 if (unlikely(err))
74 nvgpu_err(c->g, "free ctx_header failed err %d", err);
75 __nvgpu_vm_free_va(c->vm, ctx->mem.gpu_va,
76 gmmu_page_size_kernel);
77 ctx->mem.gpu_va = 0;
78 }
79}