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path: root/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c
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Diffstat (limited to 'drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c')
-rw-r--r--drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c642
1 files changed, 0 insertions, 642 deletions
diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c
deleted file mode 100644
index 17d6f049..00000000
--- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c
+++ /dev/null
@@ -1,642 +0,0 @@
1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#include <gk20a/gk20a.h>
24#include <gv11b/hal_gv11b.h>
25#include <vgpu/vgpu.h>
26#include <vgpu/fifo_vgpu.h>
27#include <vgpu/gr_vgpu.h>
28#include <vgpu/ltc_vgpu.h>
29#include <vgpu/mm_vgpu.h>
30#include <vgpu/dbg_vgpu.h>
31#include <vgpu/fecs_trace_vgpu.h>
32#include <vgpu/css_vgpu.h>
33#include <vgpu/vgpu_t19x.h>
34#include <vgpu/gm20b/vgpu_gr_gm20b.h>
35#include <vgpu/gp10b/vgpu_mm_gp10b.h>
36#include <vgpu/gp10b/vgpu_gr_gp10b.h>
37
38#include <gk20a/fb_gk20a.h>
39#include <gk20a/flcn_gk20a.h>
40#include <gk20a/bus_gk20a.h>
41#include <gk20a/mc_gk20a.h>
42
43#include <gm20b/gr_gm20b.h>
44#include <gm20b/fb_gm20b.h>
45#include <gm20b/fifo_gm20b.h>
46#include <gm20b/pmu_gm20b.h>
47#include <gm20b/mm_gm20b.h>
48#include <gm20b/acr_gm20b.h>
49#include <gm20b/ltc_gm20b.h>
50
51#include <gp10b/fb_gp10b.h>
52#include <gp10b/pmu_gp10b.h>
53#include <gp10b/mm_gp10b.h>
54#include <gp10b/mc_gp10b.h>
55#include <gp10b/ce_gp10b.h>
56#include <gp10b/fifo_gp10b.h>
57#include <gp10b/therm_gp10b.h>
58#include <gp10b/priv_ring_gp10b.h>
59#include <gp10b/ltc_gp10b.h>
60
61#include <gp106/pmu_gp106.h>
62#include <gp106/acr_gp106.h>
63
64#include <gv11b/fb_gv11b.h>
65#include <gv11b/pmu_gv11b.h>
66#include <gv11b/acr_gv11b.h>
67#include <gv11b/mm_gv11b.h>
68#include <gv11b/mc_gv11b.h>
69#include <gv11b/ce_gv11b.h>
70#include <gv11b/fifo_gv11b.h>
71#include <gv11b/therm_gv11b.h>
72#include <gv11b/regops_gv11b.h>
73#include <gv11b/gr_ctx_gv11b.h>
74#include <gv11b/ltc_gv11b.h>
75#include <gv11b/gv11b_gating_reglist.h>
76
77#include <gv100/gr_gv100.h>
78
79#include <nvgpu/enabled.h>
80
81#include "vgpu_gv11b.h"
82#include "vgpu_gr_gv11b.h"
83#include "vgpu_fifo_gv11b.h"
84#include "vgpu_subctx_gv11b.h"
85#include "vgpu_tsg_gv11b.h"
86
87#include <nvgpu/hw/gv11b/hw_fuse_gv11b.h>
88#include <nvgpu/hw/gv11b/hw_fifo_gv11b.h>
89#include <nvgpu/hw/gv11b/hw_ram_gv11b.h>
90#include <nvgpu/hw/gv11b/hw_top_gv11b.h>
91#include <nvgpu/hw/gv11b/hw_pwr_gv11b.h>
92
93static const struct gpu_ops vgpu_gv11b_ops = {
94 .ltc = {
95 .determine_L2_size_bytes = vgpu_determine_L2_size_bytes,
96 .set_zbc_s_entry = gv11b_ltc_set_zbc_stencil_entry,
97 .set_zbc_color_entry = gm20b_ltc_set_zbc_color_entry,
98 .set_zbc_depth_entry = gm20b_ltc_set_zbc_depth_entry,
99 .init_cbc = NULL,
100 .init_fs_state = vgpu_ltc_init_fs_state,
101 .init_comptags = vgpu_ltc_init_comptags,
102 .cbc_ctrl = NULL,
103 .isr = gv11b_ltc_isr,
104 .cbc_fix_config = gv11b_ltc_cbc_fix_config,
105 .flush = gm20b_flush_ltc,
106 .set_enabled = gp10b_ltc_set_enabled,
107 },
108 .ce2 = {
109 .isr_stall = gv11b_ce_isr,
110 .isr_nonstall = gp10b_ce_nonstall_isr,
111 .get_num_pce = vgpu_ce_get_num_pce,
112 },
113 .gr = {
114 .init_gpc_mmu = gr_gv11b_init_gpc_mmu,
115 .bundle_cb_defaults = gr_gv11b_bundle_cb_defaults,
116 .cb_size_default = gr_gv11b_cb_size_default,
117 .calc_global_ctx_buffer_size =
118 gr_gv11b_calc_global_ctx_buffer_size,
119 .commit_global_attrib_cb = gr_gv11b_commit_global_attrib_cb,
120 .commit_global_bundle_cb = gr_gp10b_commit_global_bundle_cb,
121 .commit_global_cb_manager = gr_gp10b_commit_global_cb_manager,
122 .commit_global_pagepool = gr_gp10b_commit_global_pagepool,
123 .handle_sw_method = gr_gv11b_handle_sw_method,
124 .set_alpha_circular_buffer_size =
125 gr_gv11b_set_alpha_circular_buffer_size,
126 .set_circular_buffer_size = gr_gv11b_set_circular_buffer_size,
127 .enable_hww_exceptions = gr_gv11b_enable_hww_exceptions,
128 .is_valid_class = gr_gv11b_is_valid_class,
129 .is_valid_gfx_class = gr_gv11b_is_valid_gfx_class,
130 .is_valid_compute_class = gr_gv11b_is_valid_compute_class,
131 .get_sm_dsm_perf_regs = gv11b_gr_get_sm_dsm_perf_regs,
132 .get_sm_dsm_perf_ctrl_regs = gv11b_gr_get_sm_dsm_perf_ctrl_regs,
133 .init_fs_state = vgpu_gm20b_init_fs_state,
134 .set_hww_esr_report_mask = gv11b_gr_set_hww_esr_report_mask,
135 .falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments,
136 .load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode,
137 .set_gpc_tpc_mask = gr_gv11b_set_gpc_tpc_mask,
138 .get_gpc_tpc_mask = vgpu_gr_get_gpc_tpc_mask,
139 .free_channel_ctx = vgpu_gr_free_channel_ctx,
140 .alloc_obj_ctx = vgpu_gr_alloc_obj_ctx,
141 .bind_ctxsw_zcull = vgpu_gr_bind_ctxsw_zcull,
142 .get_zcull_info = vgpu_gr_get_zcull_info,
143 .is_tpc_addr = gr_gm20b_is_tpc_addr,
144 .get_tpc_num = gr_gm20b_get_tpc_num,
145 .detect_sm_arch = vgpu_gr_detect_sm_arch,
146 .add_zbc_color = gr_gp10b_add_zbc_color,
147 .add_zbc_depth = gr_gp10b_add_zbc_depth,
148 .zbc_set_table = vgpu_gr_add_zbc,
149 .zbc_query_table = vgpu_gr_query_zbc,
150 .pmu_save_zbc = gk20a_pmu_save_zbc,
151 .add_zbc = gr_gk20a_add_zbc,
152 .pagepool_default_size = gr_gv11b_pagepool_default_size,
153 .init_ctx_state = vgpu_gr_gp10b_init_ctx_state,
154 .alloc_gr_ctx = vgpu_gr_gp10b_alloc_gr_ctx,
155 .free_gr_ctx = vgpu_gr_gp10b_free_gr_ctx,
156 .update_ctxsw_preemption_mode =
157 gr_gp10b_update_ctxsw_preemption_mode,
158 .dump_gr_regs = NULL,
159 .update_pc_sampling = gr_gm20b_update_pc_sampling,
160 .get_fbp_en_mask = vgpu_gr_get_fbp_en_mask,
161 .get_max_ltc_per_fbp = vgpu_gr_get_max_ltc_per_fbp,
162 .get_max_lts_per_ltc = vgpu_gr_get_max_lts_per_ltc,
163 .get_rop_l2_en_mask = vgpu_gr_rop_l2_en_mask,
164 .get_max_fbps_count = vgpu_gr_get_max_fbps_count,
165 .init_sm_dsm_reg_info = gv11b_gr_init_sm_dsm_reg_info,
166 .wait_empty = gr_gv11b_wait_empty,
167 .init_cyclestats = vgpu_gr_gm20b_init_cyclestats,
168 .set_sm_debug_mode = vgpu_gr_set_sm_debug_mode,
169 .enable_cde_in_fecs = gr_gm20b_enable_cde_in_fecs,
170 .bpt_reg_info = gv11b_gr_bpt_reg_info,
171 .get_access_map = gr_gv11b_get_access_map,
172 .handle_fecs_error = gr_gv11b_handle_fecs_error,
173 .handle_sm_exception = gr_gk20a_handle_sm_exception,
174 .handle_tex_exception = gr_gv11b_handle_tex_exception,
175 .enable_gpc_exceptions = gr_gv11b_enable_gpc_exceptions,
176 .enable_exceptions = gr_gv11b_enable_exceptions,
177 .get_lrf_tex_ltc_dram_override = get_ecc_override_val,
178 .update_smpc_ctxsw_mode = vgpu_gr_update_smpc_ctxsw_mode,
179 .update_hwpm_ctxsw_mode = vgpu_gr_update_hwpm_ctxsw_mode,
180 .record_sm_error_state = gv11b_gr_record_sm_error_state,
181 .update_sm_error_state = gv11b_gr_update_sm_error_state,
182 .clear_sm_error_state = vgpu_gr_clear_sm_error_state,
183 .suspend_contexts = vgpu_gr_suspend_contexts,
184 .resume_contexts = vgpu_gr_resume_contexts,
185 .get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags,
186 .init_sm_id_table = gr_gv100_init_sm_id_table,
187 .load_smid_config = gr_gv11b_load_smid_config,
188 .program_sm_id_numbering = gr_gv11b_program_sm_id_numbering,
189 .is_ltcs_ltss_addr = gr_gm20b_is_ltcs_ltss_addr,
190 .is_ltcn_ltss_addr = gr_gm20b_is_ltcn_ltss_addr,
191 .split_lts_broadcast_addr = gr_gm20b_split_lts_broadcast_addr,
192 .split_ltc_broadcast_addr = gr_gm20b_split_ltc_broadcast_addr,
193 .setup_rop_mapping = gr_gv11b_setup_rop_mapping,
194 .program_zcull_mapping = gr_gv11b_program_zcull_mapping,
195 .commit_global_timeslice = gr_gv11b_commit_global_timeslice,
196 .commit_inst = vgpu_gr_gv11b_commit_inst,
197 .write_zcull_ptr = gr_gv11b_write_zcull_ptr,
198 .write_pm_ptr = gr_gv11b_write_pm_ptr,
199 .init_elcg_mode = gr_gv11b_init_elcg_mode,
200 .load_tpc_mask = gr_gv11b_load_tpc_mask,
201 .inval_icache = gr_gk20a_inval_icache,
202 .trigger_suspend = gv11b_gr_sm_trigger_suspend,
203 .wait_for_pause = gr_gk20a_wait_for_pause,
204 .resume_from_pause = gv11b_gr_resume_from_pause,
205 .clear_sm_errors = gr_gk20a_clear_sm_errors,
206 .tpc_enabled_exceptions = gr_gk20a_tpc_enabled_exceptions,
207 .get_esr_sm_sel = gv11b_gr_get_esr_sm_sel,
208 .sm_debugger_attached = gv11b_gr_sm_debugger_attached,
209 .suspend_single_sm = gv11b_gr_suspend_single_sm,
210 .suspend_all_sms = gv11b_gr_suspend_all_sms,
211 .resume_single_sm = gv11b_gr_resume_single_sm,
212 .resume_all_sms = gv11b_gr_resume_all_sms,
213 .get_sm_hww_warp_esr = gv11b_gr_get_sm_hww_warp_esr,
214 .get_sm_hww_global_esr = gv11b_gr_get_sm_hww_global_esr,
215 .get_sm_no_lock_down_hww_global_esr_mask =
216 gv11b_gr_get_sm_no_lock_down_hww_global_esr_mask,
217 .lock_down_sm = gv11b_gr_lock_down_sm,
218 .wait_for_sm_lock_down = gv11b_gr_wait_for_sm_lock_down,
219 .clear_sm_hww = gv11b_gr_clear_sm_hww,
220 .init_ovr_sm_dsm_perf = gv11b_gr_init_ovr_sm_dsm_perf,
221 .get_ovr_perf_regs = gv11b_gr_get_ovr_perf_regs,
222 .disable_rd_coalesce = gm20a_gr_disable_rd_coalesce,
223 .set_boosted_ctx = NULL,
224 .set_preemption_mode = vgpu_gr_gp10b_set_preemption_mode,
225 .set_czf_bypass = NULL,
226 .pre_process_sm_exception = gr_gv11b_pre_process_sm_exception,
227 .set_preemption_buffer_va = gr_gv11b_set_preemption_buffer_va,
228 .init_preemption_state = NULL,
229 .update_boosted_ctx = NULL,
230 .set_bes_crop_debug3 = gr_gp10b_set_bes_crop_debug3,
231 .create_gr_sysfs = gr_gv11b_create_sysfs,
232 .set_ctxsw_preemption_mode = vgpu_gr_gp10b_set_ctxsw_preemption_mode,
233 .is_etpc_addr = gv11b_gr_pri_is_etpc_addr,
234 .egpc_etpc_priv_addr_table = gv11b_gr_egpc_etpc_priv_addr_table,
235 .handle_tpc_mpc_exception = gr_gv11b_handle_tpc_mpc_exception,
236 .zbc_s_query_table = gr_gv11b_zbc_s_query_table,
237 .load_zbc_s_default_tbl = gr_gv11b_load_stencil_default_tbl,
238 .handle_gpc_gpcmmu_exception =
239 gr_gv11b_handle_gpc_gpcmmu_exception,
240 .add_zbc_type_s = gr_gv11b_add_zbc_type_s,
241 .get_egpc_base = gv11b_gr_get_egpc_base,
242 .get_egpc_etpc_num = gv11b_gr_get_egpc_etpc_num,
243 .handle_gpc_gpccs_exception =
244 gr_gv11b_handle_gpc_gpccs_exception,
245 .load_zbc_s_tbl = gr_gv11b_load_stencil_tbl,
246 .access_smpc_reg = gv11b_gr_access_smpc_reg,
247 .is_egpc_addr = gv11b_gr_pri_is_egpc_addr,
248 .add_zbc_s = gr_gv11b_add_zbc_stencil,
249 .handle_gcc_exception = gr_gv11b_handle_gcc_exception,
250 .init_sw_veid_bundle = gr_gv11b_init_sw_veid_bundle,
251 .handle_tpc_sm_ecc_exception =
252 gr_gv11b_handle_tpc_sm_ecc_exception,
253 .decode_egpc_addr = gv11b_gr_decode_egpc_addr,
254 .init_ctxsw_hdr_data = gr_gp10b_init_ctxsw_hdr_data,
255 },
256 .fb = {
257 .reset = gv11b_fb_reset,
258 .init_hw = gk20a_fb_init_hw,
259 .init_fs_state = gv11b_fb_init_fs_state,
260 .init_cbc = gv11b_fb_init_cbc,
261 .set_mmu_page_size = gm20b_fb_set_mmu_page_size,
262 .set_use_full_comp_tag_line =
263 gm20b_fb_set_use_full_comp_tag_line,
264 .compression_page_size = gp10b_fb_compression_page_size,
265 .compressible_page_size = gp10b_fb_compressible_page_size,
266 .vpr_info_fetch = gm20b_fb_vpr_info_fetch,
267 .dump_vpr_wpr_info = gm20b_fb_dump_vpr_wpr_info,
268 .read_wpr_info = gm20b_fb_read_wpr_info,
269 .is_debug_mode_enabled = NULL,
270 .set_debug_mode = vgpu_mm_mmu_set_debug_mode,
271 .tlb_invalidate = vgpu_mm_tlb_invalidate,
272 .hub_isr = gv11b_fb_hub_isr,
273 },
274 .clock_gating = {
275 .slcg_bus_load_gating_prod =
276 gv11b_slcg_bus_load_gating_prod,
277 .slcg_ce2_load_gating_prod =
278 gv11b_slcg_ce2_load_gating_prod,
279 .slcg_chiplet_load_gating_prod =
280 gv11b_slcg_chiplet_load_gating_prod,
281 .slcg_ctxsw_firmware_load_gating_prod =
282 gv11b_slcg_ctxsw_firmware_load_gating_prod,
283 .slcg_fb_load_gating_prod =
284 gv11b_slcg_fb_load_gating_prod,
285 .slcg_fifo_load_gating_prod =
286 gv11b_slcg_fifo_load_gating_prod,
287 .slcg_gr_load_gating_prod =
288 gr_gv11b_slcg_gr_load_gating_prod,
289 .slcg_ltc_load_gating_prod =
290 ltc_gv11b_slcg_ltc_load_gating_prod,
291 .slcg_perf_load_gating_prod =
292 gv11b_slcg_perf_load_gating_prod,
293 .slcg_priring_load_gating_prod =
294 gv11b_slcg_priring_load_gating_prod,
295 .slcg_pmu_load_gating_prod =
296 gv11b_slcg_pmu_load_gating_prod,
297 .slcg_therm_load_gating_prod =
298 gv11b_slcg_therm_load_gating_prod,
299 .slcg_xbar_load_gating_prod =
300 gv11b_slcg_xbar_load_gating_prod,
301 .blcg_bus_load_gating_prod =
302 gv11b_blcg_bus_load_gating_prod,
303 .blcg_ce_load_gating_prod =
304 gv11b_blcg_ce_load_gating_prod,
305 .blcg_ctxsw_firmware_load_gating_prod =
306 gv11b_blcg_ctxsw_firmware_load_gating_prod,
307 .blcg_fb_load_gating_prod =
308 gv11b_blcg_fb_load_gating_prod,
309 .blcg_fifo_load_gating_prod =
310 gv11b_blcg_fifo_load_gating_prod,
311 .blcg_gr_load_gating_prod =
312 gv11b_blcg_gr_load_gating_prod,
313 .blcg_ltc_load_gating_prod =
314 gv11b_blcg_ltc_load_gating_prod,
315 .blcg_pwr_csb_load_gating_prod =
316 gv11b_blcg_pwr_csb_load_gating_prod,
317 .blcg_pmu_load_gating_prod =
318 gv11b_blcg_pmu_load_gating_prod,
319 .blcg_xbar_load_gating_prod =
320 gv11b_blcg_xbar_load_gating_prod,
321 .pg_gr_load_gating_prod =
322 gr_gv11b_pg_gr_load_gating_prod,
323 },
324 .fifo = {
325 .init_fifo_setup_hw = vgpu_gv11b_init_fifo_setup_hw,
326 .bind_channel = vgpu_channel_bind,
327 .unbind_channel = vgpu_channel_unbind,
328 .disable_channel = vgpu_channel_disable,
329 .enable_channel = vgpu_channel_enable,
330 .alloc_inst = vgpu_channel_alloc_inst,
331 .free_inst = vgpu_channel_free_inst,
332 .setup_ramfc = vgpu_channel_setup_ramfc,
333 .channel_set_timeslice = vgpu_channel_set_timeslice,
334 .default_timeslice_us = vgpu_fifo_default_timeslice_us,
335 .setup_userd = gk20a_fifo_setup_userd,
336 .userd_gp_get = gv11b_userd_gp_get,
337 .userd_gp_put = gv11b_userd_gp_put,
338 .userd_pb_get = gv11b_userd_pb_get,
339 .pbdma_acquire_val = gk20a_fifo_pbdma_acquire_val,
340 .preempt_channel = vgpu_fifo_preempt_channel,
341 .preempt_tsg = vgpu_fifo_preempt_tsg,
342 .enable_tsg = vgpu_enable_tsg,
343 .disable_tsg = gk20a_disable_tsg,
344 .tsg_verify_channel_status = NULL,
345 .tsg_verify_status_ctx_reload = NULL,
346 /* TODO: implement it for CE fault */
347 .tsg_verify_status_faulted = NULL,
348 .update_runlist = vgpu_fifo_update_runlist,
349 .trigger_mmu_fault = NULL,
350 .get_mmu_fault_info = NULL,
351 .wait_engine_idle = vgpu_fifo_wait_engine_idle,
352 .get_num_fifos = gv11b_fifo_get_num_fifos,
353 .get_pbdma_signature = gp10b_fifo_get_pbdma_signature,
354 .set_runlist_interleave = vgpu_fifo_set_runlist_interleave,
355 .tsg_set_timeslice = vgpu_tsg_set_timeslice,
356 .tsg_open = vgpu_tsg_open,
357 .force_reset_ch = vgpu_fifo_force_reset_ch,
358 .engine_enum_from_type = gp10b_fifo_engine_enum_from_type,
359 .device_info_data_parse = gp10b_device_info_data_parse,
360 .eng_runlist_base_size = fifo_eng_runlist_base__size_1_v,
361 .init_engine_info = vgpu_fifo_init_engine_info,
362 .runlist_entry_size = ram_rl_entry_size_v,
363 .get_tsg_runlist_entry = gv11b_get_tsg_runlist_entry,
364 .get_ch_runlist_entry = gv11b_get_ch_runlist_entry,
365 .is_fault_engine_subid_gpc = gv11b_is_fault_engine_subid_gpc,
366 .dump_pbdma_status = gk20a_dump_pbdma_status,
367 .dump_eng_status = gv11b_dump_eng_status,
368 .dump_channel_status_ramfc = gv11b_dump_channel_status_ramfc,
369 .intr_0_error_mask = gv11b_fifo_intr_0_error_mask,
370 .is_preempt_pending = gv11b_fifo_is_preempt_pending,
371 .init_pbdma_intr_descs = gv11b_fifo_init_pbdma_intr_descs,
372 .reset_enable_hw = gv11b_init_fifo_reset_enable_hw,
373 .teardown_ch_tsg = gv11b_fifo_teardown_ch_tsg,
374 .handle_sched_error = gv11b_fifo_handle_sched_error,
375 .handle_pbdma_intr_0 = gv11b_fifo_handle_pbdma_intr_0,
376 .handle_pbdma_intr_1 = gv11b_fifo_handle_pbdma_intr_1,
377 .init_eng_method_buffers = gv11b_fifo_init_eng_method_buffers,
378 .deinit_eng_method_buffers =
379 gv11b_fifo_deinit_eng_method_buffers,
380 .tsg_bind_channel = vgpu_gv11b_tsg_bind_channel,
381 .tsg_unbind_channel = vgpu_tsg_unbind_channel,
382#ifdef CONFIG_TEGRA_GK20A_NVHOST
383 .alloc_syncpt_buf = vgpu_gv11b_fifo_alloc_syncpt_buf,
384 .free_syncpt_buf = gv11b_fifo_free_syncpt_buf,
385 .add_syncpt_wait_cmd = gv11b_fifo_add_syncpt_wait_cmd,
386 .get_syncpt_wait_cmd_size = gv11b_fifo_get_syncpt_wait_cmd_size,
387 .add_syncpt_incr_cmd = gv11b_fifo_add_syncpt_incr_cmd,
388 .get_syncpt_incr_cmd_size = gv11b_fifo_get_syncpt_incr_cmd_size,
389#endif
390 .resetup_ramfc = NULL,
391 .reschedule_runlist = NULL,
392 .device_info_fault_id = top_device_info_data_fault_id_enum_v,
393 .free_channel_ctx_header = vgpu_gv11b_free_subctx_header,
394 .preempt_ch_tsg = gv11b_fifo_preempt_ch_tsg,
395 .handle_ctxsw_timeout = gv11b_fifo_handle_ctxsw_timeout,
396 },
397 .gr_ctx = {
398 .get_netlist_name = gr_gv11b_get_netlist_name,
399 .is_fw_defined = gr_gv11b_is_firmware_defined,
400 },
401#ifdef CONFIG_GK20A_CTXSW_TRACE
402 .fecs_trace = {
403 .alloc_user_buffer = NULL,
404 .free_user_buffer = NULL,
405 .mmap_user_buffer = NULL,
406 .init = NULL,
407 .deinit = NULL,
408 .enable = NULL,
409 .disable = NULL,
410 .is_enabled = NULL,
411 .reset = NULL,
412 .flush = NULL,
413 .poll = NULL,
414 .bind_channel = NULL,
415 .unbind_channel = NULL,
416 .max_entries = NULL,
417 },
418#endif /* CONFIG_GK20A_CTXSW_TRACE */
419 .mm = {
420 /* FIXME: add support for sparse mappings */
421 .support_sparse = NULL,
422 .gmmu_map = vgpu_gp10b_locked_gmmu_map,
423 .gmmu_unmap = vgpu_locked_gmmu_unmap,
424 .vm_bind_channel = vgpu_vm_bind_channel,
425 .fb_flush = vgpu_mm_fb_flush,
426 .l2_invalidate = vgpu_mm_l2_invalidate,
427 .l2_flush = vgpu_mm_l2_flush,
428 .cbc_clean = gk20a_mm_cbc_clean,
429 .set_big_page_size = gm20b_mm_set_big_page_size,
430 .get_big_page_sizes = gm20b_mm_get_big_page_sizes,
431 .get_default_big_page_size = gp10b_mm_get_default_big_page_size,
432 .gpu_phys_addr = gm20b_gpu_phys_addr,
433 .get_iommu_bit = gk20a_mm_get_iommu_bit,
434 .get_mmu_levels = gp10b_mm_get_mmu_levels,
435 .init_pdb = gp10b_mm_init_pdb,
436 .init_mm_setup_hw = vgpu_gp10b_init_mm_setup_hw,
437 .is_bar1_supported = gv11b_mm_is_bar1_supported,
438 .init_inst_block = gv11b_init_inst_block,
439 .mmu_fault_pending = gv11b_mm_mmu_fault_pending,
440 .get_kind_invalid = gm20b_get_kind_invalid,
441 .get_kind_pitch = gm20b_get_kind_pitch,
442 .init_bar2_vm = gb10b_init_bar2_vm,
443 .init_bar2_mm_hw_setup = gv11b_init_bar2_mm_hw_setup,
444 .remove_bar2_vm = gv11b_mm_remove_bar2_vm,
445 .fault_info_mem_destroy = gv11b_mm_fault_info_mem_destroy,
446 },
447 .therm = {
448 .init_therm_setup_hw = gp10b_init_therm_setup_hw,
449 .elcg_init_idle_filters = gv11b_elcg_init_idle_filters,
450 },
451 .pmu = {
452 .pmu_setup_elpg = gp10b_pmu_setup_elpg,
453 .pmu_get_queue_head = pwr_pmu_queue_head_r,
454 .pmu_get_queue_head_size = pwr_pmu_queue_head__size_1_v,
455 .pmu_get_queue_tail = pwr_pmu_queue_tail_r,
456 .pmu_get_queue_tail_size = pwr_pmu_queue_tail__size_1_v,
457 .pmu_queue_head = gk20a_pmu_queue_head,
458 .pmu_queue_tail = gk20a_pmu_queue_tail,
459 .pmu_msgq_tail = gk20a_pmu_msgq_tail,
460 .pmu_mutex_size = pwr_pmu_mutex__size_1_v,
461 .pmu_mutex_acquire = gk20a_pmu_mutex_acquire,
462 .pmu_mutex_release = gk20a_pmu_mutex_release,
463 .write_dmatrfbase = gp10b_write_dmatrfbase,
464 .pmu_elpg_statistics = gp106_pmu_elpg_statistics,
465 .pmu_pg_init_param = gv11b_pg_gr_init,
466 .pmu_pg_supported_engines_list = gk20a_pmu_pg_engines_list,
467 .pmu_pg_engines_feature_list = gk20a_pmu_pg_feature_list,
468 .dump_secure_fuses = pmu_dump_security_fuses_gp10b,
469 .reset_engine = gp106_pmu_engine_reset,
470 .is_engine_in_reset = gp106_pmu_is_engine_in_reset,
471 .pmu_nsbootstrap = gv11b_pmu_bootstrap,
472 .pmu_pg_set_sub_feature_mask = gv11b_pg_set_subfeature_mask,
473 .is_pmu_supported = gv11b_is_pmu_supported,
474 },
475 .regops = {
476 .get_global_whitelist_ranges =
477 gv11b_get_global_whitelist_ranges,
478 .get_global_whitelist_ranges_count =
479 gv11b_get_global_whitelist_ranges_count,
480 .get_context_whitelist_ranges =
481 gv11b_get_context_whitelist_ranges,
482 .get_context_whitelist_ranges_count =
483 gv11b_get_context_whitelist_ranges_count,
484 .get_runcontrol_whitelist = gv11b_get_runcontrol_whitelist,
485 .get_runcontrol_whitelist_count =
486 gv11b_get_runcontrol_whitelist_count,
487 .get_runcontrol_whitelist_ranges =
488 gv11b_get_runcontrol_whitelist_ranges,
489 .get_runcontrol_whitelist_ranges_count =
490 gv11b_get_runcontrol_whitelist_ranges_count,
491 .get_qctl_whitelist = gv11b_get_qctl_whitelist,
492 .get_qctl_whitelist_count = gv11b_get_qctl_whitelist_count,
493 .get_qctl_whitelist_ranges = gv11b_get_qctl_whitelist_ranges,
494 .get_qctl_whitelist_ranges_count =
495 gv11b_get_qctl_whitelist_ranges_count,
496 .apply_smpc_war = gv11b_apply_smpc_war,
497 },
498 .mc = {
499 .intr_enable = mc_gv11b_intr_enable,
500 .intr_unit_config = mc_gp10b_intr_unit_config,
501 .isr_stall = mc_gp10b_isr_stall,
502 .intr_stall = mc_gp10b_intr_stall,
503 .intr_stall_pause = mc_gp10b_intr_stall_pause,
504 .intr_stall_resume = mc_gp10b_intr_stall_resume,
505 .intr_nonstall = mc_gp10b_intr_nonstall,
506 .intr_nonstall_pause = mc_gp10b_intr_nonstall_pause,
507 .intr_nonstall_resume = mc_gp10b_intr_nonstall_resume,
508 .enable = gk20a_mc_enable,
509 .disable = gk20a_mc_disable,
510 .reset = gk20a_mc_reset,
511 .boot_0 = gk20a_mc_boot_0,
512 .is_intr1_pending = mc_gp10b_is_intr1_pending,
513 .is_intr_hub_pending = gv11b_mc_is_intr_hub_pending,
514 },
515 .debug = {
516 .show_dump = NULL,
517 },
518 .dbg_session_ops = {
519 .exec_reg_ops = vgpu_exec_regops,
520 .dbg_set_powergate = vgpu_dbg_set_powergate,
521 .check_and_set_global_reservation =
522 vgpu_check_and_set_global_reservation,
523 .check_and_set_context_reservation =
524 vgpu_check_and_set_context_reservation,
525 .release_profiler_reservation =
526 vgpu_release_profiler_reservation,
527 .perfbuffer_enable = vgpu_perfbuffer_enable,
528 .perfbuffer_disable = vgpu_perfbuffer_disable,
529 },
530 .bus = {
531 .init_hw = gk20a_bus_init_hw,
532 .isr = gk20a_bus_isr,
533 .read_ptimer = vgpu_read_ptimer,
534 .get_timestamps_zipper = vgpu_get_timestamps_zipper,
535 .bar1_bind = NULL,
536 },
537#if defined(CONFIG_GK20A_CYCLE_STATS)
538 .css = {
539 .enable_snapshot = vgpu_css_enable_snapshot_buffer,
540 .disable_snapshot = vgpu_css_release_snapshot_buffer,
541 .check_data_available = vgpu_css_flush_snapshots,
542 .set_handled_snapshots = NULL,
543 .allocate_perfmon_ids = NULL,
544 .release_perfmon_ids = NULL,
545 },
546#endif
547 .falcon = {
548 .falcon_hal_sw_init = gk20a_falcon_hal_sw_init,
549 },
550 .priv_ring = {
551 .isr = gp10b_priv_ring_isr,
552 },
553 .chip_init_gpu_characteristics = vgpu_gv11b_init_gpu_characteristics,
554 .get_litter_value = gv11b_get_litter_value,
555};
556
557int vgpu_gv11b_init_hal(struct gk20a *g)
558{
559 struct gpu_ops *gops = &g->ops;
560 u32 val;
561 bool priv_security;
562
563 gops->ltc = vgpu_gv11b_ops.ltc;
564 gops->ce2 = vgpu_gv11b_ops.ce2;
565 gops->gr = vgpu_gv11b_ops.gr;
566 gops->fb = vgpu_gv11b_ops.fb;
567 gops->clock_gating = vgpu_gv11b_ops.clock_gating;
568 gops->fifo = vgpu_gv11b_ops.fifo;
569 gops->gr_ctx = vgpu_gv11b_ops.gr_ctx;
570 gops->mm = vgpu_gv11b_ops.mm;
571 gops->fecs_trace = vgpu_gv11b_ops.fecs_trace;
572 gops->therm = vgpu_gv11b_ops.therm;
573 gops->pmu = vgpu_gv11b_ops.pmu;
574 gops->regops = vgpu_gv11b_ops.regops;
575 gops->mc = vgpu_gv11b_ops.mc;
576 gops->debug = vgpu_gv11b_ops.debug;
577 gops->dbg_session_ops = vgpu_gv11b_ops.dbg_session_ops;
578 gops->bus = vgpu_gv11b_ops.bus;
579#if defined(CONFIG_GK20A_CYCLE_STATS)
580 gops->css = vgpu_gv11b_ops.css;
581#endif
582 gops->falcon = vgpu_gv11b_ops.falcon;
583 gops->priv_ring = vgpu_gv11b_ops.priv_ring;
584
585 /* Lone functions */
586 gops->chip_init_gpu_characteristics =
587 vgpu_gv11b_ops.chip_init_gpu_characteristics;
588 gops->get_litter_value = vgpu_gv11b_ops.get_litter_value;
589
590 val = gk20a_readl(g, fuse_opt_priv_sec_en_r());
591 if (val) {
592 priv_security = true;
593 pr_err("priv security is enabled\n");
594 } else {
595 priv_security = false;
596 pr_err("priv security is disabled\n");
597 }
598 __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, false);
599 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, priv_security);
600 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, priv_security);
601
602 /* priv security dependent ops */
603 if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) {
604 /* Add in ops from gm20b acr */
605 gops->pmu.prepare_ucode = gp106_prepare_ucode_blob,
606 gops->pmu.pmu_setup_hw_and_bootstrap = gv11b_bootstrap_hs_flcn,
607 gops->pmu.get_wpr = gm20b_wpr_info,
608 gops->pmu.alloc_blob_space = gm20b_alloc_blob_space,
609 gops->pmu.pmu_populate_loader_cfg =
610 gp106_pmu_populate_loader_cfg,
611 gops->pmu.flcn_populate_bl_dmem_desc =
612 gp106_flcn_populate_bl_dmem_desc,
613 gops->pmu.falcon_wait_for_halt = pmu_wait_for_halt,
614 gops->pmu.falcon_clear_halt_interrupt_status =
615 clear_halt_interrupt_status,
616 gops->pmu.init_falcon_setup_hw = gv11b_init_pmu_setup_hw1,
617
618 gops->pmu.init_wpr_region = gm20b_pmu_init_acr;
619 gops->pmu.load_lsfalcon_ucode = gp10b_load_falcon_ucode;
620 gops->pmu.is_lazy_bootstrap = gv11b_is_lazy_bootstrap,
621 gops->pmu.is_priv_load = gv11b_is_priv_load,
622
623 gops->gr.load_ctxsw_ucode = gr_gm20b_load_ctxsw_ucode;
624 } else {
625 /* Inherit from gk20a */
626 gops->pmu.prepare_ucode = nvgpu_pmu_prepare_ns_ucode_blob,
627 gops->pmu.pmu_setup_hw_and_bootstrap = gk20a_init_pmu_setup_hw1,
628
629 gops->pmu.load_lsfalcon_ucode = NULL;
630 gops->pmu.init_wpr_region = NULL;
631 gops->pmu.pmu_setup_hw_and_bootstrap = gp10b_init_pmu_setup_hw1;
632
633 gops->gr.load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode;
634 }
635
636 __nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false);
637 g->bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT;
638
639 g->name = "gv11b";
640
641 return 0;
642}
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-16 09:25:39 -0400