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path: root/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c
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Diffstat (limited to 'drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c')
-rw-r--r--drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c603
1 files changed, 603 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c
new file mode 100644
index 00000000..76f7b389
--- /dev/null
+++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c
@@ -0,0 +1,603 @@
1/*
2 * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#include <gk20a/gk20a.h>
24#include <gv11b/hal_gv11b.h>
25#include <nvgpu/vgpu/vgpu.h>
26
27#include "vgpu/fifo_vgpu.h"
28#include "vgpu/gr_vgpu.h"
29#include "vgpu/ltc_vgpu.h"
30#include "vgpu/mm_vgpu.h"
31#include "vgpu/dbg_vgpu.h"
32#include "vgpu/fecs_trace_vgpu.h"
33#include "vgpu/css_vgpu.h"
34#include "vgpu/gm20b/vgpu_gr_gm20b.h"
35#include "vgpu/gp10b/vgpu_mm_gp10b.h"
36#include "vgpu/gp10b/vgpu_gr_gp10b.h"
37
38#include <gk20a/fb_gk20a.h>
39#include <gk20a/flcn_gk20a.h>
40#include <gk20a/bus_gk20a.h>
41#include <gk20a/mc_gk20a.h>
42
43#include <gm20b/gr_gm20b.h>
44#include <gm20b/fb_gm20b.h>
45#include <gm20b/fifo_gm20b.h>
46#include <gm20b/pmu_gm20b.h>
47#include <gm20b/mm_gm20b.h>
48#include <gm20b/acr_gm20b.h>
49#include <gm20b/ltc_gm20b.h>
50
51#include <gp10b/fb_gp10b.h>
52#include <gp10b/pmu_gp10b.h>
53#include <gp10b/mm_gp10b.h>
54#include <gp10b/mc_gp10b.h>
55#include <gp10b/ce_gp10b.h>
56#include "gp10b/gr_gp10b.h"
57#include <gp10b/fifo_gp10b.h>
58#include <gp10b/therm_gp10b.h>
59#include <gp10b/priv_ring_gp10b.h>
60#include <gp10b/ltc_gp10b.h>
61
62#include <gp106/pmu_gp106.h>
63#include <gp106/acr_gp106.h>
64
65#include <gv11b/fb_gv11b.h>
66#include <gv11b/pmu_gv11b.h>
67#include <gv11b/acr_gv11b.h>
68#include <gv11b/mm_gv11b.h>
69#include <gv11b/mc_gv11b.h>
70#include <gv11b/ce_gv11b.h>
71#include <gv11b/fifo_gv11b.h>
72#include <gv11b/therm_gv11b.h>
73#include <gv11b/regops_gv11b.h>
74#include <gv11b/gr_ctx_gv11b.h>
75#include <gv11b/ltc_gv11b.h>
76#include <gv11b/gv11b_gating_reglist.h>
77#include <gv11b/gr_gv11b.h>
78
79#include <nvgpu/enabled.h>
80
81#include "vgpu_gv11b.h"
82#include "vgpu_gr_gv11b.h"
83#include "vgpu_fifo_gv11b.h"
84#include "vgpu_subctx_gv11b.h"
85#include "vgpu_tsg_gv11b.h"
86
87#include <nvgpu/hw/gv11b/hw_fuse_gv11b.h>
88#include <nvgpu/hw/gv11b/hw_fifo_gv11b.h>
89#include <nvgpu/hw/gv11b/hw_ram_gv11b.h>
90#include <nvgpu/hw/gv11b/hw_top_gv11b.h>
91#include <nvgpu/hw/gv11b/hw_pwr_gv11b.h>
92
93static const struct gpu_ops vgpu_gv11b_ops = {
94 .ltc = {
95 .determine_L2_size_bytes = vgpu_determine_L2_size_bytes,
96 .set_zbc_s_entry = gv11b_ltc_set_zbc_stencil_entry,
97 .set_zbc_color_entry = gm20b_ltc_set_zbc_color_entry,
98 .set_zbc_depth_entry = gm20b_ltc_set_zbc_depth_entry,
99 .init_cbc = NULL,
100 .init_fs_state = vgpu_ltc_init_fs_state,
101 .init_comptags = vgpu_ltc_init_comptags,
102 .cbc_ctrl = NULL,
103 .isr = gv11b_ltc_isr,
104 .flush = gm20b_flush_ltc,
105 .set_enabled = gp10b_ltc_set_enabled,
106 },
107 .ce2 = {
108 .isr_stall = gv11b_ce_isr,
109 .isr_nonstall = gp10b_ce_nonstall_isr,
110 .get_num_pce = vgpu_ce_get_num_pce,
111 },
112 .gr = {
113 .init_gpc_mmu = gr_gv11b_init_gpc_mmu,
114 .bundle_cb_defaults = gr_gv11b_bundle_cb_defaults,
115 .cb_size_default = gr_gv11b_cb_size_default,
116 .calc_global_ctx_buffer_size =
117 gr_gv11b_calc_global_ctx_buffer_size,
118 .commit_global_attrib_cb = gr_gv11b_commit_global_attrib_cb,
119 .commit_global_bundle_cb = gr_gp10b_commit_global_bundle_cb,
120 .commit_global_cb_manager = gr_gp10b_commit_global_cb_manager,
121 .commit_global_pagepool = gr_gp10b_commit_global_pagepool,
122 .handle_sw_method = gr_gv11b_handle_sw_method,
123 .set_alpha_circular_buffer_size =
124 gr_gv11b_set_alpha_circular_buffer_size,
125 .set_circular_buffer_size = gr_gv11b_set_circular_buffer_size,
126 .enable_hww_exceptions = gr_gv11b_enable_hww_exceptions,
127 .is_valid_class = gr_gv11b_is_valid_class,
128 .is_valid_gfx_class = gr_gv11b_is_valid_gfx_class,
129 .is_valid_compute_class = gr_gv11b_is_valid_compute_class,
130 .get_sm_dsm_perf_regs = gv11b_gr_get_sm_dsm_perf_regs,
131 .get_sm_dsm_perf_ctrl_regs = gv11b_gr_get_sm_dsm_perf_ctrl_regs,
132 .init_fs_state = vgpu_gr_init_fs_state,
133 .set_hww_esr_report_mask = gv11b_gr_set_hww_esr_report_mask,
134 .falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments,
135 .load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode,
136 .set_gpc_tpc_mask = gr_gv11b_set_gpc_tpc_mask,
137 .get_gpc_tpc_mask = vgpu_gr_get_gpc_tpc_mask,
138 .alloc_obj_ctx = vgpu_gr_alloc_obj_ctx,
139 .bind_ctxsw_zcull = vgpu_gr_bind_ctxsw_zcull,
140 .get_zcull_info = vgpu_gr_get_zcull_info,
141 .is_tpc_addr = gr_gm20b_is_tpc_addr,
142 .get_tpc_num = gr_gm20b_get_tpc_num,
143 .detect_sm_arch = vgpu_gr_detect_sm_arch,
144 .add_zbc_color = gr_gp10b_add_zbc_color,
145 .add_zbc_depth = gr_gp10b_add_zbc_depth,
146 .zbc_set_table = vgpu_gr_add_zbc,
147 .zbc_query_table = vgpu_gr_query_zbc,
148 .pmu_save_zbc = gk20a_pmu_save_zbc,
149 .add_zbc = gr_gk20a_add_zbc,
150 .pagepool_default_size = gr_gv11b_pagepool_default_size,
151 .init_ctx_state = vgpu_gr_gp10b_init_ctx_state,
152 .alloc_gr_ctx = vgpu_gr_gp10b_alloc_gr_ctx,
153 .free_gr_ctx = vgpu_gr_free_gr_ctx,
154 .update_ctxsw_preemption_mode =
155 gr_gp10b_update_ctxsw_preemption_mode,
156 .dump_gr_regs = NULL,
157 .update_pc_sampling = gr_gm20b_update_pc_sampling,
158 .get_fbp_en_mask = vgpu_gr_get_fbp_en_mask,
159 .get_max_ltc_per_fbp = vgpu_gr_get_max_ltc_per_fbp,
160 .get_max_lts_per_ltc = vgpu_gr_get_max_lts_per_ltc,
161 .get_rop_l2_en_mask = vgpu_gr_rop_l2_en_mask,
162 .get_max_fbps_count = vgpu_gr_get_max_fbps_count,
163 .init_sm_dsm_reg_info = gv11b_gr_init_sm_dsm_reg_info,
164 .wait_empty = gr_gv11b_wait_empty,
165 .init_cyclestats = vgpu_gr_gm20b_init_cyclestats,
166 .set_sm_debug_mode = vgpu_gr_set_sm_debug_mode,
167 .enable_cde_in_fecs = gr_gm20b_enable_cde_in_fecs,
168 .bpt_reg_info = gv11b_gr_bpt_reg_info,
169 .get_access_map = gr_gv11b_get_access_map,
170 .handle_fecs_error = gr_gv11b_handle_fecs_error,
171 .handle_sm_exception = gr_gk20a_handle_sm_exception,
172 .handle_tex_exception = gr_gv11b_handle_tex_exception,
173 .enable_gpc_exceptions = gr_gv11b_enable_gpc_exceptions,
174 .enable_exceptions = gr_gv11b_enable_exceptions,
175 .get_lrf_tex_ltc_dram_override = get_ecc_override_val,
176 .update_smpc_ctxsw_mode = vgpu_gr_update_smpc_ctxsw_mode,
177 .update_hwpm_ctxsw_mode = vgpu_gr_update_hwpm_ctxsw_mode,
178 .record_sm_error_state = gv11b_gr_record_sm_error_state,
179 .update_sm_error_state = gv11b_gr_update_sm_error_state,
180 .clear_sm_error_state = vgpu_gr_clear_sm_error_state,
181 .suspend_contexts = vgpu_gr_suspend_contexts,
182 .resume_contexts = vgpu_gr_resume_contexts,
183 .get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags,
184 .init_sm_id_table = vgpu_gr_init_sm_id_table,
185 .load_smid_config = gr_gv11b_load_smid_config,
186 .program_sm_id_numbering = gr_gv11b_program_sm_id_numbering,
187 .is_ltcs_ltss_addr = gr_gm20b_is_ltcs_ltss_addr,
188 .is_ltcn_ltss_addr = gr_gm20b_is_ltcn_ltss_addr,
189 .split_lts_broadcast_addr = gr_gm20b_split_lts_broadcast_addr,
190 .split_ltc_broadcast_addr = gr_gm20b_split_ltc_broadcast_addr,
191 .setup_rop_mapping = gr_gv11b_setup_rop_mapping,
192 .program_zcull_mapping = gr_gv11b_program_zcull_mapping,
193 .commit_global_timeslice = gr_gv11b_commit_global_timeslice,
194 .commit_inst = vgpu_gr_gv11b_commit_inst,
195 .write_zcull_ptr = gr_gv11b_write_zcull_ptr,
196 .write_pm_ptr = gr_gv11b_write_pm_ptr,
197 .init_elcg_mode = gr_gv11b_init_elcg_mode,
198 .load_tpc_mask = gr_gv11b_load_tpc_mask,
199 .inval_icache = gr_gk20a_inval_icache,
200 .trigger_suspend = gv11b_gr_sm_trigger_suspend,
201 .wait_for_pause = gr_gk20a_wait_for_pause,
202 .resume_from_pause = gv11b_gr_resume_from_pause,
203 .clear_sm_errors = gr_gk20a_clear_sm_errors,
204 .tpc_enabled_exceptions = gr_gk20a_tpc_enabled_exceptions,
205 .get_esr_sm_sel = gv11b_gr_get_esr_sm_sel,
206 .sm_debugger_attached = gv11b_gr_sm_debugger_attached,
207 .suspend_single_sm = gv11b_gr_suspend_single_sm,
208 .suspend_all_sms = gv11b_gr_suspend_all_sms,
209 .resume_single_sm = gv11b_gr_resume_single_sm,
210 .resume_all_sms = gv11b_gr_resume_all_sms,
211 .get_sm_hww_warp_esr = gv11b_gr_get_sm_hww_warp_esr,
212 .get_sm_hww_global_esr = gv11b_gr_get_sm_hww_global_esr,
213 .get_sm_no_lock_down_hww_global_esr_mask =
214 gv11b_gr_get_sm_no_lock_down_hww_global_esr_mask,
215 .lock_down_sm = gv11b_gr_lock_down_sm,
216 .wait_for_sm_lock_down = gv11b_gr_wait_for_sm_lock_down,
217 .clear_sm_hww = gv11b_gr_clear_sm_hww,
218 .init_ovr_sm_dsm_perf = gv11b_gr_init_ovr_sm_dsm_perf,
219 .get_ovr_perf_regs = gv11b_gr_get_ovr_perf_regs,
220 .disable_rd_coalesce = gm20a_gr_disable_rd_coalesce,
221 .set_boosted_ctx = NULL,
222 .set_preemption_mode = vgpu_gr_gp10b_set_preemption_mode,
223 .set_czf_bypass = NULL,
224 .pre_process_sm_exception = gr_gv11b_pre_process_sm_exception,
225 .set_preemption_buffer_va = gr_gv11b_set_preemption_buffer_va,
226 .init_preemption_state = NULL,
227 .update_boosted_ctx = NULL,
228 .set_bes_crop_debug3 = gr_gp10b_set_bes_crop_debug3,
229 .set_bes_crop_debug4 = gr_gp10b_set_bes_crop_debug4,
230 .create_gr_sysfs = gr_gv11b_create_sysfs,
231 .set_ctxsw_preemption_mode = vgpu_gr_gp10b_set_ctxsw_preemption_mode,
232 .is_etpc_addr = gv11b_gr_pri_is_etpc_addr,
233 .egpc_etpc_priv_addr_table = gv11b_gr_egpc_etpc_priv_addr_table,
234 .handle_tpc_mpc_exception = gr_gv11b_handle_tpc_mpc_exception,
235 .zbc_s_query_table = gr_gv11b_zbc_s_query_table,
236 .load_zbc_s_default_tbl = gr_gv11b_load_stencil_default_tbl,
237 .handle_gpc_gpcmmu_exception =
238 gr_gv11b_handle_gpc_gpcmmu_exception,
239 .add_zbc_type_s = gr_gv11b_add_zbc_type_s,
240 .get_egpc_base = gv11b_gr_get_egpc_base,
241 .get_egpc_etpc_num = gv11b_gr_get_egpc_etpc_num,
242 .handle_gpc_gpccs_exception =
243 gr_gv11b_handle_gpc_gpccs_exception,
244 .load_zbc_s_tbl = gr_gv11b_load_stencil_tbl,
245 .access_smpc_reg = gv11b_gr_access_smpc_reg,
246 .is_egpc_addr = gv11b_gr_pri_is_egpc_addr,
247 .add_zbc_s = gr_gv11b_add_zbc_stencil,
248 .handle_gcc_exception = gr_gv11b_handle_gcc_exception,
249 .init_sw_veid_bundle = gr_gv11b_init_sw_veid_bundle,
250 .handle_tpc_sm_ecc_exception =
251 gr_gv11b_handle_tpc_sm_ecc_exception,
252 .decode_egpc_addr = gv11b_gr_decode_egpc_addr,
253 .init_ctxsw_hdr_data = gr_gp10b_init_ctxsw_hdr_data,
254 .init_gfxp_wfi_timeout_count =
255 gr_gv11b_init_gfxp_wfi_timeout_count,
256 .get_max_gfxp_wfi_timeout_count =
257 gr_gv11b_get_max_gfxp_wfi_timeout_count,
258 },
259 .fb = {
260 .reset = gv11b_fb_reset,
261 .init_hw = gk20a_fb_init_hw,
262 .init_fs_state = gv11b_fb_init_fs_state,
263 .init_cbc = gv11b_fb_init_cbc,
264 .set_mmu_page_size = gm20b_fb_set_mmu_page_size,
265 .set_use_full_comp_tag_line =
266 gm20b_fb_set_use_full_comp_tag_line,
267 .compression_page_size = gp10b_fb_compression_page_size,
268 .compressible_page_size = gp10b_fb_compressible_page_size,
269 .compression_align_mask = gm20b_fb_compression_align_mask,
270 .vpr_info_fetch = gm20b_fb_vpr_info_fetch,
271 .dump_vpr_wpr_info = gm20b_fb_dump_vpr_wpr_info,
272 .read_wpr_info = gm20b_fb_read_wpr_info,
273 .is_debug_mode_enabled = NULL,
274 .set_debug_mode = vgpu_mm_mmu_set_debug_mode,
275 .tlb_invalidate = vgpu_mm_tlb_invalidate,
276 .hub_isr = gv11b_fb_hub_isr,
277 },
278 .clock_gating = {
279 .slcg_bus_load_gating_prod =
280 gv11b_slcg_bus_load_gating_prod,
281 .slcg_ce2_load_gating_prod =
282 gv11b_slcg_ce2_load_gating_prod,
283 .slcg_chiplet_load_gating_prod =
284 gv11b_slcg_chiplet_load_gating_prod,
285 .slcg_ctxsw_firmware_load_gating_prod =
286 gv11b_slcg_ctxsw_firmware_load_gating_prod,
287 .slcg_fb_load_gating_prod =
288 gv11b_slcg_fb_load_gating_prod,
289 .slcg_fifo_load_gating_prod =
290 gv11b_slcg_fifo_load_gating_prod,
291 .slcg_gr_load_gating_prod =
292 gr_gv11b_slcg_gr_load_gating_prod,
293 .slcg_ltc_load_gating_prod =
294 ltc_gv11b_slcg_ltc_load_gating_prod,
295 .slcg_perf_load_gating_prod =
296 gv11b_slcg_perf_load_gating_prod,
297 .slcg_priring_load_gating_prod =
298 gv11b_slcg_priring_load_gating_prod,
299 .slcg_pmu_load_gating_prod =
300 gv11b_slcg_pmu_load_gating_prod,
301 .slcg_therm_load_gating_prod =
302 gv11b_slcg_therm_load_gating_prod,
303 .slcg_xbar_load_gating_prod =
304 gv11b_slcg_xbar_load_gating_prod,
305 .blcg_bus_load_gating_prod =
306 gv11b_blcg_bus_load_gating_prod,
307 .blcg_ce_load_gating_prod =
308 gv11b_blcg_ce_load_gating_prod,
309 .blcg_ctxsw_firmware_load_gating_prod =
310 gv11b_blcg_ctxsw_firmware_load_gating_prod,
311 .blcg_fb_load_gating_prod =
312 gv11b_blcg_fb_load_gating_prod,
313 .blcg_fifo_load_gating_prod =
314 gv11b_blcg_fifo_load_gating_prod,
315 .blcg_gr_load_gating_prod =
316 gv11b_blcg_gr_load_gating_prod,
317 .blcg_ltc_load_gating_prod =
318 gv11b_blcg_ltc_load_gating_prod,
319 .blcg_pwr_csb_load_gating_prod =
320 gv11b_blcg_pwr_csb_load_gating_prod,
321 .blcg_pmu_load_gating_prod =
322 gv11b_blcg_pmu_load_gating_prod,
323 .blcg_xbar_load_gating_prod =
324 gv11b_blcg_xbar_load_gating_prod,
325 .pg_gr_load_gating_prod =
326 gr_gv11b_pg_gr_load_gating_prod,
327 },
328 .fifo = {
329 .init_fifo_setup_hw = vgpu_gv11b_init_fifo_setup_hw,
330 .bind_channel = vgpu_channel_bind,
331 .unbind_channel = vgpu_channel_unbind,
332 .disable_channel = vgpu_channel_disable,
333 .enable_channel = vgpu_channel_enable,
334 .alloc_inst = vgpu_channel_alloc_inst,
335 .free_inst = vgpu_channel_free_inst,
336 .setup_ramfc = vgpu_channel_setup_ramfc,
337 .default_timeslice_us = vgpu_fifo_default_timeslice_us,
338 .setup_userd = gk20a_fifo_setup_userd,
339 .userd_gp_get = gv11b_userd_gp_get,
340 .userd_gp_put = gv11b_userd_gp_put,
341 .userd_pb_get = gv11b_userd_pb_get,
342 .pbdma_acquire_val = gk20a_fifo_pbdma_acquire_val,
343 .preempt_channel = vgpu_fifo_preempt_channel,
344 .preempt_tsg = vgpu_fifo_preempt_tsg,
345 .enable_tsg = vgpu_enable_tsg,
346 .disable_tsg = gk20a_disable_tsg,
347 .tsg_verify_channel_status = NULL,
348 .tsg_verify_status_ctx_reload = NULL,
349 /* TODO: implement it for CE fault */
350 .tsg_verify_status_faulted = NULL,
351 .update_runlist = vgpu_fifo_update_runlist,
352 .trigger_mmu_fault = NULL,
353 .get_mmu_fault_info = NULL,
354 .wait_engine_idle = vgpu_fifo_wait_engine_idle,
355 .get_num_fifos = gv11b_fifo_get_num_fifos,
356 .get_pbdma_signature = gp10b_fifo_get_pbdma_signature,
357 .set_runlist_interleave = vgpu_fifo_set_runlist_interleave,
358 .tsg_set_timeslice = vgpu_tsg_set_timeslice,
359 .tsg_open = vgpu_tsg_open,
360 .tsg_release = vgpu_tsg_release,
361 .force_reset_ch = vgpu_fifo_force_reset_ch,
362 .engine_enum_from_type = gp10b_fifo_engine_enum_from_type,
363 .device_info_data_parse = gp10b_device_info_data_parse,
364 .eng_runlist_base_size = fifo_eng_runlist_base__size_1_v,
365 .init_engine_info = vgpu_fifo_init_engine_info,
366 .runlist_entry_size = ram_rl_entry_size_v,
367 .get_tsg_runlist_entry = gv11b_get_tsg_runlist_entry,
368 .get_ch_runlist_entry = gv11b_get_ch_runlist_entry,
369 .is_fault_engine_subid_gpc = gv11b_is_fault_engine_subid_gpc,
370 .dump_pbdma_status = gk20a_dump_pbdma_status,
371 .dump_eng_status = gv11b_dump_eng_status,
372 .dump_channel_status_ramfc = gv11b_dump_channel_status_ramfc,
373 .intr_0_error_mask = gv11b_fifo_intr_0_error_mask,
374 .is_preempt_pending = gv11b_fifo_is_preempt_pending,
375 .init_pbdma_intr_descs = gv11b_fifo_init_pbdma_intr_descs,
376 .reset_enable_hw = gv11b_init_fifo_reset_enable_hw,
377 .teardown_ch_tsg = gv11b_fifo_teardown_ch_tsg,
378 .handle_sched_error = gv11b_fifo_handle_sched_error,
379 .handle_pbdma_intr_0 = gv11b_fifo_handle_pbdma_intr_0,
380 .handle_pbdma_intr_1 = gv11b_fifo_handle_pbdma_intr_1,
381 .init_eng_method_buffers = gv11b_fifo_init_eng_method_buffers,
382 .deinit_eng_method_buffers =
383 gv11b_fifo_deinit_eng_method_buffers,
384 .tsg_bind_channel = vgpu_gv11b_tsg_bind_channel,
385 .tsg_unbind_channel = vgpu_tsg_unbind_channel,
386#ifdef CONFIG_TEGRA_GK20A_NVHOST
387 .alloc_syncpt_buf = vgpu_gv11b_fifo_alloc_syncpt_buf,
388 .free_syncpt_buf = gv11b_fifo_free_syncpt_buf,
389 .add_syncpt_wait_cmd = gv11b_fifo_add_syncpt_wait_cmd,
390 .get_syncpt_wait_cmd_size = gv11b_fifo_get_syncpt_wait_cmd_size,
391 .add_syncpt_incr_cmd = gv11b_fifo_add_syncpt_incr_cmd,
392 .get_syncpt_incr_cmd_size = gv11b_fifo_get_syncpt_incr_cmd_size,
393 .get_sync_ro_map = vgpu_gv11b_fifo_get_sync_ro_map,
394#endif
395 .resetup_ramfc = NULL,
396 .reschedule_runlist = NULL,
397 .device_info_fault_id = top_device_info_data_fault_id_enum_v,
398 .free_channel_ctx_header = vgpu_gv11b_free_subctx_header,
399 .preempt_ch_tsg = gv11b_fifo_preempt_ch_tsg,
400 .handle_ctxsw_timeout = gv11b_fifo_handle_ctxsw_timeout,
401 },
402 .gr_ctx = {
403 .get_netlist_name = gr_gv11b_get_netlist_name,
404 .is_fw_defined = gr_gv11b_is_firmware_defined,
405 },
406#ifdef CONFIG_GK20A_CTXSW_TRACE
407 .fecs_trace = {
408 .alloc_user_buffer = NULL,
409 .free_user_buffer = NULL,
410 .mmap_user_buffer = NULL,
411 .init = NULL,
412 .deinit = NULL,
413 .enable = NULL,
414 .disable = NULL,
415 .is_enabled = NULL,
416 .reset = NULL,
417 .flush = NULL,
418 .poll = NULL,
419 .bind_channel = NULL,
420 .unbind_channel = NULL,
421 .max_entries = NULL,
422 },
423#endif /* CONFIG_GK20A_CTXSW_TRACE */
424 .mm = {
425 /* FIXME: add support for sparse mappings */
426 .support_sparse = NULL,
427 .gmmu_map = vgpu_gp10b_locked_gmmu_map,
428 .gmmu_unmap = vgpu_locked_gmmu_unmap,
429 .vm_bind_channel = vgpu_vm_bind_channel,
430 .fb_flush = vgpu_mm_fb_flush,
431 .l2_invalidate = vgpu_mm_l2_invalidate,
432 .l2_flush = vgpu_mm_l2_flush,
433 .cbc_clean = gk20a_mm_cbc_clean,
434 .set_big_page_size = gm20b_mm_set_big_page_size,
435 .get_big_page_sizes = gm20b_mm_get_big_page_sizes,
436 .get_default_big_page_size = gp10b_mm_get_default_big_page_size,
437 .gpu_phys_addr = gm20b_gpu_phys_addr,
438 .get_iommu_bit = gk20a_mm_get_iommu_bit,
439 .get_mmu_levels = gp10b_mm_get_mmu_levels,
440 .init_pdb = gp10b_mm_init_pdb,
441 .init_mm_setup_hw = vgpu_gp10b_init_mm_setup_hw,
442 .is_bar1_supported = gv11b_mm_is_bar1_supported,
443 .init_inst_block = gv11b_init_inst_block,
444 .mmu_fault_pending = gv11b_mm_mmu_fault_pending,
445 .get_kind_invalid = gm20b_get_kind_invalid,
446 .get_kind_pitch = gm20b_get_kind_pitch,
447 .init_bar2_vm = gp10b_init_bar2_vm,
448 .init_bar2_mm_hw_setup = gv11b_init_bar2_mm_hw_setup,
449 .remove_bar2_vm = gv11b_mm_remove_bar2_vm,
450 .fault_info_mem_destroy = gv11b_mm_fault_info_mem_destroy,
451 },
452 .therm = {
453 .init_therm_setup_hw = gp10b_init_therm_setup_hw,
454 .elcg_init_idle_filters = gv11b_elcg_init_idle_filters,
455 },
456 .pmu = {
457 .pmu_setup_elpg = gp10b_pmu_setup_elpg,
458 .pmu_get_queue_head = pwr_pmu_queue_head_r,
459 .pmu_get_queue_head_size = pwr_pmu_queue_head__size_1_v,
460 .pmu_get_queue_tail = pwr_pmu_queue_tail_r,
461 .pmu_get_queue_tail_size = pwr_pmu_queue_tail__size_1_v,
462 .pmu_queue_head = gk20a_pmu_queue_head,
463 .pmu_queue_tail = gk20a_pmu_queue_tail,
464 .pmu_msgq_tail = gk20a_pmu_msgq_tail,
465 .pmu_mutex_size = pwr_pmu_mutex__size_1_v,
466 .pmu_mutex_acquire = gk20a_pmu_mutex_acquire,
467 .pmu_mutex_release = gk20a_pmu_mutex_release,
468 .write_dmatrfbase = gp10b_write_dmatrfbase,
469 .pmu_elpg_statistics = gp106_pmu_elpg_statistics,
470 .pmu_init_perfmon = nvgpu_pmu_init_perfmon_rpc,
471 .pmu_perfmon_start_sampling = nvgpu_pmu_perfmon_start_sampling_rpc,
472 .pmu_perfmon_stop_sampling = nvgpu_pmu_perfmon_stop_sampling_rpc,
473 .pmu_perfmon_get_samples_rpc = nvgpu_pmu_perfmon_get_samples_rpc,
474 .pmu_pg_init_param = gv11b_pg_gr_init,
475 .pmu_pg_supported_engines_list = gk20a_pmu_pg_engines_list,
476 .pmu_pg_engines_feature_list = gk20a_pmu_pg_feature_list,
477 .dump_secure_fuses = pmu_dump_security_fuses_gp10b,
478 .reset_engine = gp106_pmu_engine_reset,
479 .is_engine_in_reset = gp106_pmu_is_engine_in_reset,
480 .pmu_nsbootstrap = gv11b_pmu_bootstrap,
481 .pmu_pg_set_sub_feature_mask = gv11b_pg_set_subfeature_mask,
482 .is_pmu_supported = gv11b_is_pmu_supported,
483 },
484 .regops = {
485 .get_global_whitelist_ranges =
486 gv11b_get_global_whitelist_ranges,
487 .get_global_whitelist_ranges_count =
488 gv11b_get_global_whitelist_ranges_count,
489 .get_context_whitelist_ranges =
490 gv11b_get_context_whitelist_ranges,
491 .get_context_whitelist_ranges_count =
492 gv11b_get_context_whitelist_ranges_count,
493 .get_runcontrol_whitelist = gv11b_get_runcontrol_whitelist,
494 .get_runcontrol_whitelist_count =
495 gv11b_get_runcontrol_whitelist_count,
496 .get_runcontrol_whitelist_ranges =
497 gv11b_get_runcontrol_whitelist_ranges,
498 .get_runcontrol_whitelist_ranges_count =
499 gv11b_get_runcontrol_whitelist_ranges_count,
500 .get_qctl_whitelist = gv11b_get_qctl_whitelist,
501 .get_qctl_whitelist_count = gv11b_get_qctl_whitelist_count,
502 .get_qctl_whitelist_ranges = gv11b_get_qctl_whitelist_ranges,
503 .get_qctl_whitelist_ranges_count =
504 gv11b_get_qctl_whitelist_ranges_count,
505 .apply_smpc_war = gv11b_apply_smpc_war,
506 },
507 .mc = {
508 .intr_enable = mc_gv11b_intr_enable,
509 .intr_unit_config = mc_gp10b_intr_unit_config,
510 .isr_stall = mc_gp10b_isr_stall,
511 .intr_stall = mc_gp10b_intr_stall,
512 .intr_stall_pause = mc_gp10b_intr_stall_pause,
513 .intr_stall_resume = mc_gp10b_intr_stall_resume,
514 .intr_nonstall = mc_gp10b_intr_nonstall,
515 .intr_nonstall_pause = mc_gp10b_intr_nonstall_pause,
516 .intr_nonstall_resume = mc_gp10b_intr_nonstall_resume,
517 .enable = gk20a_mc_enable,
518 .disable = gk20a_mc_disable,
519 .reset = gk20a_mc_reset,
520 .boot_0 = gk20a_mc_boot_0,
521 .is_intr1_pending = mc_gp10b_is_intr1_pending,
522 .is_intr_hub_pending = gv11b_mc_is_intr_hub_pending,
523 },
524 .debug = {
525 .show_dump = NULL,
526 },
527 .dbg_session_ops = {
528 .exec_reg_ops = vgpu_exec_regops,
529 .dbg_set_powergate = vgpu_dbg_set_powergate,
530 .check_and_set_global_reservation =
531 vgpu_check_and_set_global_reservation,
532 .check_and_set_context_reservation =
533 vgpu_check_and_set_context_reservation,
534 .release_profiler_reservation =
535 vgpu_release_profiler_reservation,
536 .perfbuffer_enable = vgpu_perfbuffer_enable,
537 .perfbuffer_disable = vgpu_perfbuffer_disable,
538 },
539 .bus = {
540 .init_hw = gk20a_bus_init_hw,
541 .isr = gk20a_bus_isr,
542 .read_ptimer = vgpu_read_ptimer,
543 .get_timestamps_zipper = vgpu_get_timestamps_zipper,
544 .bar1_bind = NULL,
545 },
546#if defined(CONFIG_GK20A_CYCLE_STATS)
547 .css = {
548 .enable_snapshot = vgpu_css_enable_snapshot_buffer,
549 .disable_snapshot = vgpu_css_release_snapshot_buffer,
550 .check_data_available = vgpu_css_flush_snapshots,
551 .detach_snapshot = vgpu_css_detach,
552 .set_handled_snapshots = NULL,
553 .allocate_perfmon_ids = NULL,
554 .release_perfmon_ids = NULL,
555 },
556#endif
557 .falcon = {
558 .falcon_hal_sw_init = gk20a_falcon_hal_sw_init,
559 },
560 .priv_ring = {
561 .isr = gp10b_priv_ring_isr,
562 },
563 .chip_init_gpu_characteristics = vgpu_gv11b_init_gpu_characteristics,
564 .get_litter_value = gv11b_get_litter_value,
565};
566
567int vgpu_gv11b_init_hal(struct gk20a *g)
568{
569 struct gpu_ops *gops = &g->ops;
570
571 gops->ltc = vgpu_gv11b_ops.ltc;
572 gops->ce2 = vgpu_gv11b_ops.ce2;
573 gops->gr = vgpu_gv11b_ops.gr;
574 gops->fb = vgpu_gv11b_ops.fb;
575 gops->clock_gating = vgpu_gv11b_ops.clock_gating;
576 gops->fifo = vgpu_gv11b_ops.fifo;
577 gops->gr_ctx = vgpu_gv11b_ops.gr_ctx;
578 gops->mm = vgpu_gv11b_ops.mm;
579#ifdef CONFIG_GK20A_CTXSW_TRACE
580 gops->fecs_trace = vgpu_gv11b_ops.fecs_trace;
581#endif
582 gops->therm = vgpu_gv11b_ops.therm;
583 gops->pmu = vgpu_gv11b_ops.pmu;
584 gops->regops = vgpu_gv11b_ops.regops;
585 gops->mc = vgpu_gv11b_ops.mc;
586 gops->debug = vgpu_gv11b_ops.debug;
587 gops->dbg_session_ops = vgpu_gv11b_ops.dbg_session_ops;
588 gops->bus = vgpu_gv11b_ops.bus;
589#if defined(CONFIG_GK20A_CYCLE_STATS)
590 gops->css = vgpu_gv11b_ops.css;
591#endif
592 gops->falcon = vgpu_gv11b_ops.falcon;
593 gops->priv_ring = vgpu_gv11b_ops.priv_ring;
594
595 /* Lone functions */
596 gops->chip_init_gpu_characteristics =
597 vgpu_gv11b_ops.chip_init_gpu_characteristics;
598 gops->get_litter_value = vgpu_gv11b_ops.get_litter_value;
599
600 g->name = "gv11b";
601
602 return 0;
603}
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-07 17:05:28 -0400