diff options
Diffstat (limited to 'drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.c')
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.c | 117 |
1 files changed, 117 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.c new file mode 100644 index 00000000..ae9d52a7 --- /dev/null +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.c | |||
@@ -0,0 +1,117 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | |||
23 | #include <gk20a/gk20a.h> | ||
24 | |||
25 | #include "vgpu/vgpu.h" | ||
26 | #include "gv11b/fifo_gv11b.h" | ||
27 | #include <nvgpu/nvhost_t19x.h> | ||
28 | |||
29 | #include <linux/tegra_vgpu.h> | ||
30 | |||
31 | #ifdef CONFIG_TEGRA_GK20A_NVHOST | ||
32 | int vgpu_gv11b_fifo_alloc_syncpt_buf(struct channel_gk20a *c, | ||
33 | u32 syncpt_id, struct nvgpu_mem *syncpt_buf) | ||
34 | { | ||
35 | int err; | ||
36 | struct gk20a *g = c->g; | ||
37 | struct vm_gk20a *vm = c->vm; | ||
38 | struct tegra_vgpu_cmd_msg msg = {}; | ||
39 | struct tegra_vgpu_map_syncpt_params *p = &msg.params.t19x.map_syncpt; | ||
40 | |||
41 | /* | ||
42 | * Add ro map for complete sync point shim range in vm. | ||
43 | * All channels sharing same vm will share same ro mapping. | ||
44 | * Create rw map for current channel sync point. | ||
45 | */ | ||
46 | if (!vm->syncpt_ro_map_gpu_va) { | ||
47 | vm->syncpt_ro_map_gpu_va = __nvgpu_vm_alloc_va(vm, | ||
48 | g->syncpt_unit_size, | ||
49 | gmmu_page_size_kernel); | ||
50 | if (!vm->syncpt_ro_map_gpu_va) { | ||
51 | nvgpu_err(g, "allocating read-only va space failed"); | ||
52 | return -ENOMEM; | ||
53 | } | ||
54 | |||
55 | msg.cmd = TEGRA_VGPU_CMD_MAP_SYNCPT; | ||
56 | msg.handle = vgpu_get_handle(g); | ||
57 | p->as_handle = c->vm->handle; | ||
58 | p->gpu_va = vm->syncpt_ro_map_gpu_va; | ||
59 | p->len = g->syncpt_unit_size; | ||
60 | p->offset = 0; | ||
61 | p->prot = TEGRA_VGPU_MAP_PROT_READ_ONLY; | ||
62 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
63 | err = err ? err : msg.ret; | ||
64 | if (err) { | ||
65 | nvgpu_err(g, | ||
66 | "mapping read-only va space failed err %d", | ||
67 | err); | ||
68 | __nvgpu_vm_free_va(c->vm, vm->syncpt_ro_map_gpu_va, | ||
69 | gmmu_page_size_kernel); | ||
70 | vm->syncpt_ro_map_gpu_va = 0; | ||
71 | return err; | ||
72 | } | ||
73 | } | ||
74 | |||
75 | syncpt_buf->gpu_va = __nvgpu_vm_alloc_va(c->vm, g->syncpt_size, | ||
76 | gmmu_page_size_kernel); | ||
77 | if (!syncpt_buf->gpu_va) { | ||
78 | nvgpu_err(g, "allocating syncpt va space failed"); | ||
79 | return -ENOMEM; | ||
80 | } | ||
81 | |||
82 | msg.cmd = TEGRA_VGPU_CMD_MAP_SYNCPT; | ||
83 | msg.handle = vgpu_get_handle(g); | ||
84 | p->as_handle = c->vm->handle; | ||
85 | p->gpu_va = syncpt_buf->gpu_va; | ||
86 | p->len = g->syncpt_size; | ||
87 | p->offset = | ||
88 | nvgpu_nvhost_syncpt_unit_interface_get_byte_offset(syncpt_id); | ||
89 | p->prot = TEGRA_VGPU_MAP_PROT_NONE; | ||
90 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
91 | err = err ? err : msg.ret; | ||
92 | if (err) { | ||
93 | nvgpu_err(g, "mapping syncpt va space failed err %d", err); | ||
94 | __nvgpu_vm_free_va(c->vm, syncpt_buf->gpu_va, | ||
95 | gmmu_page_size_kernel); | ||
96 | return err; | ||
97 | } | ||
98 | |||
99 | return 0; | ||
100 | } | ||
101 | #endif /* CONFIG_TEGRA_GK20A_NVHOST */ | ||
102 | |||
103 | int vgpu_gv11b_init_fifo_setup_hw(struct gk20a *g) | ||
104 | { | ||
105 | struct fifo_gk20a *f = &g->fifo; | ||
106 | int err; | ||
107 | |||
108 | err = vgpu_get_attribute(vgpu_get_handle(g), | ||
109 | TEGRA_VGPU_ATTRIB_MAX_SUBCTX_COUNT, | ||
110 | &f->t19x.max_subctx_count); | ||
111 | if (err) { | ||
112 | nvgpu_err(g, "get max_subctx_count failed %d", err); | ||
113 | return err; | ||
114 | } | ||
115 | |||
116 | return 0; | ||
117 | } | ||