diff options
Diffstat (limited to 'drivers/gpu/nvgpu/vgpu/gr_vgpu.h')
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gr_vgpu.h | 44 |
1 files changed, 44 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/vgpu/gr_vgpu.h b/drivers/gpu/nvgpu/vgpu/gr_vgpu.h index b6df991e..5a5e0928 100644 --- a/drivers/gpu/nvgpu/vgpu/gr_vgpu.h +++ b/drivers/gpu/nvgpu/vgpu/gr_vgpu.h | |||
@@ -23,6 +23,50 @@ | |||
23 | #ifndef _GR_VGPU_H_ | 23 | #ifndef _GR_VGPU_H_ |
24 | #define _GR_VGPU_H_ | 24 | #define _GR_VGPU_H_ |
25 | 25 | ||
26 | #include <nvgpu/types.h> | ||
27 | |||
28 | struct gk20a; | ||
29 | struct channel_gk20a; | ||
30 | struct nvgpu_alloc_obj_ctx_args; | ||
31 | struct gr_gk20a; | ||
32 | struct gr_zcull_info; | ||
33 | struct zbc_entry; | ||
34 | struct zbc_query_params; | ||
35 | struct dbg_session_gk20a; | ||
36 | |||
37 | void vgpu_gr_detect_sm_arch(struct gk20a *g); | ||
38 | void vgpu_gr_free_channel_ctx(struct channel_gk20a *c, bool is_tsg); | ||
39 | int vgpu_gr_alloc_obj_ctx(struct channel_gk20a *c, | ||
40 | struct nvgpu_alloc_obj_ctx_args *args); | ||
41 | int vgpu_gr_bind_ctxsw_zcull(struct gk20a *g, struct gr_gk20a *gr, | ||
42 | struct channel_gk20a *c, u64 zcull_va, | ||
43 | u32 mode); | ||
44 | int vgpu_gr_get_zcull_info(struct gk20a *g, struct gr_gk20a *gr, | ||
45 | struct gr_zcull_info *zcull_params); | ||
46 | u32 vgpu_gr_get_gpc_tpc_mask(struct gk20a *g, u32 gpc_index); | ||
47 | u32 vgpu_gr_get_max_fbps_count(struct gk20a *g); | ||
48 | u32 vgpu_gr_get_fbp_en_mask(struct gk20a *g); | ||
49 | u32 vgpu_gr_get_max_ltc_per_fbp(struct gk20a *g); | ||
50 | u32 vgpu_gr_get_max_lts_per_ltc(struct gk20a *g); | ||
51 | u32 *vgpu_gr_rop_l2_en_mask(struct gk20a *g); | ||
52 | int vgpu_gr_add_zbc(struct gk20a *g, struct gr_gk20a *gr, | ||
53 | struct zbc_entry *zbc_val); | ||
54 | int vgpu_gr_query_zbc(struct gk20a *g, struct gr_gk20a *gr, | ||
55 | struct zbc_query_params *query_params); | ||
56 | int vgpu_gr_set_sm_debug_mode(struct gk20a *g, | ||
57 | struct channel_gk20a *ch, u64 sms, bool enable); | ||
58 | int vgpu_gr_update_smpc_ctxsw_mode(struct gk20a *g, | ||
59 | struct channel_gk20a *ch, bool enable); | ||
60 | int vgpu_gr_update_hwpm_ctxsw_mode(struct gk20a *g, | ||
61 | struct channel_gk20a *ch, bool enable); | ||
62 | int vgpu_gr_clear_sm_error_state(struct gk20a *g, | ||
63 | struct channel_gk20a *ch, u32 sm_id); | ||
64 | int vgpu_gr_suspend_contexts(struct gk20a *g, | ||
65 | struct dbg_session_gk20a *dbg_s, | ||
66 | int *ctx_resident_ch_fd); | ||
67 | int vgpu_gr_resume_contexts(struct gk20a *g, | ||
68 | struct dbg_session_gk20a *dbg_s, | ||
69 | int *ctx_resident_ch_fd); | ||
26 | int vgpu_gr_commit_inst(struct channel_gk20a *c, u64 gpu_va); | 70 | int vgpu_gr_commit_inst(struct channel_gk20a *c, u64 gpu_va); |
27 | 71 | ||
28 | #endif | 72 | #endif |