diff options
Diffstat (limited to 'drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.c')
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.c | 201 |
1 files changed, 201 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.c new file mode 100644 index 00000000..e4437ed2 --- /dev/null +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.c | |||
@@ -0,0 +1,201 @@ | |||
1 | /* | ||
2 | * Virtualized GPU Memory Management | ||
3 | * | ||
4 | * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice shall be included in | ||
14 | * all copies or substantial portions of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
22 | * DEALINGS IN THE SOFTWARE. | ||
23 | */ | ||
24 | |||
25 | #include "vgpu/vgpu.h" | ||
26 | #include "vgpu_mm_gp10b.h" | ||
27 | #include "gk20a/mm_gk20a.h" | ||
28 | |||
29 | #include <nvgpu/bug.h> | ||
30 | |||
31 | int vgpu_gp10b_init_mm_setup_hw(struct gk20a *g) | ||
32 | { | ||
33 | g->mm.bypass_smmu = true; | ||
34 | g->mm.disable_bigpage = true; | ||
35 | return 0; | ||
36 | } | ||
37 | |||
38 | static inline int add_mem_desc(struct tegra_vgpu_mem_desc *mem_desc, | ||
39 | u64 addr, u64 size, size_t *oob_size) | ||
40 | { | ||
41 | if (*oob_size < sizeof(*mem_desc)) | ||
42 | return -ENOMEM; | ||
43 | |||
44 | mem_desc->addr = addr; | ||
45 | mem_desc->length = size; | ||
46 | *oob_size -= sizeof(*mem_desc); | ||
47 | return 0; | ||
48 | } | ||
49 | |||
50 | u64 vgpu_gp10b_locked_gmmu_map(struct vm_gk20a *vm, | ||
51 | u64 map_offset, | ||
52 | struct nvgpu_sgt *sgt, | ||
53 | u64 buffer_offset, | ||
54 | u64 size, | ||
55 | int pgsz_idx, | ||
56 | u8 kind_v, | ||
57 | u32 ctag_offset, | ||
58 | u32 flags, | ||
59 | int rw_flag, | ||
60 | bool clear_ctags, | ||
61 | bool sparse, | ||
62 | bool priv, | ||
63 | struct vm_gk20a_mapping_batch *batch, | ||
64 | enum nvgpu_aperture aperture) | ||
65 | { | ||
66 | int err = 0; | ||
67 | struct gk20a *g = gk20a_from_vm(vm); | ||
68 | struct tegra_vgpu_cmd_msg msg; | ||
69 | struct tegra_vgpu_as_map_ex_params *p = &msg.params.as_map_ex; | ||
70 | struct tegra_vgpu_mem_desc *mem_desc; | ||
71 | u32 page_size = vm->gmmu_page_sizes[pgsz_idx]; | ||
72 | u64 buffer_size = PAGE_ALIGN(size); | ||
73 | u64 space_to_skip = buffer_offset; | ||
74 | u32 mem_desc_count = 0, i; | ||
75 | void *handle = NULL; | ||
76 | size_t oob_size; | ||
77 | u8 prot; | ||
78 | void *sgl; | ||
79 | |||
80 | gk20a_dbg_fn(""); | ||
81 | |||
82 | /* FIXME: add support for sparse mappings */ | ||
83 | |||
84 | if (WARN_ON(!sgt) || WARN_ON(!g->mm.bypass_smmu)) | ||
85 | return 0; | ||
86 | |||
87 | if (space_to_skip & (page_size - 1)) | ||
88 | return 0; | ||
89 | |||
90 | memset(&msg, 0, sizeof(msg)); | ||
91 | |||
92 | /* Allocate (or validate when map_offset != 0) the virtual address. */ | ||
93 | if (!map_offset) { | ||
94 | map_offset = __nvgpu_vm_alloc_va(vm, size, pgsz_idx); | ||
95 | if (!map_offset) { | ||
96 | nvgpu_err(g, "failed to allocate va space"); | ||
97 | err = -ENOMEM; | ||
98 | goto fail; | ||
99 | } | ||
100 | } | ||
101 | |||
102 | handle = tegra_gr_comm_oob_get_ptr(TEGRA_GR_COMM_CTX_CLIENT, | ||
103 | tegra_gr_comm_get_server_vmid(), | ||
104 | TEGRA_VGPU_QUEUE_CMD, | ||
105 | (void **)&mem_desc, &oob_size); | ||
106 | if (!handle) { | ||
107 | err = -EINVAL; | ||
108 | goto fail; | ||
109 | } | ||
110 | sgl = sgt->sgl; | ||
111 | while (sgl) { | ||
112 | u64 phys_addr; | ||
113 | u64 chunk_length; | ||
114 | |||
115 | /* | ||
116 | * Cut out sgl ents for space_to_skip. | ||
117 | */ | ||
118 | if (space_to_skip && | ||
119 | space_to_skip >= nvgpu_sgt_get_length(sgt, sgl)) { | ||
120 | space_to_skip -= nvgpu_sgt_get_length(sgt, sgl); | ||
121 | sgl = nvgpu_sgt_get_next(sgt, sgl); | ||
122 | continue; | ||
123 | } | ||
124 | |||
125 | phys_addr = nvgpu_sgt_get_phys(sgt, sgl) + space_to_skip; | ||
126 | chunk_length = min(size, | ||
127 | nvgpu_sgt_get_length(sgt, sgl) - space_to_skip); | ||
128 | |||
129 | if (add_mem_desc(&mem_desc[mem_desc_count++], phys_addr, | ||
130 | chunk_length, &oob_size)) { | ||
131 | err = -ENOMEM; | ||
132 | goto fail; | ||
133 | } | ||
134 | |||
135 | space_to_skip = 0; | ||
136 | size -= chunk_length; | ||
137 | sgl = nvgpu_sgt_get_next(sgt, sgl); | ||
138 | |||
139 | if (size == 0) | ||
140 | break; | ||
141 | } | ||
142 | |||
143 | if (rw_flag == gk20a_mem_flag_read_only) | ||
144 | prot = TEGRA_VGPU_MAP_PROT_READ_ONLY; | ||
145 | else if (rw_flag == gk20a_mem_flag_write_only) | ||
146 | prot = TEGRA_VGPU_MAP_PROT_WRITE_ONLY; | ||
147 | else | ||
148 | prot = TEGRA_VGPU_MAP_PROT_NONE; | ||
149 | |||
150 | if (pgsz_idx == gmmu_page_size_kernel) { | ||
151 | if (page_size == vm->gmmu_page_sizes[gmmu_page_size_small]) { | ||
152 | pgsz_idx = gmmu_page_size_small; | ||
153 | } else if (page_size == | ||
154 | vm->gmmu_page_sizes[gmmu_page_size_big]) { | ||
155 | pgsz_idx = gmmu_page_size_big; | ||
156 | } else { | ||
157 | nvgpu_err(g, "invalid kernel page size %d", | ||
158 | page_size); | ||
159 | goto fail; | ||
160 | } | ||
161 | } | ||
162 | |||
163 | msg.cmd = TEGRA_VGPU_CMD_AS_MAP_EX; | ||
164 | msg.handle = vgpu_get_handle(g); | ||
165 | p->handle = vm->handle; | ||
166 | p->gpu_va = map_offset; | ||
167 | p->size = buffer_size; | ||
168 | p->mem_desc_count = mem_desc_count; | ||
169 | p->pgsz_idx = pgsz_idx; | ||
170 | p->iova = 0; | ||
171 | p->kind = kind_v; | ||
172 | p->cacheable = (flags & NVGPU_AS_MAP_BUFFER_FLAGS_CACHEABLE) ? 1 : 0; | ||
173 | p->prot = prot; | ||
174 | p->ctag_offset = ctag_offset; | ||
175 | p->clear_ctags = clear_ctags; | ||
176 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
177 | if (err || msg.ret) | ||
178 | goto fail; | ||
179 | |||
180 | /* TLB invalidate handled on server side */ | ||
181 | |||
182 | tegra_gr_comm_oob_put_ptr(handle); | ||
183 | return map_offset; | ||
184 | fail: | ||
185 | if (handle) | ||
186 | tegra_gr_comm_oob_put_ptr(handle); | ||
187 | nvgpu_err(g, "Failed: err=%d, msg.ret=%d", err, msg.ret); | ||
188 | nvgpu_err(g, | ||
189 | " Map: %-5s GPU virt %#-12llx +%#-9llx " | ||
190 | "phys offset: %#-4llx; pgsz: %3dkb perm=%-2s | " | ||
191 | "kind=%#02x APT=%-6s", | ||
192 | vm->name, map_offset, buffer_size, buffer_offset, | ||
193 | vm->gmmu_page_sizes[pgsz_idx] >> 10, | ||
194 | nvgpu_gmmu_perm_str(rw_flag), | ||
195 | kind_v, "SYSMEM"); | ||
196 | for (i = 0; i < mem_desc_count; i++) | ||
197 | nvgpu_err(g, " > 0x%010llx + 0x%llx", | ||
198 | mem_desc[i].addr, mem_desc[i].length); | ||
199 | |||
200 | return 0; | ||
201 | } | ||