diff options
Diffstat (limited to 'drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.c')
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.c | 188 |
1 files changed, 188 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.c new file mode 100644 index 00000000..66fda2d9 --- /dev/null +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.c | |||
@@ -0,0 +1,188 @@ | |||
1 | /* | ||
2 | * Virtualized GPU Memory Management | ||
3 | * | ||
4 | * Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms and conditions of the GNU General Public License, | ||
8 | * version 2, as published by the Free Software Foundation. | ||
9 | * | ||
10 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
13 | * more details. | ||
14 | */ | ||
15 | |||
16 | #include <linux/dma-mapping.h> | ||
17 | #include "vgpu/vgpu.h" | ||
18 | #include "vgpu_mm_gp10b.h" | ||
19 | #include "gk20a/semaphore_gk20a.h" | ||
20 | #include "gk20a/mm_gk20a.h" | ||
21 | |||
22 | static int vgpu_gp10b_init_mm_setup_hw(struct gk20a *g) | ||
23 | { | ||
24 | g->mm.bypass_smmu = true; | ||
25 | g->mm.disable_bigpage = true; | ||
26 | return 0; | ||
27 | } | ||
28 | |||
29 | static inline int add_mem_desc(struct tegra_vgpu_mem_desc *mem_desc, | ||
30 | u64 addr, u64 size, size_t *oob_size) | ||
31 | { | ||
32 | if (*oob_size < sizeof(*mem_desc)) | ||
33 | return -ENOMEM; | ||
34 | |||
35 | mem_desc->addr = addr; | ||
36 | mem_desc->length = size; | ||
37 | *oob_size -= sizeof(*mem_desc); | ||
38 | return 0; | ||
39 | } | ||
40 | |||
41 | static u64 vgpu_gp10b_locked_gmmu_map(struct vm_gk20a *vm, | ||
42 | u64 map_offset, | ||
43 | struct sg_table *sgt, | ||
44 | u64 buffer_offset, | ||
45 | u64 size, | ||
46 | int pgsz_idx, | ||
47 | u8 kind_v, | ||
48 | u32 ctag_offset, | ||
49 | u32 flags, | ||
50 | int rw_flag, | ||
51 | bool clear_ctags, | ||
52 | bool sparse, | ||
53 | bool priv, | ||
54 | struct vm_gk20a_mapping_batch *batch, | ||
55 | enum gk20a_aperture aperture) | ||
56 | { | ||
57 | int err = 0; | ||
58 | struct device *d = dev_from_vm(vm); | ||
59 | struct gk20a *g = gk20a_from_vm(vm); | ||
60 | struct tegra_vgpu_cmd_msg msg; | ||
61 | struct tegra_vgpu_as_map_ex_params *p = &msg.params.as_map_ex; | ||
62 | struct tegra_vgpu_mem_desc *mem_desc; | ||
63 | u32 page_size = vm->gmmu_page_sizes[pgsz_idx]; | ||
64 | u64 space_to_skip = buffer_offset; | ||
65 | u64 buffer_size = 0; | ||
66 | u32 mem_desc_count = 0; | ||
67 | struct scatterlist *sgl; | ||
68 | void *handle = NULL; | ||
69 | size_t oob_size; | ||
70 | u8 prot; | ||
71 | |||
72 | gk20a_dbg_fn(""); | ||
73 | |||
74 | /* FIXME: add support for sparse mappings */ | ||
75 | |||
76 | if (WARN_ON(!sgt) || WARN_ON(!g->mm.bypass_smmu)) | ||
77 | return 0; | ||
78 | |||
79 | if (space_to_skip & (page_size - 1)) | ||
80 | return 0; | ||
81 | |||
82 | /* Allocate (or validate when map_offset != 0) the virtual address. */ | ||
83 | if (!map_offset) { | ||
84 | map_offset = gk20a_vm_alloc_va(vm, size, pgsz_idx); | ||
85 | if (!map_offset) { | ||
86 | gk20a_err(d, "failed to allocate va space"); | ||
87 | err = -ENOMEM; | ||
88 | goto fail; | ||
89 | } | ||
90 | } | ||
91 | |||
92 | handle = tegra_gr_comm_oob_get_ptr(TEGRA_GR_COMM_CTX_CLIENT, | ||
93 | tegra_gr_comm_get_server_vmid(), | ||
94 | TEGRA_VGPU_QUEUE_CMD, | ||
95 | (void **)&mem_desc, &oob_size); | ||
96 | if (!handle) { | ||
97 | err = -EINVAL; | ||
98 | goto fail; | ||
99 | } | ||
100 | |||
101 | sgl = sgt->sgl; | ||
102 | while (space_to_skip && sgl && | ||
103 | (space_to_skip + page_size > sgl->length)) { | ||
104 | space_to_skip -= sgl->length; | ||
105 | sgl = sg_next(sgl); | ||
106 | } | ||
107 | WARN_ON(!sgl); | ||
108 | |||
109 | if (add_mem_desc(&mem_desc[mem_desc_count++], | ||
110 | sg_phys(sgl) + space_to_skip, | ||
111 | sgl->length - space_to_skip, | ||
112 | &oob_size)) { | ||
113 | err = -ENOMEM; | ||
114 | goto fail; | ||
115 | } | ||
116 | buffer_size += sgl->length - space_to_skip; | ||
117 | |||
118 | sgl = sg_next(sgl); | ||
119 | while (sgl && buffer_size < size) { | ||
120 | if (add_mem_desc(&mem_desc[mem_desc_count++], sg_phys(sgl), | ||
121 | sgl->length, &oob_size)) { | ||
122 | err = -ENOMEM; | ||
123 | goto fail; | ||
124 | } | ||
125 | |||
126 | buffer_size += sgl->length; | ||
127 | sgl = sg_next(sgl); | ||
128 | } | ||
129 | |||
130 | if (rw_flag == gk20a_mem_flag_read_only) | ||
131 | prot = TEGRA_VGPU_MAP_PROT_READ_ONLY; | ||
132 | else if (rw_flag == gk20a_mem_flag_write_only) | ||
133 | prot = TEGRA_VGPU_MAP_PROT_WRITE_ONLY; | ||
134 | else | ||
135 | prot = TEGRA_VGPU_MAP_PROT_NONE; | ||
136 | |||
137 | if (pgsz_idx == gmmu_page_size_kernel) { | ||
138 | if (page_size == vm->gmmu_page_sizes[gmmu_page_size_small]) { | ||
139 | pgsz_idx = gmmu_page_size_small; | ||
140 | } else if (page_size == | ||
141 | vm->gmmu_page_sizes[gmmu_page_size_big]) { | ||
142 | pgsz_idx = gmmu_page_size_big; | ||
143 | } else { | ||
144 | gk20a_err(d, "invalid kernel page size %d\n", | ||
145 | page_size); | ||
146 | goto fail; | ||
147 | } | ||
148 | } | ||
149 | |||
150 | msg.cmd = TEGRA_VGPU_CMD_AS_MAP_EX; | ||
151 | msg.handle = vgpu_get_handle(g); | ||
152 | p->handle = vm->handle; | ||
153 | p->gpu_va = map_offset; | ||
154 | p->size = size; | ||
155 | p->mem_desc_count = mem_desc_count; | ||
156 | p->pgsz_idx = pgsz_idx; | ||
157 | p->iova = 0; | ||
158 | p->kind = kind_v; | ||
159 | p->cacheable = | ||
160 | (flags & NVGPU_MAP_BUFFER_FLAGS_CACHEABLE_TRUE) ? 1 : 0; | ||
161 | p->prot = prot; | ||
162 | p->ctag_offset = ctag_offset; | ||
163 | p->clear_ctags = clear_ctags; | ||
164 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
165 | if (err || msg.ret) | ||
166 | goto fail; | ||
167 | |||
168 | /* TLB invalidate handled on server side */ | ||
169 | |||
170 | tegra_gr_comm_oob_put_ptr(handle); | ||
171 | return map_offset; | ||
172 | fail: | ||
173 | if (handle) | ||
174 | tegra_gr_comm_oob_put_ptr(handle); | ||
175 | gk20a_err(d, "%s: failed with err=%d\n", __func__, err); | ||
176 | return 0; | ||
177 | } | ||
178 | |||
179 | void vgpu_gp10b_init_mm_ops(struct gpu_ops *gops) | ||
180 | { | ||
181 | gk20a_dbg_fn(""); | ||
182 | |||
183 | gops->mm.gmmu_map = vgpu_gp10b_locked_gmmu_map; | ||
184 | gops->mm.init_mm_setup_hw = vgpu_gp10b_init_mm_setup_hw; | ||
185 | |||
186 | /* FIXME: add support for sparse mappings */ | ||
187 | gops->mm.support_sparse = NULL; | ||
188 | } | ||