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path: root/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
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Diffstat (limited to 'drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c')
-rw-r--r--drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c16
1 files changed, 16 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
index 78aef699..2b4b3463 100644
--- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
+++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
@@ -59,6 +59,7 @@
59#include "gp10b/gr_ctx_gp10b.h" 59#include "gp10b/gr_ctx_gp10b.h"
60#include "gp10b/fifo_gp10b.h" 60#include "gp10b/fifo_gp10b.h"
61#include "gp10b/regops_gp10b.h" 61#include "gp10b/regops_gp10b.h"
62#include "gp10b/clk_arb_gp10b.h"
62 63
63#include "gm20b/gr_gm20b.h" 64#include "gm20b/gr_gm20b.h"
64#include "gm20b/fifo_gm20b.h" 65#include "gm20b/fifo_gm20b.h"
@@ -450,6 +451,15 @@ static const struct gpu_ops vgpu_gp10b_ops = {
450 .reset_engine = NULL, 451 .reset_engine = NULL,
451 .is_engine_in_reset = NULL, 452 .is_engine_in_reset = NULL,
452 }, 453 },
454 .clk_arb = {
455 .get_arbiter_clk_domains = gp10b_get_arbiter_clk_domains,
456 .get_arbiter_f_points = gp10b_get_arbiter_f_points,
457 .get_arbiter_clk_range = gp10b_get_arbiter_clk_range,
458 .get_arbiter_clk_default = gp10b_get_arbiter_clk_default,
459 .arbiter_clk_init = gp10b_init_clk_arbiter,
460 .clk_arb_run_arbiter_cb = gp10b_clk_arb_run_arbiter_cb,
461 .clk_arb_cleanup = gp10b_clk_arb_cleanup,
462 },
453 .regops = { 463 .regops = {
454 .exec_regops = vgpu_exec_regops, 464 .exec_regops = vgpu_exec_regops,
455 .get_global_whitelist_ranges = 465 .get_global_whitelist_ranges =
@@ -558,6 +568,7 @@ static const struct gpu_ops vgpu_gp10b_ops = {
558int vgpu_gp10b_init_hal(struct gk20a *g) 568int vgpu_gp10b_init_hal(struct gk20a *g)
559{ 569{
560 struct gpu_ops *gops = &g->ops; 570 struct gpu_ops *gops = &g->ops;
571 struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
561 572
562 gops->ltc = vgpu_gp10b_ops.ltc; 573 gops->ltc = vgpu_gp10b_ops.ltc;
563 gops->ce2 = vgpu_gp10b_ops.ce2; 574 gops->ce2 = vgpu_gp10b_ops.ce2;
@@ -573,6 +584,7 @@ int vgpu_gp10b_init_hal(struct gk20a *g)
573 gops->pramin = vgpu_gp10b_ops.pramin; 584 gops->pramin = vgpu_gp10b_ops.pramin;
574 gops->therm = vgpu_gp10b_ops.therm; 585 gops->therm = vgpu_gp10b_ops.therm;
575 gops->pmu = vgpu_gp10b_ops.pmu; 586 gops->pmu = vgpu_gp10b_ops.pmu;
587 gops->clk_arb = vgpu_gp10b_ops.clk_arb;
576 gops->regops = vgpu_gp10b_ops.regops; 588 gops->regops = vgpu_gp10b_ops.regops;
577 gops->mc = vgpu_gp10b_ops.mc; 589 gops->mc = vgpu_gp10b_ops.mc;
578 gops->debug = vgpu_gp10b_ops.debug; 590 gops->debug = vgpu_gp10b_ops.debug;
@@ -642,6 +654,10 @@ int vgpu_gp10b_init_hal(struct gk20a *g)
642 __nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false); 654 __nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false);
643 g->pmu_lsf_pmu_wpr_init_done = 0; 655 g->pmu_lsf_pmu_wpr_init_done = 0;
644 656
657 if (priv->constants.can_set_clkrate) {
658 gops->clk.support_clk_freq_controller = true;
659 }
660
645 g->name = "gp10b"; 661 g->name = "gp10b";
646 662
647 return 0; 663 return 0;