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path: root/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c
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Diffstat (limited to 'drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c')
-rw-r--r--drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c34
1 files changed, 17 insertions, 17 deletions
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c
index fc8b16cb..d3ad6280 100644
--- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c
+++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c
@@ -80,16 +80,16 @@ int vgpu_gr_gp10b_alloc_gr_ctx(struct gk20a *g,
80 gr_ctx = *__gr_ctx; 80 gr_ctx = *__gr_ctx;
81 81
82 if (flags & NVGPU_OBJ_CTX_FLAGS_SUPPORT_GFXP) 82 if (flags & NVGPU_OBJ_CTX_FLAGS_SUPPORT_GFXP)
83 graphics_preempt_mode = NVGPU_GRAPHICS_PREEMPTION_MODE_GFXP; 83 graphics_preempt_mode = NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP;
84 if (flags & NVGPU_OBJ_CTX_FLAGS_SUPPORT_CILP) 84 if (flags & NVGPU_OBJ_CTX_FLAGS_SUPPORT_CILP)
85 compute_preempt_mode = NVGPU_COMPUTE_PREEMPTION_MODE_CILP; 85 compute_preempt_mode = NVGPU_PREEMPTION_MODE_COMPUTE_CILP;
86 86
87 if (priv->constants.force_preempt_mode && !graphics_preempt_mode && 87 if (priv->constants.force_preempt_mode && !graphics_preempt_mode &&
88 !compute_preempt_mode) { 88 !compute_preempt_mode) {
89 graphics_preempt_mode = PASCAL_A == class ? 89 graphics_preempt_mode = PASCAL_A == class ?
90 NVGPU_GRAPHICS_PREEMPTION_MODE_GFXP : 0; 90 NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP : 0;
91 compute_preempt_mode = PASCAL_COMPUTE_A == class ? 91 compute_preempt_mode = PASCAL_COMPUTE_A == class ?
92 NVGPU_COMPUTE_PREEMPTION_MODE_CTA : 0; 92 NVGPU_PREEMPTION_MODE_COMPUTE_CTA : 0;
93 } 93 }
94 94
95 if (graphics_preempt_mode || compute_preempt_mode) { 95 if (graphics_preempt_mode || compute_preempt_mode) {
@@ -127,23 +127,23 @@ int vgpu_gr_gp10b_set_ctxsw_preemption_mode(struct gk20a *g,
127 int err = 0; 127 int err = 0;
128 128
129 if (class == PASCAL_A && g->gr.t18x.ctx_vars.force_preemption_gfxp) 129 if (class == PASCAL_A && g->gr.t18x.ctx_vars.force_preemption_gfxp)
130 graphics_preempt_mode = NVGPU_GRAPHICS_PREEMPTION_MODE_GFXP; 130 graphics_preempt_mode = NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP;
131 131
132 if (class == PASCAL_COMPUTE_A && 132 if (class == PASCAL_COMPUTE_A &&
133 g->gr.t18x.ctx_vars.force_preemption_cilp) 133 g->gr.t18x.ctx_vars.force_preemption_cilp)
134 compute_preempt_mode = NVGPU_COMPUTE_PREEMPTION_MODE_CILP; 134 compute_preempt_mode = NVGPU_PREEMPTION_MODE_COMPUTE_CILP;
135 135
136 /* check for invalid combinations */ 136 /* check for invalid combinations */
137 if ((graphics_preempt_mode == 0) && (compute_preempt_mode == 0)) 137 if ((graphics_preempt_mode == 0) && (compute_preempt_mode == 0))
138 return -EINVAL; 138 return -EINVAL;
139 139
140 if ((graphics_preempt_mode == NVGPU_GRAPHICS_PREEMPTION_MODE_GFXP) && 140 if ((graphics_preempt_mode == NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP) &&
141 (compute_preempt_mode == NVGPU_COMPUTE_PREEMPTION_MODE_CILP)) 141 (compute_preempt_mode == NVGPU_PREEMPTION_MODE_COMPUTE_CILP))
142 return -EINVAL; 142 return -EINVAL;
143 143
144 /* set preemption modes */ 144 /* set preemption modes */
145 switch (graphics_preempt_mode) { 145 switch (graphics_preempt_mode) {
146 case NVGPU_GRAPHICS_PREEMPTION_MODE_GFXP: 146 case NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP:
147 { 147 {
148 u32 spill_size = 148 u32 spill_size =
149 gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v() * 149 gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v() *
@@ -213,11 +213,11 @@ int vgpu_gr_gp10b_set_ctxsw_preemption_mode(struct gk20a *g,
213 desc->gpu_va; 213 desc->gpu_va;
214 p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_BETACB] = desc->size; 214 p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_BETACB] = desc->size;
215 215
216 gr_ctx->graphics_preempt_mode = NVGPU_GRAPHICS_PREEMPTION_MODE_GFXP; 216 gr_ctx->graphics_preempt_mode = NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP;
217 p->mode = TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_GFX_GFXP; 217 p->mode = TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_GFX_GFXP;
218 break; 218 break;
219 } 219 }
220 case NVGPU_GRAPHICS_PREEMPTION_MODE_WFI: 220 case NVGPU_PREEMPTION_MODE_GRAPHICS_WFI:
221 gr_ctx->graphics_preempt_mode = graphics_preempt_mode; 221 gr_ctx->graphics_preempt_mode = graphics_preempt_mode;
222 break; 222 break;
223 223
@@ -227,20 +227,20 @@ int vgpu_gr_gp10b_set_ctxsw_preemption_mode(struct gk20a *g,
227 227
228 if (class == PASCAL_COMPUTE_A) { 228 if (class == PASCAL_COMPUTE_A) {
229 switch (compute_preempt_mode) { 229 switch (compute_preempt_mode) {
230 case NVGPU_COMPUTE_PREEMPTION_MODE_WFI: 230 case NVGPU_PREEMPTION_MODE_COMPUTE_WFI:
231 gr_ctx->compute_preempt_mode = 231 gr_ctx->compute_preempt_mode =
232 NVGPU_COMPUTE_PREEMPTION_MODE_WFI; 232 NVGPU_PREEMPTION_MODE_COMPUTE_WFI;
233 p->mode = TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_WFI; 233 p->mode = TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_WFI;
234 break; 234 break;
235 case NVGPU_COMPUTE_PREEMPTION_MODE_CTA: 235 case NVGPU_PREEMPTION_MODE_COMPUTE_CTA:
236 gr_ctx->compute_preempt_mode = 236 gr_ctx->compute_preempt_mode =
237 NVGPU_COMPUTE_PREEMPTION_MODE_CTA; 237 NVGPU_PREEMPTION_MODE_COMPUTE_CTA;
238 p->mode = 238 p->mode =
239 TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_COMPUTE_CTA; 239 TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_COMPUTE_CTA;
240 break; 240 break;
241 case NVGPU_COMPUTE_PREEMPTION_MODE_CILP: 241 case NVGPU_PREEMPTION_MODE_COMPUTE_CILP:
242 gr_ctx->compute_preempt_mode = 242 gr_ctx->compute_preempt_mode =
243 NVGPU_COMPUTE_PREEMPTION_MODE_CILP; 243 NVGPU_PREEMPTION_MODE_COMPUTE_CILP;
244 p->mode = 244 p->mode =
245 TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_COMPUTE_CILP; 245 TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_COMPUTE_CILP;
246 break; 246 break;