diff options
Diffstat (limited to 'drivers/gpu/nvgpu/vgpu/fifo_vgpu.h')
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/fifo_vgpu.h | 65 |
1 files changed, 65 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.h b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.h new file mode 100644 index 00000000..7633ad95 --- /dev/null +++ b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.h | |||
@@ -0,0 +1,65 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | |||
23 | #ifndef _FIFO_VGPU_H_ | ||
24 | #define _FIFO_VGPU_H_ | ||
25 | |||
26 | #include <nvgpu/types.h> | ||
27 | |||
28 | struct gk20a; | ||
29 | struct channel_gk20a; | ||
30 | struct fifo_gk20a; | ||
31 | struct tsg_gk20a; | ||
32 | |||
33 | int vgpu_init_fifo_setup_hw(struct gk20a *g); | ||
34 | void vgpu_channel_bind(struct channel_gk20a *ch); | ||
35 | void vgpu_channel_unbind(struct channel_gk20a *ch); | ||
36 | int vgpu_channel_alloc_inst(struct gk20a *g, struct channel_gk20a *ch); | ||
37 | void vgpu_channel_free_inst(struct gk20a *g, struct channel_gk20a *ch); | ||
38 | void vgpu_channel_enable(struct channel_gk20a *ch); | ||
39 | void vgpu_channel_disable(struct channel_gk20a *ch); | ||
40 | int vgpu_channel_setup_ramfc(struct channel_gk20a *ch, u64 gpfifo_base, | ||
41 | u32 gpfifo_entries, | ||
42 | unsigned long acquire_timeout, u32 flags); | ||
43 | int vgpu_fifo_init_engine_info(struct fifo_gk20a *f); | ||
44 | int vgpu_fifo_preempt_channel(struct gk20a *g, u32 chid); | ||
45 | int vgpu_fifo_preempt_tsg(struct gk20a *g, u32 tsgid); | ||
46 | int vgpu_fifo_update_runlist(struct gk20a *g, u32 runlist_id, | ||
47 | u32 chid, bool add, bool wait_for_finish); | ||
48 | int vgpu_fifo_wait_engine_idle(struct gk20a *g); | ||
49 | int vgpu_fifo_set_runlist_interleave(struct gk20a *g, | ||
50 | u32 id, | ||
51 | bool is_tsg, | ||
52 | u32 runlist_id, | ||
53 | u32 new_level); | ||
54 | int vgpu_channel_set_timeslice(struct channel_gk20a *ch, u32 timeslice); | ||
55 | int vgpu_fifo_force_reset_ch(struct channel_gk20a *ch, | ||
56 | u32 err_code, bool verbose); | ||
57 | u32 vgpu_fifo_default_timeslice_us(struct gk20a *g); | ||
58 | int vgpu_tsg_open(struct tsg_gk20a *tsg); | ||
59 | int vgpu_tsg_bind_channel(struct tsg_gk20a *tsg, | ||
60 | struct channel_gk20a *ch); | ||
61 | int vgpu_tsg_unbind_channel(struct channel_gk20a *ch); | ||
62 | int vgpu_tsg_set_timeslice(struct tsg_gk20a *tsg, u32 timeslice); | ||
63 | int vgpu_enable_tsg(struct tsg_gk20a *tsg); | ||
64 | |||
65 | #endif | ||