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path: root/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c
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Diffstat (limited to 'drivers/gpu/nvgpu/vgpu/fifo_vgpu.c')
-rw-r--r--drivers/gpu/nvgpu/vgpu/fifo_vgpu.c15
1 files changed, 6 insertions, 9 deletions
diff --git a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c
index 4055d5af..60ab628a 100644
--- a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c
+++ b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c
@@ -641,9 +641,8 @@ int vgpu_fifo_force_reset_ch(struct channel_gk20a *ch,
641 641
642 nvgpu_log_fn(g, " "); 642 nvgpu_log_fn(g, " ");
643 643
644 if (gk20a_is_channel_marked_as_tsg(ch)) { 644 tsg = tsg_gk20a_from_ch(ch);
645 tsg = &g->fifo.tsg[ch->tsgid]; 645 if (tsg != NULL) {
646
647 nvgpu_rwsem_down_read(&tsg->ch_list_lock); 646 nvgpu_rwsem_down_read(&tsg->ch_list_lock);
648 647
649 nvgpu_list_for_each_entry(ch_tsg, &tsg->ch_list, 648 nvgpu_list_for_each_entry(ch_tsg, &tsg->ch_list,
@@ -658,8 +657,7 @@ int vgpu_fifo_force_reset_ch(struct channel_gk20a *ch,
658 657
659 nvgpu_rwsem_up_read(&tsg->ch_list_lock); 658 nvgpu_rwsem_up_read(&tsg->ch_list_lock);
660 } else { 659 } else {
661 g->ops.fifo.set_error_notifier(ch, err_code); 660 nvgpu_err(g, "chid: %d is not bound to tsg", ch->chid);
662 gk20a_channel_set_timedout(ch);
663 } 661 }
664 662
665 msg.cmd = TEGRA_VGPU_CMD_CHANNEL_FORCE_RESET; 663 msg.cmd = TEGRA_VGPU_CMD_CHANNEL_FORCE_RESET;
@@ -698,9 +696,8 @@ static void vgpu_fifo_set_ctx_mmu_error_ch_tsg(struct gk20a *g,
698 struct tsg_gk20a *tsg = NULL; 696 struct tsg_gk20a *tsg = NULL;
699 struct channel_gk20a *ch_tsg = NULL; 697 struct channel_gk20a *ch_tsg = NULL;
700 698
701 if (gk20a_is_channel_marked_as_tsg(ch)) { 699 tsg = tsg_gk20a_from_ch(ch);
702 tsg = &g->fifo.tsg[ch->tsgid]; 700 if (tsg != NULL) {
703
704 nvgpu_rwsem_down_read(&tsg->ch_list_lock); 701 nvgpu_rwsem_down_read(&tsg->ch_list_lock);
705 702
706 nvgpu_list_for_each_entry(ch_tsg, &tsg->ch_list, 703 nvgpu_list_for_each_entry(ch_tsg, &tsg->ch_list,
@@ -713,7 +710,7 @@ static void vgpu_fifo_set_ctx_mmu_error_ch_tsg(struct gk20a *g,
713 710
714 nvgpu_rwsem_up_read(&tsg->ch_list_lock); 711 nvgpu_rwsem_up_read(&tsg->ch_list_lock);
715 } else { 712 } else {
716 vgpu_fifo_set_ctx_mmu_error_ch(g, ch); 713 nvgpu_err(g, "chid: %d is not bound to tsg", ch->chid);
717 } 714 }
718} 715}
719 716