diff options
Diffstat (limited to 'drivers/gpu/nvgpu/vgpu/fifo_vgpu.c')
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/fifo_vgpu.c | 32 |
1 files changed, 16 insertions, 16 deletions
diff --git a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c index 8d12bb42..55b3de07 100644 --- a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c | |||
@@ -34,7 +34,7 @@ static void vgpu_channel_bind(struct channel_gk20a *ch) | |||
34 | &msg.params.channel_config; | 34 | &msg.params.channel_config; |
35 | int err; | 35 | int err; |
36 | 36 | ||
37 | gk20a_dbg_info("bind channel %d", ch->hw_chid); | 37 | gk20a_dbg_info("bind channel %d", ch->chid); |
38 | 38 | ||
39 | msg.cmd = TEGRA_VGPU_CMD_CHANNEL_BIND; | 39 | msg.cmd = TEGRA_VGPU_CMD_CHANNEL_BIND; |
40 | msg.handle = vgpu_get_handle(ch->g); | 40 | msg.handle = vgpu_get_handle(ch->g); |
@@ -76,7 +76,7 @@ static int vgpu_channel_alloc_inst(struct gk20a *g, struct channel_gk20a *ch) | |||
76 | 76 | ||
77 | msg.cmd = TEGRA_VGPU_CMD_CHANNEL_ALLOC_HWCTX; | 77 | msg.cmd = TEGRA_VGPU_CMD_CHANNEL_ALLOC_HWCTX; |
78 | msg.handle = vgpu_get_handle(g); | 78 | msg.handle = vgpu_get_handle(g); |
79 | p->id = ch->hw_chid; | 79 | p->id = ch->chid; |
80 | p->pid = (u64)current->tgid; | 80 | p->pid = (u64)current->tgid; |
81 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | 81 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); |
82 | if (err || msg.ret) { | 82 | if (err || msg.ret) { |
@@ -407,10 +407,10 @@ int vgpu_init_fifo_support(struct gk20a *g) | |||
407 | return err; | 407 | return err; |
408 | } | 408 | } |
409 | 409 | ||
410 | static int vgpu_fifo_preempt_channel(struct gk20a *g, u32 hw_chid) | 410 | static int vgpu_fifo_preempt_channel(struct gk20a *g, u32 chid) |
411 | { | 411 | { |
412 | struct fifo_gk20a *f = &g->fifo; | 412 | struct fifo_gk20a *f = &g->fifo; |
413 | struct channel_gk20a *ch = &f->channel[hw_chid]; | 413 | struct channel_gk20a *ch = &f->channel[chid]; |
414 | struct tegra_vgpu_cmd_msg msg; | 414 | struct tegra_vgpu_cmd_msg msg; |
415 | struct tegra_vgpu_channel_config_params *p = | 415 | struct tegra_vgpu_channel_config_params *p = |
416 | &msg.params.channel_config; | 416 | &msg.params.channel_config; |
@@ -428,7 +428,7 @@ static int vgpu_fifo_preempt_channel(struct gk20a *g, u32 hw_chid) | |||
428 | 428 | ||
429 | if (err || msg.ret) { | 429 | if (err || msg.ret) { |
430 | nvgpu_err(g, | 430 | nvgpu_err(g, |
431 | "preempt channel %d failed", hw_chid); | 431 | "preempt channel %d failed", chid); |
432 | err = -ENOMEM; | 432 | err = -ENOMEM; |
433 | } | 433 | } |
434 | 434 | ||
@@ -497,7 +497,7 @@ done: | |||
497 | } | 497 | } |
498 | 498 | ||
499 | static int vgpu_fifo_update_runlist_locked(struct gk20a *g, u32 runlist_id, | 499 | static int vgpu_fifo_update_runlist_locked(struct gk20a *g, u32 runlist_id, |
500 | u32 hw_chid, bool add, | 500 | u32 chid, bool add, |
501 | bool wait_for_finish) | 501 | bool wait_for_finish) |
502 | { | 502 | { |
503 | struct fifo_gk20a *f = &g->fifo; | 503 | struct fifo_gk20a *f = &g->fifo; |
@@ -511,19 +511,19 @@ static int vgpu_fifo_update_runlist_locked(struct gk20a *g, u32 runlist_id, | |||
511 | 511 | ||
512 | /* valid channel, add/remove it from active list. | 512 | /* valid channel, add/remove it from active list. |
513 | Otherwise, keep active list untouched for suspend/resume. */ | 513 | Otherwise, keep active list untouched for suspend/resume. */ |
514 | if (hw_chid != (u32)~0) { | 514 | if (chid != (u32)~0) { |
515 | if (add) { | 515 | if (add) { |
516 | if (test_and_set_bit(hw_chid, | 516 | if (test_and_set_bit(chid, |
517 | runlist->active_channels) == 1) | 517 | runlist->active_channels) == 1) |
518 | return 0; | 518 | return 0; |
519 | } else { | 519 | } else { |
520 | if (test_and_clear_bit(hw_chid, | 520 | if (test_and_clear_bit(chid, |
521 | runlist->active_channels) == 0) | 521 | runlist->active_channels) == 0) |
522 | return 0; | 522 | return 0; |
523 | } | 523 | } |
524 | } | 524 | } |
525 | 525 | ||
526 | if (hw_chid != (u32)~0 || /* add/remove a valid channel */ | 526 | if (chid != (u32)~0 || /* add/remove a valid channel */ |
527 | add /* resume to add all channels back */) { | 527 | add /* resume to add all channels back */) { |
528 | u32 chid; | 528 | u32 chid; |
529 | 529 | ||
@@ -544,10 +544,10 @@ static int vgpu_fifo_update_runlist_locked(struct gk20a *g, u32 runlist_id, | |||
544 | 544 | ||
545 | /* add/remove a channel from runlist | 545 | /* add/remove a channel from runlist |
546 | special cases below: runlist->active_channels will NOT be changed. | 546 | special cases below: runlist->active_channels will NOT be changed. |
547 | (hw_chid == ~0 && !add) means remove all active channels from runlist. | 547 | (chid == ~0 && !add) means remove all active channels from runlist. |
548 | (hw_chid == ~0 && add) means restore all active channels on runlist. */ | 548 | (chid == ~0 && add) means restore all active channels on runlist. */ |
549 | static int vgpu_fifo_update_runlist(struct gk20a *g, u32 runlist_id, | 549 | static int vgpu_fifo_update_runlist(struct gk20a *g, u32 runlist_id, |
550 | u32 hw_chid, bool add, bool wait_for_finish) | 550 | u32 chid, bool add, bool wait_for_finish) |
551 | { | 551 | { |
552 | struct fifo_runlist_info_gk20a *runlist = NULL; | 552 | struct fifo_runlist_info_gk20a *runlist = NULL; |
553 | struct fifo_gk20a *f = &g->fifo; | 553 | struct fifo_gk20a *f = &g->fifo; |
@@ -559,7 +559,7 @@ static int vgpu_fifo_update_runlist(struct gk20a *g, u32 runlist_id, | |||
559 | 559 | ||
560 | nvgpu_mutex_acquire(&runlist->mutex); | 560 | nvgpu_mutex_acquire(&runlist->mutex); |
561 | 561 | ||
562 | ret = vgpu_fifo_update_runlist_locked(g, runlist_id, hw_chid, add, | 562 | ret = vgpu_fifo_update_runlist_locked(g, runlist_id, chid, add, |
563 | wait_for_finish); | 563 | wait_for_finish); |
564 | 564 | ||
565 | nvgpu_mutex_release(&runlist->mutex); | 565 | nvgpu_mutex_release(&runlist->mutex); |
@@ -580,7 +580,7 @@ static int vgpu_channel_set_priority(struct channel_gk20a *ch, u32 priority) | |||
580 | &msg.params.channel_priority; | 580 | &msg.params.channel_priority; |
581 | int err; | 581 | int err; |
582 | 582 | ||
583 | gk20a_dbg_info("channel %d set priority %u", ch->hw_chid, priority); | 583 | gk20a_dbg_info("channel %d set priority %u", ch->chid, priority); |
584 | 584 | ||
585 | msg.cmd = TEGRA_VGPU_CMD_CHANNEL_SET_PRIORITY; | 585 | msg.cmd = TEGRA_VGPU_CMD_CHANNEL_SET_PRIORITY; |
586 | msg.handle = vgpu_get_handle(ch->g); | 586 | msg.handle = vgpu_get_handle(ch->g); |
@@ -739,7 +739,7 @@ int vgpu_fifo_isr(struct gk20a *g, struct tegra_vgpu_fifo_intr_info *info) | |||
739 | nvgpu_err(g, "fifo intr (%d) on ch %u", | 739 | nvgpu_err(g, "fifo intr (%d) on ch %u", |
740 | info->type, info->chid); | 740 | info->type, info->chid); |
741 | 741 | ||
742 | trace_gk20a_channel_reset(ch->hw_chid, ch->tsgid); | 742 | trace_gk20a_channel_reset(ch->chid, ch->tsgid); |
743 | 743 | ||
744 | switch (info->type) { | 744 | switch (info->type) { |
745 | case TEGRA_VGPU_FIFO_INTR_PBDMA: | 745 | case TEGRA_VGPU_FIFO_INTR_PBDMA: |