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path: root/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c
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Diffstat (limited to 'drivers/gpu/nvgpu/vgpu/fifo_vgpu.c')
-rw-r--r--drivers/gpu/nvgpu/vgpu/fifo_vgpu.c22
1 files changed, 15 insertions, 7 deletions
diff --git a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c
index 11f389fb..ffa16cd3 100644
--- a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c
+++ b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c
@@ -160,22 +160,29 @@ static int vgpu_channel_setup_ramfc(struct channel_gk20a *ch, u64 gpfifo_base,
160 return (err || msg.ret) ? -ENOMEM : 0; 160 return (err || msg.ret) ? -ENOMEM : 0;
161} 161}
162 162
163static int init_engine_info(struct fifo_gk20a *f) 163static int vgpu_fifo_init_engine_info(struct fifo_gk20a *f)
164{ 164{
165 struct fifo_engine_info_gk20a *gr_info; 165 struct fifo_engine_info_gk20a *gr_info;
166 struct fifo_engine_info_gk20a *ce_info;
166 const u32 gr_sw_id = ENGINE_GR_GK20A; 167 const u32 gr_sw_id = ENGINE_GR_GK20A;
168 const u32 ce_sw_id = ENGINE_GRCE_GK20A;
167 169
168 gk20a_dbg_fn(""); 170 gk20a_dbg_fn("");
169 171
170 /* all we really care about finding is the graphics entry */ 172 f->num_engines = 2;
171 /* especially early on in sim it probably thinks it has more */
172 f->num_engines = 1;
173 173
174 gr_info = f->engine_info + gr_sw_id; 174 gr_info = &f->engine_info[0];
175 175
176 /* FIXME: retrieve this from server */ 176 /* FIXME: retrieve this from server */
177 gr_info->runlist_id = 0; 177 gr_info->runlist_id = 0;
178 f->active_engines_list[0] = gr_sw_id; 178 gr_info->engine_enum = gr_sw_id;
179 f->active_engines_list[0] = 0;
180
181 ce_info = &f->engine_info[1];
182 ce_info->runlist_id = 0;
183 ce_info->inst_id = 2;
184 ce_info->engine_enum = ce_sw_id;
185 f->active_engines_list[1] = 1;
179 186
180 return 0; 187 return 0;
181} 188}
@@ -292,7 +299,7 @@ static int vgpu_init_fifo_setup_sw(struct gk20a *g)
292 } 299 }
293 memset(f->active_engines_list, 0xff, (f->max_engines * sizeof(u32))); 300 memset(f->active_engines_list, 0xff, (f->max_engines * sizeof(u32)));
294 301
295 init_engine_info(f); 302 g->ops.fifo.init_engine_info(f);
296 303
297 init_runlist(g, f); 304 init_runlist(g, f);
298 305
@@ -778,4 +785,5 @@ void vgpu_init_fifo_ops(struct gpu_ops *gops)
778 gops->fifo.set_runlist_interleave = vgpu_fifo_set_runlist_interleave; 785 gops->fifo.set_runlist_interleave = vgpu_fifo_set_runlist_interleave;
779 gops->fifo.channel_set_timeslice = vgpu_channel_set_timeslice; 786 gops->fifo.channel_set_timeslice = vgpu_channel_set_timeslice;
780 gops->fifo.force_reset_ch = vgpu_fifo_force_reset_ch; 787 gops->fifo.force_reset_ch = vgpu_fifo_force_reset_ch;
788 gops->fifo.init_engine_info = vgpu_fifo_init_engine_info;
781} 789}