diff options
Diffstat (limited to 'drivers/gpu/nvgpu/vgpu/css_vgpu.c')
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/css_vgpu.c | 240 |
1 files changed, 240 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/vgpu/css_vgpu.c b/drivers/gpu/nvgpu/vgpu/css_vgpu.c new file mode 100644 index 00000000..7362fc6f --- /dev/null +++ b/drivers/gpu/nvgpu/vgpu/css_vgpu.c | |||
@@ -0,0 +1,240 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | #if defined(CONFIG_GK20A_CYCLE_STATS) | ||
23 | |||
24 | #include <linux/tegra-ivc.h> | ||
25 | #include <linux/tegra_vgpu.h> | ||
26 | #include <uapi/linux/nvgpu.h> | ||
27 | |||
28 | #include "gk20a/gk20a.h" | ||
29 | #include "gk20a/channel_gk20a.h" | ||
30 | #include "gk20a/css_gr_gk20a.h" | ||
31 | #include "common/linux/platform_gk20a.h" | ||
32 | #include "vgpu.h" | ||
33 | #include "css_vgpu.h" | ||
34 | |||
35 | static struct tegra_hv_ivm_cookie *css_cookie; | ||
36 | |||
37 | static struct tegra_hv_ivm_cookie *vgpu_css_reserve_mempool(struct gk20a *g) | ||
38 | { | ||
39 | struct device *dev = dev_from_gk20a(g); | ||
40 | struct device_node *np = dev->of_node; | ||
41 | struct of_phandle_args args; | ||
42 | struct device_node *hv_np; | ||
43 | struct tegra_hv_ivm_cookie *cookie; | ||
44 | u32 mempool; | ||
45 | int err; | ||
46 | |||
47 | err = of_parse_phandle_with_fixed_args(np, | ||
48 | "mempool-css", 1, 0, &args); | ||
49 | if (err) { | ||
50 | nvgpu_err(g, "dt missing mempool-css"); | ||
51 | return ERR_PTR(err); | ||
52 | } | ||
53 | |||
54 | hv_np = args.np; | ||
55 | mempool = args.args[0]; | ||
56 | cookie = tegra_hv_mempool_reserve(hv_np, mempool); | ||
57 | if (IS_ERR_OR_NULL(cookie)) { | ||
58 | nvgpu_err(g, "mempool %u reserve failed", mempool); | ||
59 | return ERR_PTR(-EINVAL); | ||
60 | } | ||
61 | return cookie; | ||
62 | } | ||
63 | |||
64 | u32 vgpu_css_get_buffer_size(struct gk20a *g) | ||
65 | { | ||
66 | struct tegra_hv_ivm_cookie *cookie; | ||
67 | u32 size; | ||
68 | |||
69 | nvgpu_log_fn(g, " "); | ||
70 | |||
71 | if (css_cookie) { | ||
72 | nvgpu_log_info(g, "buffer size = %llu", css_cookie->size); | ||
73 | return (u32)css_cookie->size; | ||
74 | } | ||
75 | |||
76 | cookie = vgpu_css_reserve_mempool(g); | ||
77 | if (IS_ERR(cookie)) | ||
78 | return 0; | ||
79 | |||
80 | size = cookie->size; | ||
81 | |||
82 | tegra_hv_mempool_unreserve(cookie); | ||
83 | nvgpu_log_info(g, "buffer size = %u", size); | ||
84 | return size; | ||
85 | } | ||
86 | |||
87 | static int vgpu_css_init_snapshot_buffer(struct gr_gk20a *gr) | ||
88 | { | ||
89 | struct gk20a *g = gr->g; | ||
90 | struct gk20a_cs_snapshot *data = gr->cs_data; | ||
91 | void *buf = NULL; | ||
92 | int err; | ||
93 | |||
94 | gk20a_dbg_fn(""); | ||
95 | |||
96 | if (data->hw_snapshot) | ||
97 | return 0; | ||
98 | |||
99 | css_cookie = vgpu_css_reserve_mempool(g); | ||
100 | if (IS_ERR(css_cookie)) | ||
101 | return PTR_ERR(css_cookie); | ||
102 | |||
103 | /* Make sure buffer size is large enough */ | ||
104 | if (css_cookie->size < CSS_MIN_HW_SNAPSHOT_SIZE) { | ||
105 | nvgpu_info(g, "mempool size %lld too small", | ||
106 | css_cookie->size); | ||
107 | err = -ENOMEM; | ||
108 | goto fail; | ||
109 | } | ||
110 | |||
111 | buf = ioremap_cache(css_cookie->ipa, css_cookie->size); | ||
112 | if (!buf) { | ||
113 | nvgpu_info(g, "ioremap_cache failed"); | ||
114 | err = -EINVAL; | ||
115 | goto fail; | ||
116 | } | ||
117 | |||
118 | data->hw_snapshot = buf; | ||
119 | data->hw_end = data->hw_snapshot + | ||
120 | css_cookie->size / sizeof(struct gk20a_cs_snapshot_fifo_entry); | ||
121 | data->hw_get = data->hw_snapshot; | ||
122 | memset(data->hw_snapshot, 0xff, css_cookie->size); | ||
123 | return 0; | ||
124 | fail: | ||
125 | tegra_hv_mempool_unreserve(css_cookie); | ||
126 | css_cookie = NULL; | ||
127 | return err; | ||
128 | } | ||
129 | |||
130 | void vgpu_css_release_snapshot_buffer(struct gr_gk20a *gr) | ||
131 | { | ||
132 | struct gk20a_cs_snapshot *data = gr->cs_data; | ||
133 | |||
134 | if (!data->hw_snapshot) | ||
135 | return; | ||
136 | |||
137 | iounmap(data->hw_snapshot); | ||
138 | data->hw_snapshot = NULL; | ||
139 | |||
140 | tegra_hv_mempool_unreserve(css_cookie); | ||
141 | css_cookie = NULL; | ||
142 | |||
143 | gk20a_dbg_info("cyclestats(vgpu): buffer for snapshots released\n"); | ||
144 | } | ||
145 | |||
146 | int vgpu_css_flush_snapshots(struct channel_gk20a *ch, | ||
147 | u32 *pending, bool *hw_overflow) | ||
148 | { | ||
149 | struct gk20a *g = ch->g; | ||
150 | struct tegra_vgpu_cmd_msg msg = {}; | ||
151 | struct tegra_vgpu_channel_cyclestats_snapshot_params *p; | ||
152 | struct gr_gk20a *gr = &g->gr; | ||
153 | struct gk20a_cs_snapshot *data = gr->cs_data; | ||
154 | int err; | ||
155 | |||
156 | gk20a_dbg_fn(""); | ||
157 | |||
158 | msg.cmd = TEGRA_VGPU_CMD_CHANNEL_CYCLESTATS_SNAPSHOT; | ||
159 | msg.handle = vgpu_get_handle(g); | ||
160 | p = &msg.params.cyclestats_snapshot; | ||
161 | p->handle = ch->virt_ctx; | ||
162 | p->subcmd = NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT_CMD_FLUSH; | ||
163 | p->buf_info = (uintptr_t)data->hw_get - (uintptr_t)data->hw_snapshot; | ||
164 | |||
165 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
166 | |||
167 | err = (err || msg.ret) ? -1 : 0; | ||
168 | |||
169 | *pending = p->buf_info; | ||
170 | *hw_overflow = p->hw_overflow; | ||
171 | |||
172 | return err; | ||
173 | } | ||
174 | |||
175 | static int vgpu_css_attach(struct channel_gk20a *ch, | ||
176 | struct gk20a_cs_snapshot_client *cs_client) | ||
177 | { | ||
178 | struct gk20a *g = ch->g; | ||
179 | struct tegra_vgpu_cmd_msg msg = {}; | ||
180 | struct tegra_vgpu_channel_cyclestats_snapshot_params *p = | ||
181 | &msg.params.cyclestats_snapshot; | ||
182 | int err; | ||
183 | |||
184 | gk20a_dbg_fn(""); | ||
185 | |||
186 | msg.cmd = TEGRA_VGPU_CMD_CHANNEL_CYCLESTATS_SNAPSHOT; | ||
187 | msg.handle = vgpu_get_handle(g); | ||
188 | p->handle = ch->virt_ctx; | ||
189 | p->subcmd = NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT_CMD_ATTACH; | ||
190 | p->perfmon_count = cs_client->perfmon_count; | ||
191 | |||
192 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
193 | err = err ? err : msg.ret; | ||
194 | if (err) | ||
195 | nvgpu_err(g, "failed"); | ||
196 | else | ||
197 | cs_client->perfmon_start = p->perfmon_start; | ||
198 | |||
199 | return err; | ||
200 | } | ||
201 | |||
202 | int vgpu_css_detach(struct channel_gk20a *ch, | ||
203 | struct gk20a_cs_snapshot_client *cs_client) | ||
204 | { | ||
205 | struct gk20a *g = ch->g; | ||
206 | struct tegra_vgpu_cmd_msg msg = {}; | ||
207 | struct tegra_vgpu_channel_cyclestats_snapshot_params *p = | ||
208 | &msg.params.cyclestats_snapshot; | ||
209 | int err; | ||
210 | |||
211 | gk20a_dbg_fn(""); | ||
212 | |||
213 | msg.cmd = TEGRA_VGPU_CMD_CHANNEL_CYCLESTATS_SNAPSHOT; | ||
214 | msg.handle = vgpu_get_handle(g); | ||
215 | p->handle = ch->virt_ctx; | ||
216 | p->subcmd = NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT_CMD_DETACH; | ||
217 | p->perfmon_start = cs_client->perfmon_start; | ||
218 | p->perfmon_count = cs_client->perfmon_count; | ||
219 | |||
220 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
221 | err = err ? err : msg.ret; | ||
222 | if (err) | ||
223 | nvgpu_err(g, "failed"); | ||
224 | |||
225 | return err; | ||
226 | } | ||
227 | |||
228 | int vgpu_css_enable_snapshot_buffer(struct channel_gk20a *ch, | ||
229 | struct gk20a_cs_snapshot_client *cs_client) | ||
230 | { | ||
231 | int ret; | ||
232 | |||
233 | ret = vgpu_css_attach(ch, cs_client); | ||
234 | if (ret) | ||
235 | return ret; | ||
236 | |||
237 | ret = vgpu_css_init_snapshot_buffer(&ch->g->gr); | ||
238 | return ret; | ||
239 | } | ||
240 | #endif /* CONFIG_GK20A_CYCLE_STATS */ | ||