diff options
Diffstat (limited to 'drivers/gpu/nvgpu/tegra/linux')
-rw-r--r-- | drivers/gpu/nvgpu/tegra/linux/platform_gk20a_tegra.c | 170 |
1 files changed, 5 insertions, 165 deletions
diff --git a/drivers/gpu/nvgpu/tegra/linux/platform_gk20a_tegra.c b/drivers/gpu/nvgpu/tegra/linux/platform_gk20a_tegra.c index 2bb7d5cb..a8a1451a 100644 --- a/drivers/gpu/nvgpu/tegra/linux/platform_gk20a_tegra.c +++ b/drivers/gpu/nvgpu/tegra/linux/platform_gk20a_tegra.c | |||
@@ -26,12 +26,9 @@ | |||
26 | #include <linux/dma-attrs.h> | 26 | #include <linux/dma-attrs.h> |
27 | #include <linux/nvmap.h> | 27 | #include <linux/nvmap.h> |
28 | #include <linux/reset.h> | 28 | #include <linux/reset.h> |
29 | #if defined(CONFIG_TEGRA_CLK_FRAMEWORK) || defined(CONFIG_TEGRA_DVFS) | 29 | #if defined(CONFIG_TEGRA_DVFS) |
30 | #include <linux/tegra_soctherm.h> | 30 | #include <linux/tegra_soctherm.h> |
31 | #endif | 31 | #endif |
32 | #if defined(CONFIG_TEGRA_CLK_FRAMEWORK) | ||
33 | #include <linux/platform/tegra/dvfs.h> | ||
34 | #endif | ||
35 | #include <linux/platform/tegra/common.h> | 32 | #include <linux/platform/tegra/common.h> |
36 | #include <linux/platform/tegra/mc.h> | 33 | #include <linux/platform/tegra/mc.h> |
37 | #include <linux/clk/tegra.h> | 34 | #include <linux/clk/tegra.h> |
@@ -391,137 +388,7 @@ done: | |||
391 | 388 | ||
392 | #endif | 389 | #endif |
393 | 390 | ||
394 | #ifdef CONFIG_TEGRA_CLK_FRAMEWORK | 391 | #if defined(CONFIG_TEGRA_DVFS) |
395 | /* | ||
396 | * gk20a_tegra_railgate() | ||
397 | * | ||
398 | * Gate (disable) gk20a power rail | ||
399 | */ | ||
400 | |||
401 | static int gk20a_tegra_railgate(struct device *dev) | ||
402 | { | ||
403 | struct gk20a *g = get_gk20a(dev); | ||
404 | struct gk20a_platform *platform = dev_get_drvdata(dev); | ||
405 | int ret = 0; | ||
406 | |||
407 | if (g->is_fmodel || | ||
408 | !tegra_dvfs_is_rail_up(platform->gpu_rail)) | ||
409 | return 0; | ||
410 | |||
411 | tegra_mc_flush(MC_CLIENT_GPU); | ||
412 | |||
413 | udelay(10); | ||
414 | |||
415 | /* enable clamp */ | ||
416 | pmc_write(0x1, PMC_GPU_RG_CNTRL_0); | ||
417 | pmc_read(PMC_GPU_RG_CNTRL_0); | ||
418 | |||
419 | udelay(10); | ||
420 | |||
421 | platform->reset_assert(dev); | ||
422 | |||
423 | udelay(10); | ||
424 | |||
425 | /* | ||
426 | * GPCPLL is already disabled before entering this function; reference | ||
427 | * clocks are enabled until now - disable them just before rail gating | ||
428 | */ | ||
429 | clk_disable(platform->clk[0]); | ||
430 | clk_disable(platform->clk[1]); | ||
431 | |||
432 | udelay(10); | ||
433 | |||
434 | if (tegra_dvfs_is_rail_up(platform->gpu_rail)) { | ||
435 | ret = tegra_dvfs_rail_power_down(platform->gpu_rail); | ||
436 | if (ret) | ||
437 | goto err_power_off; | ||
438 | } else | ||
439 | pr_info("No GPU regulator?\n"); | ||
440 | |||
441 | return 0; | ||
442 | |||
443 | err_power_off: | ||
444 | nvgpu_err(get_gk20a(dev), "Could not railgate GPU"); | ||
445 | return ret; | ||
446 | } | ||
447 | |||
448 | |||
449 | /* | ||
450 | * gk20a_tegra_unrailgate() | ||
451 | * | ||
452 | * Ungate (enable) gk20a power rail | ||
453 | */ | ||
454 | |||
455 | static int gk20a_tegra_unrailgate(struct device *dev) | ||
456 | { | ||
457 | struct gk20a *g = get_gk20a(dev); | ||
458 | struct gk20a_platform *platform = dev_get_drvdata(dev); | ||
459 | int ret = 0; | ||
460 | bool first = false; | ||
461 | |||
462 | if (g->is_fmodel) | ||
463 | return 0; | ||
464 | |||
465 | if (!platform->gpu_rail) { | ||
466 | platform->gpu_rail = tegra_dvfs_get_rail_by_name("vdd_gpu"); | ||
467 | if (IS_ERR_OR_NULL(platform->gpu_rail)) { | ||
468 | WARN(1, "No GPU regulator?\n"); | ||
469 | return -EINVAL; | ||
470 | } | ||
471 | first = true; | ||
472 | } | ||
473 | |||
474 | ret = tegra_dvfs_rail_power_up(platform->gpu_rail); | ||
475 | if (ret) | ||
476 | return ret; | ||
477 | |||
478 | if (!first) { | ||
479 | ret = clk_enable(platform->clk[0]); | ||
480 | if (ret) { | ||
481 | nvgpu_err(platform->g, "could not turn on gpu pll"); | ||
482 | goto err_clk_on; | ||
483 | } | ||
484 | ret = clk_enable(platform->clk[1]); | ||
485 | if (ret) { | ||
486 | nvgpu_err(platform->g, "could not turn on pwr clock"); | ||
487 | goto err_clk_on; | ||
488 | } | ||
489 | } | ||
490 | |||
491 | udelay(10); | ||
492 | |||
493 | platform->reset_assert(dev); | ||
494 | |||
495 | udelay(10); | ||
496 | |||
497 | pmc_write(0, PMC_GPU_RG_CNTRL_0); | ||
498 | pmc_read(PMC_GPU_RG_CNTRL_0); | ||
499 | |||
500 | udelay(10); | ||
501 | |||
502 | platform->reset_deassert(dev); | ||
503 | |||
504 | /* Flush MC after boot/railgate/SC7 */ | ||
505 | tegra_mc_flush(MC_CLIENT_GPU); | ||
506 | |||
507 | udelay(10); | ||
508 | |||
509 | tegra_mc_flush_done(MC_CLIENT_GPU); | ||
510 | |||
511 | udelay(10); | ||
512 | |||
513 | return 0; | ||
514 | |||
515 | err_clk_on: | ||
516 | tegra_dvfs_rail_power_down(platform->gpu_rail); | ||
517 | |||
518 | return ret; | ||
519 | } | ||
520 | |||
521 | #endif | ||
522 | |||
523 | |||
524 | #if defined(CONFIG_TEGRA_CLK_FRAMEWORK) || defined(CONFIG_TEGRA_DVFS) | ||
525 | /* | 392 | /* |
526 | * gk20a_tegra_is_railgated() | 393 | * gk20a_tegra_is_railgated() |
527 | * | 394 | * |
@@ -619,17 +486,6 @@ static int gm20b_tegra_unrailgate(struct device *dev) | |||
619 | if (g->is_fmodel) | 486 | if (g->is_fmodel) |
620 | return 0; | 487 | return 0; |
621 | 488 | ||
622 | #ifdef CONFIG_TEGRA_CLK_FRAMEWORK | ||
623 | if (!platform->gpu_rail) { | ||
624 | platform->gpu_rail = tegra_dvfs_get_rail_by_name(GPU_RAIL_NAME); | ||
625 | if (IS_ERR_OR_NULL(platform->gpu_rail)) { | ||
626 | WARN(1, "No GPU regulator?\n"); | ||
627 | return -EINVAL; | ||
628 | } | ||
629 | first = true; | ||
630 | } | ||
631 | #endif | ||
632 | |||
633 | ret = tegra_dvfs_rail_power_up(platform->gpu_rail); | 489 | ret = tegra_dvfs_rail_power_up(platform->gpu_rail); |
634 | if (ret) | 490 | if (ret) |
635 | return ret; | 491 | return ret; |
@@ -713,16 +569,10 @@ static struct { | |||
713 | char *name; | 569 | char *name; |
714 | unsigned long default_rate; | 570 | unsigned long default_rate; |
715 | } tegra_gk20a_clocks[] = { | 571 | } tegra_gk20a_clocks[] = { |
716 | #ifdef CONFIG_TEGRA_CLK_FRAMEWORK | ||
717 | {"PLLG_ref", UINT_MAX}, | ||
718 | {"pwr", 204000000}, | ||
719 | {"emc", UINT_MAX}, | ||
720 | #elif defined(CONFIG_COMMON_CLK) | ||
721 | {"gpu_ref", UINT_MAX}, | 572 | {"gpu_ref", UINT_MAX}, |
722 | {"pll_p_out5", 204000000}, | 573 | {"pll_p_out5", 204000000}, |
723 | {"emc", UINT_MAX}, | 574 | {"emc", UINT_MAX}, |
724 | {"fuse", UINT_MAX}, | 575 | {"fuse", UINT_MAX}, |
725 | #endif | ||
726 | }; | 576 | }; |
727 | 577 | ||
728 | 578 | ||
@@ -1021,7 +871,7 @@ static int gk20a_tegra_suspend(struct device *dev) | |||
1021 | return 0; | 871 | return 0; |
1022 | } | 872 | } |
1023 | 873 | ||
1024 | #if defined(CONFIG_TEGRA_CLK_FRAMEWORK) || defined(CONFIG_COMMON_CLK) | 874 | #if defined(CONFIG_COMMON_CLK) |
1025 | static long gk20a_round_clk_rate(struct device *dev, unsigned long rate) | 875 | static long gk20a_round_clk_rate(struct device *dev, unsigned long rate) |
1026 | { | 876 | { |
1027 | struct gk20a_platform *platform = gk20a_get_platform(dev); | 877 | struct gk20a_platform *platform = gk20a_get_platform(dev); |
@@ -1073,11 +923,6 @@ struct gk20a_platform gk20a_tegra_platform = { | |||
1073 | 923 | ||
1074 | /* power management callbacks */ | 924 | /* power management callbacks */ |
1075 | .suspend = gk20a_tegra_suspend, | 925 | .suspend = gk20a_tegra_suspend, |
1076 | #ifdef CONFIG_TEGRA_CLK_FRAMEWORK | ||
1077 | .railgate = gk20a_tegra_railgate, | ||
1078 | .unrailgate = gk20a_tegra_unrailgate, | ||
1079 | .is_railgated = gk20a_tegra_is_railgated, | ||
1080 | #endif | ||
1081 | 926 | ||
1082 | .busy = gk20a_tegra_busy, | 927 | .busy = gk20a_tegra_busy, |
1083 | .idle = gk20a_tegra_idle, | 928 | .idle = gk20a_tegra_idle, |
@@ -1085,11 +930,6 @@ struct gk20a_platform gk20a_tegra_platform = { | |||
1085 | .reset_assert = gk20a_tegra_reset_assert, | 930 | .reset_assert = gk20a_tegra_reset_assert, |
1086 | .reset_deassert = gk20a_tegra_reset_deassert, | 931 | .reset_deassert = gk20a_tegra_reset_deassert, |
1087 | 932 | ||
1088 | #ifdef CONFIG_TEGRA_CLK_FRAMEWORK | ||
1089 | .clk_round_rate = gk20a_round_clk_rate, | ||
1090 | .get_clk_freqs = gk20a_clk_get_freqs, | ||
1091 | #endif | ||
1092 | |||
1093 | /* frequency scaling configuration */ | 933 | /* frequency scaling configuration */ |
1094 | .prescale = gk20a_tegra_prescale, | 934 | .prescale = gk20a_tegra_prescale, |
1095 | .postscale = gk20a_tegra_postscale, | 935 | .postscale = gk20a_tegra_postscale, |
@@ -1130,7 +970,7 @@ struct gk20a_platform gm20b_tegra_platform = { | |||
1130 | /* power management callbacks */ | 970 | /* power management callbacks */ |
1131 | .suspend = gk20a_tegra_suspend, | 971 | .suspend = gk20a_tegra_suspend, |
1132 | 972 | ||
1133 | #if defined(CONFIG_TEGRA_CLK_FRAMEWORK) || defined(CONFIG_TEGRA_DVFS) | 973 | #if defined(CONFIG_TEGRA_DVFS) |
1134 | .railgate = gm20b_tegra_railgate, | 974 | .railgate = gm20b_tegra_railgate, |
1135 | .unrailgate = gm20b_tegra_unrailgate, | 975 | .unrailgate = gm20b_tegra_unrailgate, |
1136 | .is_railgated = gk20a_tegra_is_railgated, | 976 | .is_railgated = gk20a_tegra_is_railgated, |
@@ -1147,7 +987,7 @@ struct gk20a_platform gm20b_tegra_platform = { | |||
1147 | .reset_deassert = gk20a_tegra_reset_deassert, | 987 | .reset_deassert = gk20a_tegra_reset_deassert, |
1148 | #endif | 988 | #endif |
1149 | 989 | ||
1150 | #if defined(CONFIG_TEGRA_CLK_FRAMEWORK) || defined(CONFIG_COMMON_CLK) | 990 | #if defined(CONFIG_COMMON_CLK) |
1151 | .clk_round_rate = gk20a_round_clk_rate, | 991 | .clk_round_rate = gk20a_round_clk_rate, |
1152 | .get_clk_freqs = gk20a_clk_get_freqs, | 992 | .get_clk_freqs = gk20a_clk_get_freqs, |
1153 | #endif | 993 | #endif |